Explaining and Understanding the sequential circuits

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Explaining and Understanding the sequential circuits

© All Rights Reserved

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Sequential circuits

Sequential circuits

Outputs = f(inputs, past inputs, past outputs)

Basis for building "memory" into logic circuits

Door combination lock is an example of a sequential circuit

State is memory

State is an "output" and an "input" to combinational logic

Combination storage elements are also memory

new equal reset

value

C1 C2 C3

mux comb. logic

multiplexer

control

comparator state clock

equal open/closed

Circuits with feedback

What stops values from cycling around endlessly

X1 Z1

X2 Z2

switching

network

Xn Zn

Simplest circuits with feedback

Will hold value as long as it has power applied

"1"

"stored value"

"0"

Selectively break feedback path

Load new value into cell

"remember"

"data"

Memory with cross-coupled gates

Cross-coupled NOR gates

Similar to inverter pair, with capability to force output to 0

(reset=1) or 1 (set=1)

R Q

Q

R

S Q'

Cross-coupled NAND gates S

(reset=0) or 1 (set=0)

S' Q

Q

S'

R' Q'

R'

Timing behavior

R Q

S Q'

R

S

Q

\Q

State behavior of R-S latch

Q Q' Q Q'

0 1 1 0

S R Q

0 0 hold

0 1 0

Q Q'

1 0 1

0 0

1 1 unstable

Q Q'

1 1

Theoretical R-S latch behavior

SR=10

SR=00 SR=00

SR=01 SR=10

Q Q' SR=01 Q Q'

0 1 1 0

SR=01 SR=10

SR=11

State diagram

States: possible values Q Q'

SR=11 0 0 SR=11

Transitions: changes

based on inputs SR=00

SR=00 SR=11

SR=01 SR=10

between states 00 and 11 1 1

Observed R-S latch behavior

One of R or S usually changes first

Ambiguously returns to state 0-1 or 1-0

A so-called "race condition"

Or non-deterministic transition

SR=10

SR=00 SR=00

SR=01 SR=10

Q Q' SR=01 Q Q'

0 1 1 0

SR=01 SR=10

SR=11

Q Q'

SR=11 0 0 SR=11

SR=00 SR=00

R-S latch analysis

Break feedback path

R Q Q(t)

S Q(t+)

S Q' R

S R Q(t) Q(t+)

0 0 0 0 S

hold

0 0 1 1

0 0 X 1

0 1 0 0 reset

0 1 1 0 Q(t) 1 0 X 1

1 0 0 1 set

R

1 0 1 1

1 1 0 X not allowed characteristic equation

1 1 1 X Q(t+) = S + R Q(t)

Gated R-S latch

inputs matter R' R

Q

Otherwise, the

slightest glitch on R enable'

or S while enable is Q'

S' S

low could cause

change in value

stored

Set Reset

100

S'

R'

enable'

Q

Q'

Clocks

Wait long enough for inputs (R' and S') to settle

Then allow to have effect on value stored

Clocks are regular periodic signals

Period (time between ticks)

Duty-cycle (time clock is high between ticks - expressed as

% of period)

duty cycle (in this case, 50%)

period

Clocks(Cont.)

Can't let R and S change while clock is active

(allowing R and S to pass)

Only have half of clock period for signal changes

to propagate

Signals must be stable for the other half of clock

period

R' R

Q stable changing stable changing stable

R' and S'

clock'

Q' clock

S' S

Cascading latches

How to stop changes from racing through chain?

Need to control flow of data from one latch to the

next

Advance from one latch per clock period

Worry about logic between latches (arrows) that is

too fast

R R Q' R Q'

S S Q S Q

clock

Master-Slave structure

Break flow by alternating clocks (like an air-lock)

Use positive clock to latch inputs into one R-S latch

Use negative clock to change outputs with another R-S latch

View pair as one basic unit

master-slave flip-flop

twice as much logic

output changes a few gate delays after the falling edge of clock

but does not affect any cascaded flip-flops

P'

R R Q' R Q'

S S Q S Q

P

clock

The 1s catching problem

0-1-0 glitch on R or S while clock is high "caught"

by master stage

Leads to constraints on logic to be hazard-free

1s master stage slave stage

Set Reset catch R R Q' P' R Q'

S S S Q S Q

P

R clock

CLK

P Master

P' Outputs

Q Slave

Q' Outputs

D flip-flop

Eliminates 1s catching problem

Can't just hold previous value (must have new value ready

every clock period)

Value of D just before clock goes low is what is stored in

flip-flop

Can make R-S flip-flop by adding logic to make D = S + R' Q

P'

R Q' R Q' Q'

D S Q S Q Q

P

clock

10 gates

Edge-triggered flip-flops

More efficient solution: only 6 gates

sensitive to inputs only near edge of clock signal

(not while high)

D D

holds D' when negative edge-triggered D

clock goes low flip-flop (D-FF)

0

4-5 gate delays

R

Q must respect setup and hold time

constraints to successfully

clock=1 capture input

Q

S

0

holds D when characteristic equation

clock goes low

D Q(t+1) = D

D

Edge-triggered flip-flops(Cont.)

Step-by-step analysis

D D D D

D D

R R

Q Q

Clk=0 Clk=0

S S

D D

D D new D D

new D old D

when clock goes high-to-low when clock is low

data is latched data is held

Edge-triggered flip-flops(Cont.)

0

1

0 1

0 The edge of the clock is used to

1

0

sample the "D" input & send it to

"Q (positive edge triggering).

At all other times the output Q

is independent of the input D

(just stores previously sampled

value).

The input must be stable for a

short time before the clock

edge.

Edge-triggered flip-flops(Cont.)

Positive edge-triggered

Inputs sampled on rising edge; outputs change after

rising edge

Negative edge-triggered flip-flops

Inputs sampled on falling edge; outputs change after

falling edge

100

D

CLK

Qpos

positive edge-triggered FF

Qpos'

Qneg

negative edge-triggered FF

Qneg'

Comparison of latches and flip-flops

D Q

CLK D

positive

edge-triggered

flip-flop CLK

Qedge

D Q

G Qlatch

CLK

transparent

(level-sensitive)

latch behavior is the same unless input changes

while the clock is high

Comparison of latches and flip-flops(Cont.)

unclocked always propagation delay from input change

latch

latch (Tsu/Th around falling or clock edge (whichever is later)

edge of clock)

master-slave clock high propagation delay from falling edge

flip-flop (Tsu/Th around falling of clock

edge of clock)

negative clock hi-to-lo transition propagation delay from falling edge

edge-triggered (Tsu/Th around falling of clock

flip-flop edge of clock)

Clock skew

The problem

Correct behavior assumes next state of all storage

elements determined by all storage elements at the same

time

This is difficult in high-performance systems because time

for clock to arrive at flip-flop is comparable to delays

through logic

Effect of skew on cascaded flip-flops:

100

In

CLK1 is a delayed

Q0 version of CLK0

Q1

CLK0

CLK1

original state: IN = 0, Q0 = 1, Q1 = 1

due to skew, next state becomes: Q0 = 0, Q1 = 0, and not Q0 = 0, Q1 = 1

Meta-stability and asynchronous inputs

Inputs, state, and outputs sampled or changed in relation to a

common reference signal (called the clock)

E.g., master/slave, edge-triggered

Asynchronous circuits

Inputs, state, and outputs sampled or changed independently of

a common reference signal (glitches/hazards a major concern)

E.g., R-S latch

Asynchronous inputs to synchronous circuits

Inputs can change at any time, will not meet setup/hold times

Dangerous, synchronous inputs are greatly preferred

Cannot be avoided (e.g., reset signal, memory wait, user input)

Synchronization failure

FF may enter a meta-stable state neither a logic 0 nor 1

May stay in this state an indefinite amount of time

Is not likely in practice but has some probability

logic 1

logic 0

logic 0 logic 1

that the FF output will get stuck synchronizer failure and eventual

in an in-between state decay to steady state

Dealing with synchronization failure

can be reduced

slow down the system clock: this gives the synchronizer

more time to decay into a steady state; synchronizer

failure becomes a big problem for very high speed systems

use fastest possible logic technology in the synchronizer:

this makes for a very sharp "peak" upon which to balance

cascade two synchronizers: this effectively synchronizes

twice (both would have to fail)

asynchronous D Q synchronized

D Q

input input

Clk

synchronous system

Handling asynchronous inputs

more than one flip-flop

Synchronize as soon as possible and then treat as

synchronous signal

Clocked Synchronizer

Synchronous

System

Async Q0 Async Q0

Input D Q Input D Q D Q

Clock Clock

Q1 D Q Q1

D Q

Clock Clock

Handling asynchronous inputs(Cont.)

Input changes too close to clock edge (violating

setup time constraint)

In

In is asynchronous and

fans out to D0 and D1

Q0

one FF catches the

signal, one does not

Q1

inconsistent state may

be reached!

CLK

Flip-Flop features

Reset (set state to 0) R

Synchronous: Dnew = R' Dold (when next clock edge arrives)

Asynchronous: doesn't wait for clock, quick but dangerous

Preset or set (set state to 1) S (or sometimes P)

Synchronous: Dnew = Dold + S (when next clock edge arrives)

Asynchronous: doesn't wait for clock, quick but dangerous

Both reset and preset

Dnew = R' Dold + S (set-dominant)

Dnew = R' Dold + R'S (reset-dominant)

Selective input capability (input enable/load) LD or EN

Multiplexer at input: Dnew = LD' Q + LD Dold

Load may/may not override reset/set (usually R/S have priority)

Complementary outputs Q and Q'

Registers

logic

Stored values somehow related (e.g., form binary

value)

Share clock, reset, and set lines

Similar logic at each stage

Examples

OUT1 OUT2 OUT3 OUT4

Shift registers

"0"

Counters

R S R S R S R S

D Q D Q D Q D Q

CLK

Register with selective/parallel load

We often use registers to hold values for multiple clocks

Wait until needed

Used multiple times

How do we modify our D flipflop so that it holds the value till we are

done with it?

A very simple FSM En State Next

0 Q Q

1 Q D

D Q

D Q

clk

enable enable

clk

Registers with clock gating

Load signal is used to enable the clock signal to pass through if 1 and

prevent the clock signal from passing through if 0.

Example: For Positive Edge-Triggered or Negative Pulse Master-Slave Flip-

flop:

Clock

Load

Gated Clock to FF

What logic is needed for gating? Gated Clock = Clock + Load

What is the problem? Clock Skew of gated clocks with respect to clock or

each other

Register with selective/parallel load(Cont.)

1 0

load

clock R31 R0

Shift register

Store last 4 input values in sequence

4-bit shift register:

IN D Q D Q D Q D Q

CLK

Shift register with parallel load

Operation:

cycle 1: load x, output x0

cycle i: output xi

Each stage:

XI

Q(I-1) if (shift==0 )

Q(I)

load FF from xi

else from previous stage.

Shift/load

clk

Shift register with parallel load(Cont.)

shift=1

shift=0

4-bit version:

X3 X2 X1 X0

IN Q(0)

Shift/load

clk

??

??

x3 ??

x3

x2 x3

??

x2

x1 x1

x2

x3

x0

Shift registers with parallel load(Cont.)

X3 X2 X1 X0

IN Q(0)

Shift/load

clk

Parallel-to-serial converter

Also, works as Serial-to-parallel converter, if q values are connected out.

Also get used as controllers (ala ring counters)

Universal shift register

Holds 4 values

Serial or parallel inputs

Serial or parallel outputs

Permits shift left or right

Shift in

new values from left or right

output

clear sets the register contents

and output to 0

left_in right_out

left_out Universal right_in s1 and s0 determine the shift function

clear

s0 shift register clock s0 s1 function

s1 0 0 hold state

0 1 shift right

1 0 shift left

1 1 load new input

input

Universal shift register(Cont.)

Design of universal shift register

New value at next clock cycle:

Nth cell

to N-1th to N+1th

cell Q cell

D

CLK

1 0

0 0 0 output 0 1 2 3 s0 and s1

control mux

0 0 1 output value of FF to left (shift right)

0 1 0 output value of FF to right (shift left) Q[N-1] Q[N+1]

0 1 1 input (left) (right)

Input[N]

Universal shift register(Cont.)

Shift register application

transmission parallel outputs

shift registeer shift reagister shift register shift register

parallel inputs

serial transmission

Register file

Asel

Bsel

Din

R0

Dsel

R1

Multiplexor

decoder

multiplexor

1 R2

Bout

Aout

R31

ld

Frequency divider

DFF DFF

D Q D Q CLK

Q Q CLK_4

CLK

CLK_4

DFF DFF

D Q D Q CLK

Q Q CLK_3

CLK_3

CLK

Pattern recognizer

In this case, recognizing the pattern 1001 on the

single input signal

OUT

IN D Q D Q D Q D Q

CLK

Counters

Counters are sequential circuits which "count" through a specific state sequence.

They can count up, count down, or count through other fixed sequences.

Examples:

binary counter: 000, 001, 010, 011, 100, 101, 110, 111, 000, 001,

gray code counter:

000, 010, 110, 100, 101, 111, 011, 001, 000, 010, 110,

one-hot counter: 0001, 0010, 0100, 1000, 0001, 0010,

BCD counter: 0000, 0001, 0010, , 1001, 0000, 0001

pseudo-random sequence generators: 10, 01, 00, 11, 10, 01, 00, ...

Ripple Counters

Clock is connected to the flip-flop clock input on the LSB bit flip-flop

For all other bits, a flip-flop output is connected to the clock input, thus

circuit is not truly synchronous

Output change is delayed more for each bit toward the MSB.

Resurgent because of low power consumption

Synchronous Counters

Clock is directly connected to the flip-flop clock inputs

Logic is used to implement the desired state sequencing

Counters(Cont.)

What are they used for?

Examples:

Clock divider circuits

16MHz 64

Delays, Timing

Protocols

Ripple counter

How does it work? D A

When there is a positive

Clock

edge on the clock input R

of A, A complements

The clock input for flip- D B

flop B is the complemented

output of flip-flop A R

When flip A changes Reset

from 1 to 0, there is a

positive edge on the

CP

clock input of B

causing B to

complement A

B

0 1 2 3 0 1

Ripple counter(Cont.)

cause-effect relation-

ship from the prior A

slide =>

B

The corresponding

0 1 2 3 0 1

sequence of states =>

(B,A) = (0,0), (0,1), (1,0), (1,1), (0,0), (0,1),

Each additional bit, C, D, behaves like bit B, changing half as

frequently as the bit before it.

For 3 bits: (C,B,A) = (0,0,0), (0,0,1), (0,1,0), (0,1,1),

(1,0,0), (1,0,1), (1,1,0), (1,1,1), (0,0,0),

Ripple counter(Cont.)

sensitive transition (positive in the example) causes a change

in the next flip-flops state.

The changes ripple upward through the chain of flip-flops, i.

e., each transition occurs after a clock-to-output delay from

the stage before.

To see this effect in detail look at the waveforms on the next

slide.

Ripple counter(Cont.)

10, the next clock increments the count to (C,B,A) = 0 base

10. In fine timing detail:

The clock to output delay

tPHL causes an increasing

delay from clock edge for tPHL

each stage transition. CP

Thus, the count ripples tPHL

from least to most A

significant bit.

For n bits, total worst case tpHL

delay is n tPHL. B

C

Discouraged

Know it exists

Dont use it

Synchronous counters

To eliminate the "ripple" effects, use a common clock

for each flip-flop and a combinational circuit to

generate the next state.

For binary counters (most common case) incrementer

circuit would work,

register

Synchronous counters(Cont.)

D Q D Q D Q D Q c b a c+ b + a+

0 0 0 0 0 1

CLK 0 0 1 0 1 0

0 1 0 0 1 1

0 1 1 1 0 0

1 0 0 1 0 1

1 0 1 1 1 0

"1" 1 1 0 1 1 1

1 1 1 0 0 0

Synchronous counters(Cont.)

D Q 0

1

D Q 1

D Q 2

D Q 3

Carry

Output CO

Clock

counters with enable to count

Count

Count Enable D Q 0

D Q 1

Count Action

D Q 2

1 Count up stored value

D Q 3

Carry

Output CO

Clock

Counter with parallel load

Load

Count

D 0 D Q 0

enabled for Load = 1

Add logic to:

disable count logic for Load = 1 D 1 D Q 1

for Load = 1

enable count logic for Load = 0

and Count = 1 D Q

2 D 2

0 0 Hold Stored Value D 3 D Q 3

1 X Load D Carry

Output CO

Clock

Four-bit binary synchronous up-counter

Positive edge-triggered FFs w/ sync load and clear inputs

Parallel load data from D, C, B, A

Enable inputs: must be asserted to enable counting

RCO: ripple-carry out used for cascading counters

high when counter is in its highest state 1111

implemented using an AND gate

EN

(2) RCO goes high

D

C RCO

B

(3) High order 4-bits A QD

QC

are incremented LOAD QB

CLK QA

CLR

(1) Low order 4-bits = 1111

Offset counters

"1" EN

synchronous load RCO

"0" D QD

e.g., 0110, 0111, 1000, 1001, 1010, "1" C QC

"1" B QB

1011, 1100, 1101, 1111, 0110, . . . "0" A QA

CLK

comparator for ending value "0" CLR

0000

Combinations of the above (start

"1" EN

and stop value) RCO

"0" D QD

"0" C QC

"0" B QB

"0" A QA

LOAD

CLK

CLR

Design up-down counter

c b a c + b + a+

0 0 0 1 1 1

0 0 1 0 0 0

0 1 0 0 0 1

0 1 1 0 1 0

1 0 0 0 1 1

1 0 1 1 0 0

1 1 0 1 0 1

1 Down-count

1 1 1 1 0

Other counters

In this case, 1000, 0100, 0010, 0001

If one of the patterns is its initial state (by loading or

set/reset) OUT1 OUT2 OUT3 OUT4

IN D Q D Q D Q D Q

CLK

In this case, 1000, 1100, 1110, 1111, 0111, 0011,

0001, 0000 OUT1 OUT2 OUT3 OUT4

IN D Q D Q D Q D Q

CLK

Sequential logic implementation

Sequential circuits

Primitive sequential elements

Combinational logic

Models for representing sequential circuits

Finite-state machines (Moore and Mealy)

Representation of memory (states)

Changes in state (transitions)

Basic sequential circuits Inputs Outputs

Shift registers Combinational

Counters Storage logic

Design procedure Elements

State diagrams

State transition table Next

Next state functions State State

Abstraction of state elements

Localize feedback loops and make it easy to

break cycles

Implementation of storage elements leads to

various forms of sequential logic

Inputs Outputs

Combinational

Logic

Storage Elements

Forms of sequential logic

occur whenever state inputs change (elements

may be simple wires or delay elements)

Synchronous sequential logic state changes

occur in lock step across all storage elements

(using a periodic waveform - the clock)

Combinational Combinational

logic logic

Clock

Synchronous circuit

Combinational

Logic

clk

time

Synchronous circuit(Cont.)

clock input

option feedback

output

Combinational Logic Blocks (CL)

Acyclic clock

no internal state (no feedback) distributed to all flip-flops

output only a function of inputs ALL CYCLES GO THROUGH A REG!

Registers (reg)

collections of flip-flops

Finite state machine representations

storage elements

Transitions: change of state

Clock: controls when state can change by controlling

storage elements

001 010 111

In = 1 In = 0

In = 0

100 110

In = 1

Sequential logic

Sequences through a series of states

Based on sequence of values on input signals

Clock period defines elements of sequence

Example : finite state machine diagram

ERR

closed

& new not equal

& new & new

S1 S2 S3 OPEN

closed closed closed

reset open

mux=C1 equal mux=C2 equal mux=C3 equal

& new & new & new

Can any sequential system be represented

with a state diagram?

Shift register OUT1 OUT2 OUT3

on transition arcs CLK

Output values shown

within state node

1

100 110

1 0 1 1

1

0

0 1 0

0

001 011

0

Counters are simple finite state machines

Counters

Proceed thru well-defined state sequence in response to

enable

Many types of counters: binary, BCD, Gray-code

3-bit up-counter: 000, 001, 010, 011, 100, 101, 110, 111, 000,

...

3-bit down-counter: 111, 110, 101, 100, 011, 010, 001, 000,

111, ...

001 010 011

How do we turn a state diagram into

logic?

Counter

Three flip-flops to hold state

Logic to compute next state

Clock signal controls when flip-flop memory can change

Wait long enough for combinational logic to compute new value

Don't wait too long as that is low performance

OUT1 OUT2 OUT3

D Q D Q D Q

CLK

"1"

FSM design procedure

Start with counters

Simple because output is just state

Simple because no choice of next state based on input

State diagram to state transition table

Tabular form of state diagram

Like a truth-table

State encoding

Decide on representation of states

For counters it is simple: just its value

Implementation

Flip-flop for each state bit

Combinational logic based on encoding

FSM design procedure: State diagram to

encoded state transition table

Tabular form of state diagram

Like a truth-table (specify output for all input

combinations)

Encoding of states: easy for counters just use

value current state next state

0 000 001 1

001 010 011 1 001 010 2

2 010 011 3

3 011 100 4

000 100

4 100 101 5

3-bit up-counter

5 101 110 6

6 110 111 7

7 111 000 0

111 110 101

Implementation

D flip-flop for each state bit

Combinational logic based on encoding

notation to show

function represent

C3 C2 C1 N3 N2 N1 input to D-FF

0 0 0 0 0 1

0 0 1 0 1 0 N1 := C1'

0 1 0 0 1 1 N2 := C1C2' + C1'C2

0 1 1 1 0 0 := C1 xor C2

N3 := C1C2C3' + C1'C3 + C2'C3

1 0 0 1 0 1 := C1C2C3' + (C1' + C2')C3

1 0 1 1 1 0 := (C1C2) xor C3

1 1 0 1 1 1

1 1 1 0 0 0

N3 C3 N2 C3 N1 C3

0 0 1 1 0 1 1 0 1 1 1 1

C1 0 1 0 1 C1 1 0 0 1 C1 0 0 0 0

C2 C2 C2

Another example

Shift register

Input determines next state

100 1 110

In C1 C2 C3 N1 N2 N3 1

0 0 0 0 0 0 0 0 1

1 1

0 0 0 1 0 0 0

0 0 1 0 0 0 1 0 000 1 010 101 0 111 1

0 0 1 1 0 0 1

0 0 1 0

0 1 0 0 0 1 0 0

001 011

0 1 0 1 0 1 0 0

0 1 1 0 0 1 1

0 1 1 1 0 1 1

1 0 0 0 1 0 0 N1 := In

1 0 0 1 1 0 0 N2 := C1

1 0 1 0 1 0 1 N3 := C2

1 0 1 1 1 0 1 OUT1 OUT2 OUT3

1 1 0 0 1 1 0

1 1 0 1 1 1 0

1 1 1 0 1 1 1 IN D Q D Q D Q

1 1 1 1 1 1 1

CLK

More complex counter example

Complex counter

Repeats five states in sequence

Not a binary number representation

Step 1: derive the state transition diagram

Count sequence: 000, 010, 011, 101, 110

Step 2: derive the state transition table from the

state transition diagram

Present State Next State

000 110 C B A C+ B+ A+

0 0 0 0 1 0

0 0 1

0 1 0 0 1 1

010 101 0 1 1 1 0 1

1 0 0

1 0 1 1 1 0

011 1 1 0 0 0 0

1 1 1

note the don't care conditions that arise from the unused state codes

More complex counter example(Cont.)

C+ C B+ C A+ C

0 0 0 X 1 1 0 X 0 1 0 X

A X 1 X 1 A X 0 X 1 A X 1 X 0

B B B

C+ := A

B+ := B' + A'C'

A+ := BC'

Self-Starting counters(Cont.)

C+

care assignment

C B+ C A+ C

0 0 0 0 1 1 0 1 0 1 0 0

A 1 1 1 1 A 1 0 0 1 A 0 1 0 0

B B B

C B A C+ B+ A+

0 0 0 0 1 0

0 0 1 1 1 0 000 110

0 1 0 0 1 1 100

0 1 1 1 0 1

1 0 0 0 1 0

1 0 1 1 1 0 010 101

1 1 0 0 0 0

1 1 1 1 0 0

011

Self-Starting counters

Start-up states

At power-up, counter may be in an unused or invalid state

Designer must guarantee it (eventually) enters a valid

state

Self-starting solution

Design counter so that invalid states eventually transition

to a valid state

May limit exploitation of don't cares

111 111 implementation 001

001 on previous slide

100 100

011 011

State machine model

the circuit

Combinational logic computes:

Next state

Function of current state and inputs

Outputs

Function of current state and inputs (Mealy machine)

Function of current state only (Moore machine)

output Outputs

logic

Inputs

next state Next State

logic

Current State

State machine model(Cont.)

output Outputs

logic

Inputs

next state Next State

logic

States: S1, S2, ..., Sk

Inputs: I1, I2, ..., Im Current State

Transition function: Fs(Si, Ij)

Output function: Fo(Si) or Fo(Si, Ij)

Next State

State

Clock 0 1 2 3 4 5

Example: ant brain

Sensors: L and R antennae, 1 if in

touching wall

Actuators: F - forward step, TL/TR - turn

left/right slightly

Goal: find way out of maze

Strategy: keep the wall on the right

Example: ant brain(Cont.)

Ant behavior

Go forward, turning Go forward, turning right

left slightly slightly

C: Break in wall Back to state A

Go forward, turning

right slightly

Turn left until... state B

LOST: Forward until we

touch something

Example: ant brain(Cont.)

Designing an ant brain

State diagram

L+R L R

(F) (TL) (TL, F)

L R L R R

R

L R

B C

R

(TR, F) (TR, F)

R

Example: ant brain(Cont.)

Synthesizing the ant brain circuit

Encode states using a set of state variables

Arbitrary choice - may affect cost, speed

Use transition truth table

Define next state function for each state variable

Define output function for each output

Implement next state and output functions using

combinational logic

2-level logic

Multi-level logic

Next state and output functions can be optimized

together

Example: ant brain(Cont.)

Transition truth table

L+R L R

and outputs LOST L + R E/G L A

(F) (TL) (TL, F)

L R L R R

R

L R

state L R next state outputs B C

LOST 0 0 LOST F (TR, F) (TR, F) R

LOST 1 E/G F R

LOST 1 E/G F

A 0 0 B TL, F

A 0 1 A TL, F

A 1 E/G TL, F

B 0 C TR, F

B 1 A TR, F

... ... ... ... ...

Example: ant brain(Cont.)

Synthesis

required (X, Y, Z) LOST - 000

E/G - 001

State assignment (in this case, arbitrarily A - 010

B - 011

chosen) C - 100

state L R next state outputs it now remains

X,Y,Z X', Y', Z' F TR TL to synthesize

000 0 0 000 1 0 0 these 6 functions

000 0 1 001 1 0 0

... ... ... ... ...

010 0 0 011 1 0 1

010 0 1 010 1 0 1

010 1 0 001 1 0 1

010 1 1 001 1 0 1

011 0 0 100 1 1 0

011 0 1 010 1 1 0

... ... ... ... ...

Example: ant brain(Cont.)

Synthesis of next state and output functions

X,Y,Z L R X+,Y+,Z+ F TR TL

000 0 0 000 1 0 0

000 - 1 001 1 0 0

000 1 - 001 1 0 0

001 0 0 011 0 0 1

001 - 1 010 0 0 1 e.g.

001 1 - 010 0 0 1

TR = X + Y Z

010 0 0 011 1 0 1

010 0 1 010 1 0 1 X+ = X R + Y Z R = R TR

010 1 - 001 1 0 1

011 - 0 100 1 1 0

011 - 1 010 1 1 0

100 - 0 100 1 1 0

100 - 1 010 1 1 0

Example: ant brain(Cont.)

Circuit implementation

Outputs are a function of the current state only - Moore machine

output F

TR

logic

TL

L next state Next State

R logic

X+ Y+ Z+

Current State

X Y Z

Example: ant brain(Cont.)

Dont cares in FSM synthesis

What happens to the "unused" states (101, 110, 111)?

Exploited as don't cares to minimize the logic

If states can't happen, then don't care what the functions

do

if states do happen, we may be in trouble

L R

L+R L R

000 L+R 001 L 010

(F) (TL) (TL, F)

101

L R R

R

L R

011 100

110 (TR, F) (TR, F) R

R

111

Ant is in deep trouble

if it gets in this state

Example: ant brain(Cont.)

State minimization

Fewer states may mean fewer state variables

High-level synthesis may generate many

redundant states

Two state are equivalent if they are impossible to

distinguish from the outputs of the FSM, i. e., for

any input sequence the outputs are the same

Output must be the same in both states

Must transition to equivalent states for all input

combinations

Example: ant brain(Cont.)

Ant brain revisited

L+R L R

(F) (TL) (TL, F)

L R L R R

R

L R

B C

R

(TR, F) (TR, F)

R

Example: ant brain(Cont.)

New improved brain

Merge equivalent B and C states

Behavior is exactly the same as the 5-state

brain

We now need only 2 state variables rather

than 3 L+R L R

(F) (TL) (TL, F)

L R L R R

L R

B/C

R

(TR, F)

Example: ant brain(Cont.)

New brain implementation

X+ X Y+ X

X,Y L R X',Y' F TR TL

0 1 1 1 0 1 1 1

00 0 0 00 1 0 0

0 0 1 1 1 0 0 0

00 - 1 01 1 0 0 R R

0 0 1 0 1 0 0 1

00 1 - 01 1 0 0 L L

0 0 1 0 1 0 1 1

01 0 0 11 0 0 1 Y Y

01 - 1 01 0 0 1

01 1 - 01 0 0 1

X X X

10 0 0 11 1 0 1 F TR TL

1 0 1 1 0 0 1 0 0 1 0 1

10 0 1 10 1 0 1

1 0 1 1 0 0 1 0 0 1 0 1

10 1 - 01 1 0 1 R R R

1 0 1 1 0 0 1 0 0 1 0 1

11 - 0 11 1 1 0 L L L

1 0 1 1 0 0 1 0 0 1 0 1

11 - 1 10 1 1 0

Y Y Y

Mealy vs. Moore machines

Moore: outputs depend on current state only

Mealy: outputs depend on current state and inputs

Ant brain is a Moore Machine

Output does not react immediately to input change

We could have specified a Mealy FSM

Outputs have immediate reaction to inputs

As inputs change, so does next state, doesnt commit until

clocking event

L R / TL, F

L / TL

A

react right away to leaving the wall

L R / TR, F

Specifying outputs for a Moore machine

Output is only function of state

Specify in state bubble in state diagram

Example: sequence detector for 01 or 10

current next

reset input state state output

0

1 A

1 0 0 A B 0

B/0 D/1

0 1 A C 0

0 0 0 B B 0

0

reset 0 1 B D 0

A/0 1 0

0 0 C E 0

1 0 1 C C 0

1

0 0 D E 1

C/0 E/1 0 1 D C 1

0

0 0 E B 1

1 0 1 E D 1

Specifying outputs for a Mealy machine

Specify output on transition arc between states

Example: sequence detector for 01 or 10

0/0 current next

reset input state state output

B 1 A 0

0 0 A B 0

0/0

0 1 A C 0

reset/0 0 0 B B 0

A 0/1 1/1

0 1 B C 1

0 0 C B 1

1/0

0 1 C C 0

C

1/0

Comparison of Mealy and Moore

machines

Mealy machines tend to have less states

Different outputs on arcs (n^2) rather than states (n)

Moore machines are safer to use

Outputs change at clock edge (always one cycle later)

In Mealy machines, input change can cause output change

as soon as logic is done a big problem when two

machines are interconnected asynchronous feedback

Mealy machines react faster to inputs

React in same cycle don't need to wait for clock

In Moore machines, more logic may be necessary to

decode state into outputs more gate delays after

logic for

inputs inputs outputs

combinational outputs

logic for

next state logic for combinational

R outputs logic for R

outputs

next state

Mealy and Moore examples

Mealy or Moore?

A

out

D Q

B

clock

Q

A

D Q out

B

D Q

clock

Q

Mealy and Moore examples(Cont.)

Mealy or Moore? out

A

D Q

B

D Q

Q

clock

out

A

D Q D Q

Q Q

B

D Q D Q

Q Q

clock

Registered Mealy machine(Really Moore)

Registered state AND outputs

Avoids glitchy outputs

Easy to implement in PLDs

Moore machine with no output decoding

Outputs computed on transition to next state rather than

after entering

View outputs as expanded state vector

output Outputs

Inputs logic

next state

logic

Current State

Example: vending machine

Single coin slot for dimes, nickels

No change

Reset

N

Vending Open

Coin Machine Release

Sensor FSM Mechanism

D

Clock

Example: vending machine(Cont.)

Reset

Tabulate typical input sequences:

3 nickels

nickel, dime S0

dime, nickel N D

two dimes

Draw state diagram: S1 S2

Inputs: N, D, reset N D N D

Output: open chute S4 S5 S6

S3

Assumptions: [open] [open] [open]

for one cycle

Each state has a self loop S7

[open]

for N = D = 0 (no coin)

Example: vending machine(Cont.)

state D N state open

0 0 0 0 0

0 1 5 0

0 1 0 10 0

1 1

N 5 0 0 5 0

0 1 10 0

5 D 1 0 15 0

1 1

N 10 0 0 10 0

0 1 15 0

D 10 1 0 15 0

1 1

N+D 15 15 1

[open]

Example: vending machine(Cont.)

present state inputs next state output

Q1 Q0 D N D1 D0 open

0 0 0 0 0 0 0

0 1 0 1 0

1 0 1 0 0

1 1

0 1 0 0 0 1 0

0 1 1 0 0

1 0 1 1 0

1 1

1 0 0 0 1 0 0

0 1 1 1 0

1 0 1 1 0

1 1

1 1 1 1 1

Example: vending machine(Cont.)

Mapping to logic

D1 Q1 D0

0 1 1 0

Q1 Open Q1

0 0 1 0

0 0 1 1

1 0 1 1 0 0 1 0

0 1 1 1 N N N

X X X X X X X X

D X X X X D D

0 1 1 1 0 0 1 0

1 1 1 1

Q0 Q0 Q0

D1 = Q1 + D + Q0 N

D0 = Q0 N + Q0 N + Q1 N + Q1 D

OPEN = Q1 Q0

Example: vending machine(Cont.)

One-hot encoding

present state inputs next state output

Q3 Q2 Q1 Q0 D N D3 D2 D1 D0 open

0 0 0 1 0 0 0 0 0 1 0 D0 = Q0 D N

0 1 0 0 1 0 0

1 0 0 1 0 0 0

1 1 - - - - - D1 = Q0 N + Q1 D N

0 0 1 0 0 0 0 0 1 0 0

0 1 0 1 0 0 0 D2 = Q0 D + Q1 N + Q2 D N

1 0 1 0 0 0 0

1 1 - - - - -

0 1 0 0 0 0 0 1 0 0 0 D3 = Q1 D + Q2 D + Q2 N + Q3

0 1 1 0 0 0 0

1 0 1 0 0 0 0 OPEN = Q3

1 1 - - - - -

1 0 0 0 - - 1 0 0 0 1

Example: vending machine(Cont.)

This can be corrected by retiming, i.e., move flip-flops and logic through

each other to improve delay

OPEN = reset'(Q1 + D + Q0N)(Q0'N + Q0N' + Q1N + Q1D)

= reset'(Q1Q0N' + Q1N + Q1D + Q0'ND + Q0N'D)

Implementation now looks like a synchronous Mealy machine

Common for programmable devices to have FF at

end of logic

Equivalent Mealy and Moore state

diagrams

Moore machine

Mealy machine

outputs associated with state

outputs associated with

transitions

Reset N D + Reset Reset/0 (N D + Reset)/0

0

N D 0 N D/0

[0]

N N/0

D 5 D/0

N D 5 N D/0

[0]

N N/0

10

D N D D/1 10 N D/0

[0]

N+D N+D/1

15

Reset 15 Reset/1

[1]

Example: traffic light controller

A busy highway is intersected by a little used farmroad

Detectors C sense the presence of cars waiting on the farmroad

with no car on farmroad, light remain green in highway direction

if vehicle on farmroad, highway lights go from Green to Yellow to Red, allowing

the farmroad lights to become green

these stay green only as long as a farmroad car is detected but never longer

than a set interval

when these are met, farm lights transition from Green to Yellow to Red,

allowing highway to return to green

even if farmroad vehicles are waiting, highway gets at least a set interval as

green

Assume you have an interval timer that generates:

a short time pulse (TS) and

a long time pulse (TL),

in response to a set (ST) signal.

TS is to be used for timing yellow lights and TL for green lights

Example: traffic light controller(Cont.)

farm road

car sensors

highway

Example: traffic light controller(Cont.)

inputs description outputs description

reset place FSM in initial state HG, HY, HR assert green/yellow/red highway lights

C detect vehicle on the farm road FG, FY, FR assert green/yellow/red highway lights

TS short time interval expired ST start timing a short or long interval

TL long time interval expired

imply others

state description

S0 highway green (farm road red)

S1 highway yellow (farm road red)

S2 farm road green (highway red)

S3 farm road yellow (highway red)

Example: traffic light controller(Cont.)

S0

TLC / ST TS / ST

S0: HG

S1: HY TS' S1 S3 TS'

S2: FG

S3: FY TS / ST TL+C' / ST

S2

(TL+C')'

Example: traffic light controller(Cont.)

Consider state assignments

output encoding similar problem

to state assignment

(Green = 00, Yellow = 01, Red = 10)

C TL TS ST H F

0 HG HG 0 Green Red

0 HG HG 0 Green Red

1 1 HG HY 1 Green Red

0 HY HY 0 Yellow Red

1 HY FG 1 Yellow Red

1 0 FG FG 0 Red Green

0 FG FY 1 Red Green

1 FG FY 1 Red Green

0 FY FY 0 Red Yellow

1 FY HG 1 Red Yellow

SA1: HG = 00 HY = 01 FG = 11 FY = 10

SA2: HG = 00 HY = 10 FG = 01 FY = 11

SA3: HG = 0001 HY = 0010 FG = 0100 FY = 1000 (one-hot)

Example: traffic light controller(Cont.)

SA1

NS1 = CTL'PS1PS0 + TSPS1'PS0 + TSPS1PS0' + C'PS1PS0 + TLPS1PS0

NS0 = CTLPS1'PS0' + CTL'PS1PS0 + PS1'PS0

ST = CTLPS1'PS0' + TSPS1'PS0 + TSPS1PS0' + C'PS1PS0 + TLPS1PS0

H1 = PS1 H0 = PS1'PS0

F1 = PS1' F0 = PS1PS0'

SA2

NS1 = CTLPS1' + TS'PS1 + C'PS1'PS0

NS0 = TSPS1PS0' + PS1'PS0 + TS'PS1PS0

ST = CTLPS1' + C'PS1'PS0 + TSPS1

H1 = PS0 H0 = PS1PS0'

F1 = PS0' F0 = PS1PS0

SA3

NS3 = C'PS2 + TLPS2 + TS'PS3 NS2 = TSPS1 + CTL'PS2

NS1 = CTLPS0 + TS'PS1 NS0 = C'PS0 + TL'PS0 + TSPS3

H1 = PS3 + PS2 H0 = PS1

F1 = PS1 + PS0 F0 = PS3

Finite state machine optimization

State minimization

Fewer states require fewer state bits

Fewer bits require fewer logic equations

Encodings: state, inputs, outputs

State encoding with fewer bits has fewer equations to

implement

However, each may be more complex

State encoding with more bits (e.g., one-hot) has simpler

equations

Complexity directly related to complexity of state diagram

Input/output encoding may or may not be under designer

control

State minimization

Algorithmic approach

Goal identify and combine states that have equivalent behavior

Equivalent states:

Same output

For all input combinations, states transition to same or equivalent

states

Algorithm sketch

1. Place all states in one set

2. Initially partition set based on output behavior

3. Successively partition resulting subsets based on next state

transitions

4. Repeat (3) until no further partitioning is required

states left in the same set are equivalent

Polynomial time procedure

State minimization(Cont.)

State minimization example

Input Next State Output

Sequence Present State X=0 X=1 X=0 X=1

Reset S0 S1 S2 0 0

0 S1 S3 S4 0 0

1 S2 S5 S6 0 0

00 S3 S0 S0 0 0

01 S4 S0 S0 1 0

10 S5 S0 S0 0 0

11 S6 S0 S0 1 0

S0

0/0 1/0

S1 S2

0/0 1/0 0/0 1/0

S3 S4 S5 S6

1/0 1/0 1/0 1/0

0/0 0/1 0/0 0/1

State minimization(Cont.)

Method of successive partitions

Input Next State Output

Sequence Present State X=0 X=1 X=0 X=1

Reset S0 S1 S2 0 0

0 S1 S3 S4 0 0

1 S2 S5 S6 0 0

00 S3 S0 S0 0 0

01 S4 S0 S0 1 0

10 S5 S0 S0 0 0

11 S6 S0 S0 1 0

( S0 S1 S2 S3 S4 S5 S6 )

S1 is equivalent to S2

( S0 S1 S2 S3 S5 ) ( S4 S6 )

S3 is equivalent to S5

( S0 S3 S5 ) ( S1 S2 ) ( S4 S6 ) S4 is equivalent to S6

( S0 ) ( S3 S5 ) ( S1 S2 ) ( S4 S6 )

State minimization(Cont.)

Minimized FSM

110 Input

Sequence

Next State

Present State X=0 X=1 X=0

Output

X=1

0+1 S1' S3' S4' 0 0

X0 S3' S0 S0 0 0

X1 S4' S0 S0 1 0

S0

X/0

S1

0/0 1/0

S3 S4

X/0 0/1 1/0

State minimization(Cont.)

More complex state minimization

inputs here

00 10

S0 00 S1

[1] [0]

01 present next state output

10 11 state 00 01 10 11

11

00 01 S0 S0 S1 S2 S3 1

00 01 S1 S0 S3 S1 S4 0

S2 S3 S2 S1 S3 S2 S4 1

[1] 01 [0] S3 S1 S0 S4 S5 0

10

10 11 11 S4 S0 S1 S2 S5 1

01

S5 S1 S4 S0 S5 0

10 10

00 S4 11 S5 00

[1] [0]

symbolic state

01 transition table

11

State minimization(Cont.)

Minimized FSM

Implication chart method

Cross out incompatible states based on outputs

Then cross out more cells if indexed chart entries are

already crossed out

S1 present next state output

state 00 01 10 11

S0-S1

S0' S0' S1 S2 S3' 1

S1-S3 S1 S0' S3' S1 S3' 0

S2

S2-S2 S2 S1 S3' S2 S0' 1

S3-S4 S3' S1 S0' S0' S3' 0

S0-S1

S3 S3-S0

S1-S4

S4-S5 minimized state table

S0-S0 S1-S0 (S0==S4) (S3==S5)

S4 S1-S1 S3-S1

S2-S2 S2-S2

S3-S5 S4-S5

S0-S1 S1-S1

S5 S3-S4 S0-S4

S1-S0 S4-S0

S4-S5 S5-S5

S0 S1 S2 S3 S4

State minimization(Cont.)

Minimizing incompletely specified FSMs

Equivalence of states is transitive when machine is fully specified

But its not transitive when don't cares are present

e.g., state output

S0 0 S1 is compatible with both S0 and S2

S1 1 but S0 and S2 are incompatible

S2 1

states into equivalent sets that will yield the smallest number of final

states

State minimization(Cont.)

Minimizing states may not yield best circuit

two input changes from 0X toQ1 Q Q Q 1 0 1

+

0

+

X 0 0 0 0 0

0 0 1 0 0

00 X

0 1 1 0 0

[0]

1 0 0 0 1

01 1 0 1 1 1

X X [1] 1 1 1 1 1

1 0 0 0

11 X

[0]

Q1+ = X (Q1 xor Q0)

X

Q0+ = X Q1 Q0

Another implementation of edge detector

fast X

00

X [0] X

X

10 01

[0] [1]

X

X 11 X

[0]

X

State assignment

With n state bits for m states there are 2n! / (2n m)!

[log n <= m <= 2n]

2n codes possible for 1st state, 2n1 for 2nd, 2n2 for 3rd,

Huge number even for small values of n and m

Intractable for state machines of any size

Heuristics are necessary for practical solutions

Optimize some metric for the combinational logic

Size (amount of logic and number of FFs)

Speed (depth of logic and fanout)

Dependencies (decomposition)

State assignment(Cont.)

State assignment strategies

Possible strategies

Sequential just number states as they appear in the

state table

Random pick random codes

One-hot use as many state bits as there are states

(bit=1 > state)

Output use outputs to help encode states

Heuristic rules of thumb that seem to work in most

cases

No guarantee of optimality another intractable

problem

State assignment(Cont.)

One-hot state assignment

Simple

Easy to encode, debug

Small logic functions

Each state function requires only predecessor state bits as input

Good for programmable devices

Lots of flip-flops readily available

Simple functions with small support (signals its dependent upon)

Impractical for large machines

Too many states require too many flip-flops

Decompose FSMs into smaller pieces that can be one-hot encoded

Many slight variations to One-hot

One-hot + all-0

State assignment(Cont.)

Heuristics for state assignment

Adjacent codes to states that share a common next state

Group 1's in next state map a b

I Q Q+ O i/j i/k

c=i*a + i*b

i a c j c

i b c k

Group 1's in next state map a

I Q Q+ O i/j k/l

b=i *a

i a b j c=k*a

k a c l b c

Group

I

1'sQ in Qoutput

+ O

map

j=i *a+ i *c a c

i a b j b=i*a i/j i/j

i c d j d=i*c

b d

State assignment(Cont.)

General approach to heuristic state

assignment

All current methods are variants of this

1) Determine which states attract each other (weighted pairs)

2) Generate constraints on codes (which should be in same cube)

3) Place codes on Boolean cube so as to maximize constraints

satisfied (weighted sum)

Different weights make sense depending on whether we are

optimizing for two-level or multi-level forms

Can't consider all possible embeddings of state clusters in

Boolean cube

Heuristics for ordering embedding

To prune search for best embedding

Expand cube (more state bits) to satisfy more constraints

State assignment(Cont.)

Output-Based encoding

Reuse outputs as state bits - use outputs to help

distinguish states

Why create new functions for state bits when output can

serve as well

Fits in nicely with synchronous Mealy implementations

Inputs Present State Next State Outputs

C TL TS ST H F

0 HG HG 0 00 10

0 HG HG 0 00 10

1 1 HG HY 1 00 10

0 HY HY 0 01 10

1 HY FG 1 01 10

1 0 FG FG 0 10 00

0 FG FY 1 10 00

1 FG FY 1 10 00

0 FY FY 0 10 01

1 FY HG 1 10 01

HY = ST H1 H0 F1 F0 + ST H1 H0 F1 F0 need ANY state bits implement 5 functions

FG = ST H1 H0 F1 F0 + ST H1 H0 F1 F0 (one for each output) instead of 7 (outputs plus

HY = ST H1 H0 F1 F0 + ST H1 H0 F1 F0 2 state bits)

State assignment(Cont.)

Current state assignment approaches

For tight encodings using close to the minimum number of

state bits

Best of 10 random seems to be adequate (averages as well as

heuristics)

Heuristic approaches are not even close to optimality

Used in custom chip design

One-hot encoding

Easy for small state machines

Generates small equations with easy to estimate complexity

Common in FPGAs and other programmable logic

Output-based encoding

Ad hoc - no tools

Most common approach taken by human designers

Yields very small circuits for most FSMs

Sequential logic examples

FSMs are the decision making logic of digital designs

Partitioning designs into data-path and control

elements

When inputs are sampled and outputs asserted

Basic design approach: 4-step design process

Implementation examples and case studies

Finite-string pattern recognizer

Complex counter

Traffic light controller

Door combination lock

General FSM design procedure

Determine possible states of machine

State minimization

Encode states and outputs into a binary code

State assignment or state encoding

Output encoding

Possibly input encoding (if under our control)

Realize logic to implement functions for states and

outputs

Combinational logic implementation and optimization

Choices in steps 2 and 3 have large effect on resulting logic

Finite string pattern recognizer (Step 1)

One input (X) and one output (Z)

Output is asserted whenever the input sequence 010 has

been observed, as long as the sequence 100 has never been

seen

Sample input/output behavior:

X: 0 0 1 0 1 0 1 0 0 1 0

Z: 0 0 0 1 0 1 0 1 0 0 0

X: 1 1 0 1 1 0 1 0 0 1 0

Z: 0 0 0 0 0 0 0 1 0 0 0

Finite string pattern recognizer(Cont.)

For the strings that must be recognized, i.e., 010

and 100 reset S0

[0]

Moore implementation 0 1

S1 S4

[0] [0]

1 0

S2 S5

[0] [0]

0 0

S3 S6 0 or 1

[1] [0]

Finite string pattern recognizer(Cont.)

010

If next input is 0 then have 0100 = ...100 (state S6)

If next input is 1 then have 0101 = 01 (state S2)

reset S0

[0]

Exit conditions from S1: 0 1

recognizes strings of form 0

0 S1 S4 1

(no 1 seen); [0] ...0 ...1 [0]

loop back to S1 if input is 0 1 0

[0] [0]

recognizes strings of form 1 ...01

(no 0 seen); 0 1 0

loop back to S4 if input is 1 S3 S6 0 or 1

...010 [1] ...100 [0]

Finite string pattern recognizer(Cont.)

S2 = 01; If next input is 1,

then string could be prefix of (01)1(00)

S4 handles just this case

S5 = 10; If next input is 1,

then string could be prefix of (10)1(0)

S2 handles just this case reset S0

Reuse states as much as possible [0]

Look for same meaning 0 1

State minimization leads to 0 S1 S4 1

[0] ...0 ...1 [0]

smaller number of bits to

represent states 1 1 0

Once all states have complete

S2 1 S5

set of transitions we have [0] [0] ...10

final state diagram ...01

0 1 0

S3 S6 0 or 1

...010 [1] ...100 [0]

Finite string pattern recognizer(Cont.)

Review of process

Understanding problem

Write down sample inputs and outputs to understand specification

Derive a state diagram

Write down sequences of states and transitions for sequences to be

recognized

Minimize number of states

Add missing transitions; reuse states as much as possible

State assignment or encoding

Encode states with unique patterns

Simulate realization

Verify I/O behavior of your state diagram to ensure it matches

specification

Complex counter

When M = 0, the counter counts up in the binary sequence

When M = 1, the counter advances through the Gray code

sequence

binary: 000, 001, 010, 011, 100, 101, 110, 111

Gray: 000, 001, 011, 010, 110, 111, 101, 100

Valid I/O behavior (partial)

0 000 001

0 001 010

1 010 110

1 110 111

1 111 101

0 101 110

0 110 111

Complex counter(Cont.)

One state for each output combination

Add appropriate arcs for the mode control

reset S0 0 S1 0 S2 0 S3 0 S4 0 S5 0 S6 0 S7

[000] [001] [010] [011] [100] [101] [110] [111]

1

1 1 1

1

1 1 1

Traffic light controller as two

communicating FSMs

Without separate timer

TS'

S0 would require 7 states

S1 would require 3 states S1 S1a

S2 would require 7 states TS/ST

S1b

S3 would require 3 states

S1 and S3 have simple transformation S1c

S0 and S2 would require many more arcs /ST

C could change in any of seven states

By factoring out timer

Greatly reduce number of states traffic light

4 instead of 20 controller

Counter only requires seven or eight states ST

12 total instead of 20 TS TL

timer

Communicating finite state machines

One machine's output is another machine's

input

X

CLK

FSM 1 FSM 2

Y FSM1 A A B

Y==0 X==0

A C Y

[1] [0]

Y==1 X==1

D machines advance in lock step

B initial inputs/outputs: X = 0, Y = 0

[0] [1]

X==0

X==1

Data path and control

Digital hardware systems = data-path + control

Data-path: registers, counters, combinational

functional units (e.g., ALU), communication (e.g.,

busses)

Control: FSM generating sequences of control signals

that instructs data-path what to do next

"puppeteer who pulls the strings"

control

status control

info and state signal

inputs outputs

data-path

"puppet"

Digital combinational lock

Punch in 3 values in sequence and the door opens; if there

is an error the lock must be reset; once the door opens the

lock must be reset

Outputs: door open/close

Memory: must remember combination or always have it

available

Stored in registers (how loaded?)

Hardwired via switches set by user

Digital combinational lock(Cont.)

Implementation in software

integer combination_lock ( ) {

integer v1, v2, v3;

integer error = 0;

static integer c[3] = 3, 4, 2;

v1 = read_value( );

if (v1 != c[1]) then error = 1;

v2 = read_value( );

if (v2 != c[2]) then error = 1;

v3 = read_value( );

if (v2 != c[3]) then error = 1;

}

Digital combinational lock(Cont.)

Determining details of the specification

How many values in sequence?

How do we know a new input value is entered?

What are the states and state transitions of the

system?

new value reset

clock

open/closed

Digital Combinational Lock(Cont.)

Digital combination lock state diagram

States: 5 states

Represent point in execution of machine

Each state has outputs

Transitions: 6 from state to state, 5 self transitions, 1

global

Changes of state occur when clock says its ok

Based on value of inputs

Inputs: reset, new, results of comparisons ERR

closed

Output: open/closed

C1!=value

C2!=value C3!=value

& new

& new & new

S1 S2 S3 OPEN

reset closed closed closed open

C1=value C2=value C3=value

& new & new & new

Digital combinational lock(Cont.)

Data-path and control structure

Data-path

Storage registers for combination values

Multiplexer

Comparator

Control

Finite-state machine controller

Control for data-path (which value to compare)

C1 C2 C3 new reset

4 4 4 mux

multiplexer

control

4 controller

value comparator clock

4 equal

open/closed

Digital combinational lock(Cont.)

State table for combination lock

Finite-State machine

Refine state diagram to take internal structure into

account

State table ready for encoding

next

reset new equal state state mux open/closed

1 S1 C1 closed

0 0 S1 S1 C1 closed

0 1 0 S1 ERR closed

0 1 1 S1 S2 C2 closed

...

0 1 1 S3 OPEN open

...

Digital combinational lock(Cont.)

Encodings for combination lock

Encode state table

State can be: S1, S2, S3, OPEN, or ERR

Needs at least 3 bits to encode: 000, 001, 010, 011, 100

And as many as 5: 00001, 00010, 00100, 01000, 10000

Choose 4 bits: 0001, 0010, 0100, 1000, 0000

new reset

Output mux can be: C1, C2, or C3 mux

Needs 2 to 3 bits to encode control

Choose 3 bits: 001, 010, 100 controller

clock

Output open/closed can be: open or closed equal

Needs 1 or 2 bits to encode

open/closed

Choose 1 bit: 1, 0

next

reset new equal state state mux open/closed

1 0001 001 0 mux is identical to last 3 bits of state

0 0 0001 0001 001 0 open/closed is identical to first bit of state

0 1 0 0001 0000 0 therefore, we do not even need to implement

0 1 1 0001 0010 010 0 FFs to hold state, just use outputs

...

0 1 1 0100 1000 1

Design register with set/reset

S R

D Q

Reset forces state to 0

Design

circuit will give a 1 output when the input sequence starting

from reset up to present time includes odd number of 1s,

otherwise the circuit will give a 0 output.

Design a clock synchronous sequential circuit with two inputs

A, B and a single output Z that is 1 if:

A had the same value at each of the two previous clock

ticks, or

B has been 1 since the last time that the first condition

was true.

Otherwise, output should be 0.

Digital design

Other flip-flop types

J-K and T flip-flops

Behavior

Implementation

Basic descriptors for understanding and using

different flip-flop types

Characteristic tables

Characteristic equations

Excitation tables

For actual use, see Reading Supplement -

Design and Analysis Using J-K and T Flip-Flops

J-K flip-flop

Behavior

Same as S-R flip-flop with J analogous to S and K analogous to R

Except that J = K = 1 is allowed, and

For J = K = 1, the flip-flop changes to the opposite state

As a master-slave, has same 1s catching behavior as S-R flip-flop

If the master changes to the wrong state, that state will be passed

to the slave

E.g., if master falsely set by J = 1, K = 1 cannot reset it during the

current clock cycle

J-K flip-flop(Cont.)

Implementation Symbol

To avoid 1s catching

behavior, one solution

used is to use an J Q

edge-triggered D as

the core of the flip-flop

K

J D Q

K

T flip-flop

Behavior

Has a single input T

For T = 0, no change to state

For T = 1, changes to opposite state

Same as a J-K flip-flop with J = K = T

As a master-slave, has same 1s catching behavior as J-K

flip-flop

Cannot be initialized to a known state using the T input

Reset (asynchronous or synchronous) essential

T flip-flop(Cont.)

Implementation Symbol

To avoid 1s catching

behavior, one solution T Q

used is to use an

edge-triggered D as

the core of the flip-flop

D Q

T

Basic flip-flop descriptors

Used in analysis

Characteristic table - defines the next state of

the flip-flop in terms of flip-flop inputs and

current state

Characteristic equation - defines the next state

of the flip-flop as a Boolean function of the

flip-flop inputs and the current state

Used in design

Excitation table - defines the flip-flop input

variable values as function of the current state

and next state

D flip-flop descriptors

Characteristic Table

D Q(t + 1) Operation

0 0 Reset

1 1 Set

Characteristic Equation

Q(t+1) = D

Excitation Table

Q(t +1) D Operation

0 0 Reset

1 1 Set

T flip-flop descriptors

Characteristic Table

T Q(t + 1) Operation

0 Q ( t) No change

1 Q ( t) Complement

Characteristic Equation

Q(t+1) = T Q

Excitation Table

Q(t +1) T Operation

Q ( t) 0 No change

Q ( t) 1 Complement

S-R flip-flop descriptors

Characteristic Table S R Q(t + 1) Operation

0 0 Q ( t) No change

0 1 0 Reset

1 0 1 Set

1 1 ? Undefined

Characteristic Equation

Q(t+1) = S + R Q, S.R = 0

Excitation Table

Q(t) Q(t+ 1) S R Operation

0 0 0 X No change

0 1 1 0 Set

1 0 0 1 Reset

1 1 X 0 No change

J-K flip-flop descriptors

Characteristic Table J K Q(t + 1) Operation

0 0 Q ( t) No change

0 1 0 Reset

1 0 1 Set

1 1 Q ( t) Complement

Characteristic Equation

Q(t+1) = J Q + K Q

Excitation Table

Q(t) Q(t + 1) J K Operation

0 0 0 X No change

0 1 1 X Set

1 0 X 1 Reset

1 1 X 0 No Change

Flip-flop behavior

Use the characteristic tables to find the output waveforms for the flip-

flops shown:

Clock

D,T

D Q

T Q

Flip-flop behavior(Cont.)

Use the characteristic tables to find the output waveforms for the flip-

flops shown:

Clock

S,J

R,K

S QSR ?

J QJK

K

Implement D Flip-flop by T Flip-flop

Q Q 0 1

D 0 1 T

0 0 1

0 0 0

1 1 1 1 0

1

T = D Q + D Q

D

D

Q

T

Q

Implement JK Flip-flop by D Flip-flop

Q

0 1 Q 0 1

JK JK D Q+

00 0 1 00 0 1

01 0 0 01 0 0 0 0

11 1 0 11 1 0 1 1

10 1 1 10 1 1

D = J Q + K Q

J

Q

D

K Q

Implement JK Flip-flop by T Flip-flop

Q Q+

Q 0 1

0 1 JK Q+

JK JK

T Q+

00 0 1 00 0 0 00 Q

01 0 0 01 0 1 Q

01 0 0

11 1 0 11 1 1 10 1 1 Q

10 1 1 10 1 0 11 Q

T = J Q + K Q

J

Q

T

K Q

Implement T Flip-flop by JK Flip-flop

Q

T 0 1 J K

Q Q+

0 0 1 00 0 X

1 1 0 01 1 X

10 X 1

11 X 0

Q Q

T 0 1 T 0 1

0 X 0 X 0

0

1 1 X 1 X 1

J=T K=T

Sequential circuit analysis

thanks

digital design

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