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N A S A TECHNICAL NOTE
N A S - - TN- D-2003 A ( / ,
by John Semydn
Goddard Spme Flight Center
Greenbelt, M d
NATIONAL AERONAUTICS AND SPACE ADMINISTRATION WASHINGTON, D. C. OCTOBER 1964
20230 -- .50 Washington. Md. NATIONAL AERONAUTICS AND SPACE ADMINISTRATION For sale by the Office of Technical Services.DIGITAL OHMMETER By John Semyan Goddard Space Flight C e n t e r Greenbelt. D.C. Price $0. Department of Commerce.
DIGITAL OHMMETER by John Semyan Goddavd Space Flight Centev SUMMARY This paper describes a unique method of digitizing resistive sensor outputs f o r telemetry. and operating speed. i . Some consideration is given to possible improvements in power consumption. the resistance to be measured comprises the unknown leg of a wheatstone bridge which is automatically nulled by sequentially adding the required binary values of resistance in series in the known leg. A design example that was used t o prove the practicality and accu racy of the system is presented in detail. An abso lute accuracy of Kl. range of resistance measurement. In the system proposed.05percent is easily achieved. The states of the reed relay switches which control the binary balancing resistance then constitute a parallel digital word which represents unknown resistance.
. . .. . . . .. . . . . . . . .. . . . . . . . . . .. . . . . . DESIGNEXAMPLE . . ... . . . . . . .. . . . .. ... . . . . ACKNOWLEDGMENTS . . . ... . .. . . . . . . . . . . . . Control Circuits . . . . . . . . . INTRODUCTION . . . . . EXPEFUMENTALEVALUATION .. . . . . . . .. . . . . . . .. . .. .. . . . . . . ... . .. . . . . . . Synchronous Demodulator . . . . . ... . .. . . . .. . .. . .. . . . . . . .. . . . . . . .. . . . . . . . .. 11 11 12 13 iii . . . . . . . . . . . . . . . . . . . .. . . . . . .. . . . . DESCRIPTION O F SYSTEM OPERATION . . .. . .. ... . . ... . . ... . . . . . . .. . . . . . . . . . . Summary Preliminary Considerations . . ... Bridge Design . . . . . . . . . .. . ... . . . . . . . .. . .. . . . . . . .. . . . . . .. . . . . . . .. .. Bridge Drive Circuits . . . . .. .. . . . . . . . . . . . .. E r r o r Amplifier . . . . . Clock Oscillator and Serial Pulse Generator . . .CONTENTS . . . CONCLUDING REMARKS . . . . . . . . . . . . . . . . .. . Appendix A-Lamp Indicator System for Bench Check of Digital Ohmmeter .. .. . . . .
It may be compared to a standard servo system in that an e r r o r voltage is compared with a reference. Lubrication is required f o r many moving p a r t s 2. The system design example shown in this paper demonstrates an absolute accuracy capabil ity of better than 0. The final package is comparatively bulky and heavy 5. Controlled environment is desired for efficient. and consume little power. Simple switching circuitry r e s u l t s in a long operating life. precision gear boxes. Direct digital readout is an inherent feature. long life operation 3. after which corrective action is taken. the bridge is brought close to balance. The latter approach. System redundancy is impractical The digital ohmmeter virtually eliminates most of the above-mentioned disadvantages. has the following disadvantages: 1. rather than analog. and precision potentiometers. common in high-accuracy ground systems for many years. Power requirements are relatively high 6. The only moving p a r t s in the proposed system are the reeds in hermetically sealed reed relays of proven reliability. and accuracy of read out is readily predictable. Precision required in manufacture and assembly of mechanical components is costly and time consuming 4. Through a s e r i e s of successive approximations. The digital ohmmeter described herein is one whose readout is inherently digital. Dynamic range is easily controlled.DIGITAL OHMMETER by John Semyan Goddard Space Flight Center INTRODUCTION An ohmmeter is a device that measures resistance in ohms. the digital ohm meter is a self-balancing bridge circuit. Final packages may be small in size and weight. Basically. the p r i m a r y limitation being the number of bits provided f o r .05 percent. An analog-to-digital converter is needed to supply data to digital telemetering systems 7. The advantages of automatically nulling a bridge using the system described herein a r e nu merous compared with an electromechanical system which u s e s servo motors.
..... the status of the switches constitutes a parallel digital word which represents the value of unlknown resistance...............11111....... and thence to a phase detector... approx. DESCRIPTION OF SYSTEM OPERATION A s stated previously.. Each resistor comprising this step-adjustable resistance is sequentially sampled and controlled... During the time that each binary r e s i s t o r is being tried....... Before detailed design can proceed. DESIGN EXAMPLE Preliminary Considerations The following design example illustrates the practicality of the concept. from the largest to the smallest binary value..... .. 8 ..I I II I 1111111 11111. a r e s e t circuit opens all switches so that the binary adjustable r e s i s t o r assumes a maximum value...... employing a binary adjustable resistance in the known leg of the bridge.. a group of somewhat arbitrary design goals must be specified: Unknown resistance range Allowable power dissipation in unknown resistance Number of bits per data word.... Reed relays a r e used as switches a c r o s s each r e s i s t o r in the known leg of the bridge...... Relay contact resistance can produce an e r r o r when very small resistances a r e switched... and maximuin resistance is limited by s t r a y capacitance effects..11... a r e used to sequentially close the switches a c r o s s the binary r e s i s t o r s ............. Encoding speed Available supply voltages .... Before the sequential sampling process begins..... Serial pulses. derived from a clock signal.. When all have been sampled.. These limits depend on desired readout accuracy and dynamic range. I rtxidout.......c. 2 sec (4 cps clock) .... After the last-and smallest-binary r e s i s t o r is sampled....... In the con servative system described. 900 to 1000 ohms 1 milliwatt max. This is done by the successive approximations method... Higher o r d e r s of accuracy may be obtained by providing a greater number of bits and :iltt>ringthe bridge ratio... 2 .................1111ll~l 11111 I I I I I 1111 1111111111 I 1111 ........ I........ The output of the phase detector is then applied to circuitry that controls the condition of the respective switch.... The main limitation of the proposed system is i t s relatively low encoding speed... Another limitation is the range of resistance which can be accommodated. the e r r o r signal out of the bridge is amplified and compared in phase with the bridge-drive reference signal........... I .......... 56 volts d............. about 2 seconds is required to null the bridge and generate a single S-bit resistance rending.......... the bridge is in a balanced condition within an easily defined percentage of e r r o r .. .... the method employed here in measuring an unknown resistance is to digitally null a bridge automatically...... This condition produces an e r r o r signal out of the bridge to an amplifier...
The maximum permissible power dissipation in the unknown resistance is specified because of self-heating effects which would have to be considered in a typical sensor application. or Es = . for instance. or 255. since the logic operation is easily followed and visual readout is possible while the coder is cycling continuously. The output waveform is symmetrical t o within 5 percent. A platinum w i r e temperature sensor. Bridge Drive Circuits The free-running bridge drive multivibrator used in the breadboard model (Figure 2) operates between +6 volts dc at a frequency of approximately 400 cps. This frequency must be considerably higher than the clock r a t e to allow effective c a r r i e r filtering at the phase detector output. corresponding to about 0. = sensor voltage (rms). discrete coding levels. Since 1 milliwatt has been specified as the maximum permissible power dissipating in the 1000 ohm sensor.An 8-bit binary word provides 2*-1.4 percent of range uncertainty. the square wave driving voltage appearing a c r o s s the sensor must not exceed the amplitude shown in the following calculation: where P = power dissipation. Rs = sensor resistance. but not so high that s t r a y capaci tance will be troublesome. E~ = /(io-3) (103) = 1 volt rms. For 1 milliwatt power dissipation and 1 kilohm r e s i s t o r resistance.. The 10 percent measurement range of unknown resistance there fore should permit an absolute measuring accuracy approaching &0. A 400 cps drive for the bridge was selected. Figure 1 shows a block diagram of the complete system.02 percent. A square waveform was chosen to permit useof a simple logical AND gate as a phase detector. 3 . should have negligible self-heating to minimize e r r o r . The long encoding time was chosen f o r system demonstration.
the configuration of Figure 3 (b) results The drive is now single-ended with respect to ground. avoiding e r r o r s due to end-of-life reed relay contact resistance. . a change of 0. Perhaps the most obvious bridge drive configuration uses a balanced transformer drive [Figure 3 (a)] and produces a single-ended output. 4 .4 ohm in the sensor can be balanced out.~ t REFERENCE SIGNAL I SYNCHRONOUS DEMODULATOR 1 EMITTER FOLLOWER * =Select "C" for min. The schematic diagram in Figure 2 shows the complete drive circuit. or 10 percent. An e r r o r of 0.04 percent e r r o r in absolute sensor resistance. and an overall change of 500 ohms in the X5 leg of the bridge is necessary for bridge balance. The unknown resistance specified has a range of variation from 900 to 1000 ohms. IG = Information gate phase shift a t synchronous demodulator 24 . the dynamic range of measurement is 100 ohms. and the balanced output may be handled conveniently by a differential amplifier. Therefore.4 ohm would constitute a 0. The latter connection is considered preferable.-. The transformer is undesirable in this appli cation because of the low-frequency square wave involved and because of the effects of interwind ing capacitance. Bridge Design A 1:5 bridge ratio permits l a r g e r increments of resistance i n the binary adjustable resistor.DIODE MATRIX BISTABLE MULTIVIBRATOR CLOCK OSCILLATOR (4 cps) SCS = Silicon-controlled switch BISTABLE MULTIVIBRATOR BISTABLE MULTIVIBRATOR COUNTER CIRCUIT Figure 1 -The d i g i t a l ohmmeter. If the output and drive a r e interchanged. Since 2 ohms is the smallest increment in the binary adjustable leg of the bridge. ~ - ~.
8 25. producing an average power dissipation of less than 1 milliwatt in the sensor for the 5:l drive ratio selected. for of stray copocity I i n bridge) A= FSP-8138 Fairchild Dual PNP Figure 2-Bridge drive osci I lator. The measured drive signal to the bridge is approximately 7 volts peak-to-peak. Binary Values of Resistance (N=8 bits) 20 Binary Resistor Equivalent R in Sensor (ohms) 0.6 51. giving an actual measurement range of 898 to 1000 ohms.8 Value (ohms) 2 4 8 16 32 64 128 256 21 22 23 24 25 26 27 A 510 ohm range i n t h e known leg of the bridge is achieved with binary r e s i s t o r values as shown in the table.6 3. bridge.2 5 .4 0. and differential error amplifier. The differential 1.2 6.p + 6 v dc '42524 9 * = Nominally 33pf CClnCellClfion t Vour TO SYNCHRONOUS DEMOD_V_LA_T_O_RJ '1 2N1613 (odi.4 12.
or a 2 ohm change in the X5 leg. where vi" R . = 2 5 ~03 ohms [see Figure 3 (b)].47 Mv peak-to-peak when the 2' binary r e s i s t o r is sampled.4 ohm change in the sensor resistance. to insure the validity of the least significant bit. 5 x lo3 ohms (known leg of bridge). R.I I m L!lJuuw DRIVE SIGNAL P OUTPUT TO NULL AMP. DRIVE SIGNAL OUTPUT TO NULL AMP.47 Mv input. 1 = = 7v P . R. signal out of the bridge produced by a 0. Error Amplifier The nominal gain in the e r r o r amplifier should be about ten times greater than that required to operate the phase detector from a 0. environmentally induced gain variations. may be calculated approximately as follows: ~- ARO t 2 Vout = 'in R.P Thus. (a ) (b) (a) Bridge connected for balanced drive and single-ended output (b) Bridge connected for single-ended drive and balanced output Figure 3-Two bridge drive configurations. 6 . the e r r o r signal out of the bridge could range from 0 to a maximum of 0.47 Mv P - P . 7 (5 103) t (25 103) = 0. (bridge driving voltage). This allowance also provides a margin for safe operation with f a i r l y large.
the peak-to-peak voltage necessary to saturate the AND-gate switch in the synchronous demodulator circuit. A volt age divider adjusts the dc voltage level at the collector of the upper transistor to approximately +1. These a r e considered entirely adequate for system test purposes. for an amplifier gain of 26. the equiv alent common-mode input signal should be a factor of 10 below the differential input signal equivalent to a 1-digit e r r o r . To insure a negligible e r r o r contribution. 2 x 26. vin K A = = = 0.2 v.5 kc.I The minimum voltage gain required in the e r r o r amplifier may be computed as follows. the 7 . Synchronous Demodulator The output of the e r r o r amplifier is capacitor-coupled to the lower transistor in the synchro nous demodulator. allowing a factor of 10 excess of gain over that required to just operate the least significant digit: where Vo = 1. The reference signal from the astable multivibrator is capacitor-coupled to the upper transistor. If the reference and e r r o r signals a r e out of phase.2 o r about 108 db. 10. the effect of phase shift-within limits-can be negligible.000. is about 20 cps to 6. A high common-mode rejection (CMR) ratio in the error amplifier is necessary because the common-mode signal output would have the s a m e effect on the synchronous demodulator as a differential e r r o r signal from the bridge. When both signals are in phase with each other. When e r r o r and reference signals are in phase. Refer to Figure 4. a negative output appears at the collector of the upper transistor.47 Mv as calculated f o r the smallest incremental bridge output. no negative voltage is produced at the output of the demodulator. Measured CMR ratio and gain for the amplifier shown in Figure 2 a r e 102 db and 30. the CMR ratio required would be 1 . minimum gain required. Since a square wave signal is being amplified.000 respectively.8 volts dc when no output signal is present. a nominal gain margin as explained above. Thus. 1. Frequency response of the amplifier design. then the frequency characteristics of the amplifier would require alteration. as shown in Figure 2.000 x 10 . If operating frequency were t o be changed greatly.
5 cps. . Because of the loading effects of the gate. . a . -. The output of the synchronous demodulator is fed through an emitter follower to the eight gate inputs. I I . I I I + 6 v dc --. which count down to a final output frequency of approximately 0. +6vdc b ERROR SIGNALIDENTICAL CONNECTIONS TO 7 OTHER GATE CIRCUITS Figure 4-Synchronous demodulator. . The counter outputs connect to atwenty-four diode AND matrix.0.005#f 2N995 IDENTICAL CONNECTIONS TO 7 OTHER GATES FOR RESET * 22K For @ I 1st binary circuit only.05r f For 1st binary circuit only. . . . I .. The counter consists of three cascaded bistable multivibrators. information gate. an astable multivibrator or clock oscillator having an operating frequency of approximately 4 cps drives a counter as shown in Figure 5. filter circuit produces a negative dc output voltage that maximizes at approximately . .-...--.- REFERENCE I SIGNAL !+ "* @ rI .2 volt.. .. . . At this point of connection the matrix supplies eight s e r i a l outputs that a r e used as sequential gate trigger signals.6 v dc 47K %-d 2N1132 . The diode cathodes a r e connected in a binary configuration to eight 51 kilohm r e s i s t o r s . a l l others hove rhru-connect as shown by dotred line 0. and silicon-controlled switch..5 volts dc. all others hove 270pf fl Output to lamp indicator circuits ' I etc. 1111. 6 . Clock Oscillator and Serial Pulse Generator In the present system.6 v dc ! FROM MATRIX 2N1613 I 21'11613 ERROR SIGNAL 600 - 1..I 1I I I I II I I... the swing of the matrix output pulses is approximately +2 volts to . The 51 kilohm r e s i s t o r s a r e connected to a -6 volt source. Figure 6 shows a timing diagram of the system. .111" . .
Control Circuits The matrix outputs a r e connected to the bases of the eight gate transistors. The r e s e t pulse places all the silicon-controlled switches in an off condition. The s a m e pulse that the reset circuit receives from the matrix is applied to another differen tiating circuit. If apositive signal is applied to the emitter of the gate transistor. and the largest binary r e s i s t o r is shorted out of the bridge circuit. with a longer time constant than that employed to gate the r e s e t circuit on. the negative matrix output pulse turns the gate transistor on and applies the positive e r r o r signal to the base of a switching transistor which virtually shorts the cathode gate of the silicon-controlled switch to ground. the silicon-controlled switch is opened . 9 . Thus. counter. and matrix cii-cuits.6 v dc IN662 diode SERIAL PULSE OUTPUTS - R = 51K = MV = Multivibmtcr ( * ) = Identical units Figure 5-Clock. This negative-going pulse switches the silicon-controlled switch to an on condition s o that the reed relay switch is closed. The matrix output to the largest binary digit control circuit also is fed through a differentiating network to a reset circuit that is common to all eight binary digit control circuits. they a r e fed through a differentiating network to the cathode gates of the silicon-controlled switches. This sampling of the largest binary r e s i s t o r produces an e r r o r signal out of the bridge circuit that has aphase relationwiththe reference signal. hence all binary r e s i s t o r s are series-connected in the bridge circuit (see Figure 4). also.
26 -1 I I 22 21 20 RE ET PUI TYPICAL DIGITAL NO..._ J < I 2' I r I . I I ERROR SIGNAL TO GATE Figure 6-Timing diagram for d i g i t a l ohmmeter.1 I I 1_ _ _ .CLOCK S I G N A L = 4 cps I I --+s -c e -1 1 s e t I 4 I COUNTER OUTPUTS AT COLLECTORS c1 I I 1 I I II c2 c3 c4 c5 C6 DIODE MATRIX SERIAL OUTPUTS I I - r-------1 ! 8 BIT WORD. 10 .
11 . It operated very efficiently and would be preferred in a reliable flight package. No great amount of circuit refinement effort h a s gone into the development of this system.and the largest binary r e s i s t o r is again functional in the bridge circuit. A ring counter circuit employing modular bistable elements was tried in place of the counter and diode matrix circuits. It is expectedthat a shunt-type gating system for the e r r o r signal circuit would permit a greater range of parameter variation and possibly simplify the control circuit. The 4 cps clock frequency used in the example was experimentally increased to about 20 cps. The r e s e t circuit is actuated only at the start of the sampling pulse for the largest binary resistor. It readily can be seen that the demon strated method is valid and that it may be adapted to many systems concerned with resistance measurement. A lamp indicator system. shown in Appendix A. without appreciable change to other parts of the system. w a s used as an output display. the silicon-controlled switch might be replaced by a more e a s i l y controlled level-sensitive bistable circuit . EXPERIMENTAL EVALUATION The unit described herein performed as expected. A plot of binary numbers versus resistance proved system performance and accuracy.1 ohm increments of resistance was used as the unknown. Absolute accuracy was better than 50.1 percent. This process is then repeated for the remaining 7 binary digits. the gate never reopens and the largest binary r e s i s t o r remains shorted out of the bridge. It may be concluded that proper application of the basic scheme can result in a system of outstanding accuracy. A decade resistance box with 0. coupled with high efficiency and inherent reliability. The design example presented here proves feasibility only. The direct digital output makes the unit quite compatible with modern digital telemetry systems. Also. A ninth s e r i a l pulse is easily provided for more reliable "reset" action and for a "transfer" pulse to a telemetry system o r word buffer. the tolerance of the bridge r e s i s t o r s used. Increasing bridge drive frequency should allow further increase in coding speed. The other control circuit operations take place during the sampling period for each binary r e s i s t o r . If the e r r o r signal is negative.
Maxwell. Strange of GSFC for his technical advice in the development of the demonstration model. Maxwell G. as the originator of the concept for the digital ohmmeter. Goddard Space Flight Center.I I I Ill Il I I Im111llIIl - ACKNOWLEDGMENTS The author wishes to cite M r .) 12 II I I111 111 I1111 I Ill I I II T . Marvin S. (Manuscript Received May 19. 1964. Many thanks are also due Mr.
4 R equivalent FOR SENSOR 0 ADD 0 I + 2. NASA-Langley. 56 + 0 0 + I 6. IF LIGHTS ARE AS SHOWN ABOVE + ACTUAL VALUE OF BINARY R ' s t + 0.5~ @20 W milliamp OUTPUTS FROM SCS ANODES bONE CELL FOR ALL UNITS 8 IDENTICAL UNITS-ONE FOR EACH BINARY DIGIT 1st BINARY DIGIT 2 5 6 + 1 2 8 + 64 + 32 + 1 6 + 8 + 4 0.Appendix A Lamp Indicator System for Bench Check of Digital Ohmmeter To facilitate bench checkout and demonstration of the system.6 DIVIDE BY 5 + 12.2 + 1 6 .4 + 3. a "0" Actual unknown resistance is easily calculated as shown for the sample readout.581 13 . .8 + 0 0 898=930.8 + 6. SUBMINIATURE LAMP mSUBMINIATURE 1. miniature lamps were used to indicate the state of each bit. A lighted lamp indicates a binary "1" and an off lamp. These are driven from the reed relay coils through separate amplifiers as shown in Figure A-1.4 0 + 0 + 0 0 t I 0.8 + 2 I 0 = Light ON = Light OFF 51. 1964 G.8ohms Figure A-1 -Lamp indicator c i r c u i t for bench checkout of system.2 + 25.
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