# Latches and flip-flops

In the same way that gates are the building blocks of combinatorial circuits, latches and flip-flops are the building blocks of sequential circuits. While gates had to be built directly from transistors, latches can be built from gates, and flip-flops can be built from latches. This fact will make it somewhat easier to understand latches and flip-flops. Both latches and flip-flops are circuit elements whose output depends not only on the current inputs, but also on previous inputs and outputs. The difference between a latch and a flip-flop is that a latch does not have a clock signal, whereas a flip-flop always does.

Latches
How can we make a circuit out of gates that is not combinatorial? The answer is feed-back, which means that we create loops in the circuit diagrams so that output values depend, indirectly, on themselves. If such feed-back is positive then the circuit tends to have stable states, and if it is negative the circuit will tend to oscillate. A latch has positive feedback. Here is an example of a simple latch:

This latch is called SR-latch, which stands for set and reset. It is not practical to use the methods that we have used to describe combinatorial circuits to describe the behavior of the SR-latch. Later, we will show a method for describing flip-flops and clocked sequential circuits. For now, we just rely on our intuition to describe how latches work. The SR-latch is meant to have at most one of its inputs equal to 1 at any time. When both of its inputs are 0 it has two different stable states possible. Either x is 0, in which case we have the following signal values:

or else x is 1, in which case we have the following signal values:

The actual value depends on the history of input values as we will show next. Now suppose that s is 1 (and therefore r is 0 since we allow at most one input to be 1 at any time). We get the following signal values:

The 1 on the s input makes sure the output of the upper nor-gate is 0, and the two 0s on the input of the lower nor-gate make sure the x output is 1. Now suppose the s input goes from 1 to 0, while the r input remains at 0. The second input of the upper nor-gate is 1, so the transition from 1 to 0 of the s input, does not make any difference. The x output remains at 1. In this case, if the s and r inputs are both 0, there is only one possible stable state, the one that gives x the value 1.

they become insensitive to further changes in input.. and therefore that of the entire flip-flop now contains the value of the D input right before the clock started changing. there are minor variations depending on the number of inputs and how they control the state of the flip-flop. i. When we need to draw an SR-latch. Finally. so the transition from 1 to 0 of the r input. By the time the D value reaches the master. From the discussion above. and turns them off .e. Now suppose the r input goes from 1 to 0. there are several fundamental types of flip-flops. allowing the x output of the master to be propagated to the x value of the slave. In this case. whereas the ones at the input of the slave are open. In this case. The output of the upper nor-gate remains at 1. s or r. last had the value of 1. which means that the output changes very soon after the input changes. A master-slave D-flip-flop is built from two SR-latches and some gates. The first thing that happens is that the and-gates at the input of the master turn off. while the s input remains at 0. the two and-gates in front of the input of the master are open. We can say that the clock transition copied the input to the output of the flip-flop. i. in the sense that it remembers which of the two inputs. A flip-flop is a synchronous version of the latch. does not make any difference. and the inverse of the D input to the r input of the master. For this to work. i. The second input of the lower nor-gate is 1. we conclude that the SR-latch is able to remember the last state of the inputs. there is only one possible stable state. on the other hand. their outputs are always 0. The value of the x output of the master is now the value of the D input right before the clock started changing. we shall only consider a type called master-slave flip-flop. A brief moment later. let us consider what happens when the clock goes from 1 to 0. if the s and r inputs are both 0. When instead the clock signal is 0. These gates open. Here.Conversely. suppose that r is 1 (and therefore s is 0 since we allow at most one input to be 1 at any time). the and-gates at the input of the master are closed. Here is the circuit diagram: The leftmost SR-latch is called the master and the rightmost is called the slave. the clock signal transition reaches the and-gates of the slave. letting the value of the D input into the master. The output changes only as a result of clock transitions from 1 to 0.. In this case.. In addition to the fundamental types of flip-flops. the value of the D input will go straight trough the master to the x output of the master. they let the value of the D-input through to the s input of the master.e.e. the one that gives x the value 0. we shall only consider a very simple type of flip-flop called a D-flip-flop. which means that the outputs of all the sequential circuits change simultaneously to the rhythm of a global clock signal. To complicate the situation even more. i. and the two 0s on the input of the upper nor-gate make sure the output of the upper norgate is 0. Now. the and-gates of the master open. But at no point in time is there a direct path from input to output. Let us first consider what happens when the clock signal is 1. Most computers today.. The x value of the slave. We get the following signal values: The 1 on the r input makes sure the x output is 0. Thus. But the two and-gates of the slave re closed. we have to assume that the input remains the same during a brief period from right before to right after the clock signal changes.e. Here. so the slave keeps its old value. we use the following symbol: Flip-flops Latches are asynchronous. First. the reverse is true. let us see what happens when the clock goes from 0 to 1. the flip-flop is completely insensitive to changes in input. are synchronous. the clock signal transition has traversed the inverter and reaches the andgates of the slave.

We can therefore use our general method for building combinatorial circuits. speed. the purpose is not to turn the students into circuit designers. but only a very general method that in the worst case may waste a large number of tansistors. With our definition. The value copied is the value the input has immediately before the clock transition. A more general definition separates the concept of output and the concept of state. Sometimes we do not draw the clock input at all when it is understood that it is there. all we need to do is to build a sequential circuit from the truth table corresponding exactly to this state table. our method uses n D-flip-flops (one for each output). the number of different states of the circuit is completely determined by the number of outputs. we define a synchronous sequential circuit. the D-flip-flop is insensitive to changes in the input. the slave keeps its old value. i.. In general. number of transistors. As an example. nothing seems to happen. It copies its input to its output as a result of a clock signal transition from 1 to 0. We shall use this key characteristic of the D-flip-flop to build synchronous sequential circuits. There is therefore little use to draw them all. Sequential circuits Introduction In the same way that combinatorial circuits are generalizations of gates. or just sequential circuit as a circuit with m inputs.e. From the outside. Here is the general structure of the resulting circuit: Since we are using D-flip-flops. the additional generality is not needed. Thus. power consumption etc. For a sequential circuit with m inputs and n outputs. Summary We have shown how to build a D-flip-flop. however. since the output does not change. However. The counter should stop at 00 when counting down and at 11 when counting up. and thereby clutter the diagram unnecessarily. Most of the clock period. n outputs. Four our purposes. Here is the symbol we use for D-flip-flops: The little triangle for the clock input indicates that this input is sensitive only to transitions as opposed to levels as described in the previous paragraph. the outputs of the circuit after the next clock pulse is exactly the same as the output of the combinatorial circuit. as with combinatorial circuits. We have intentionally simplified our definition of sequential circuit. let us construct a 2-bit counter with an input indicating whether to count up or down (0 means down and 1 means up). The description of the circuit is made with the help of a state table. and a distinguished clock input. and a combinatorial circuit with m + n inputs and n outputs.before the possibly modified output of the master reaches the slave. Clock signals are boring since they are all just connected to each other. From now on. the master is open to changes in the input. sequential circuits are generalizations of flip-flops. Here is the state table for such a counter: u/d y1 y0 | y1' y0' -------------------0 0 0 |0 0 0 0 1 |0 0 0 1 0 |0 1 0 1 1 |1 0 1 0 0 |0 1 1 0 1 |1 0 1 1 0 |1 1 1 1 1 |1 1 With our general method. Here is the resulting circuit: . and we stall stick with our simple definition. we are not going to discuss methods for obtaining optimal circuits. Thus. this time applied to the state table of the sequential circuit. The same "goodness" criteria apply to the design of sequential circuits as to combinatorial circuits. but to give them an idea of how sequential circuits work.

The memory elements are devices capable of storing binary info. All state transitions in such circuits occur only when the clock value is either 0 or 1 or happen at the rising or falling edges of the clock depending on the type of memory elements used in the circuit. Synchronous sequential circuits This type of system uses storage elements called flip-flops that are employed to change their binary value only at discrete instants of time. The input and the present state of the memory element determines the output. become unstable. Sequential circuits have a clock signal as one of their inputs. A sequential circuit is specified by a time sequence of inputs. at times. There are two types of sequential circuits. Combinational logic output depends on the inputs levels. Gate-type asynchronous systems are basically combinational circuits with feedback paths. the system may. outputs. The binary info stored in the memory elements at any given time defines the state of the sequential circuit. Their classification depends on the timing of their signals: y y y Synchronous sequential circuits Asynchronous sequential circuits Asynchronous sequential circuit This is a system whose outputs depend upon the order in which its input variables change and can be affected at any instant of time. Synchronization is achieved by a timing device called a clock pulse generator. whereas sequential logic output depends on stored levels and also the input levels. Synchronous sequential circuits that use clock pulses in the inputs are called clocked-sequential circuits. Because of the feedback among logic gates. and internal states. Synchronous sequential circuits use logic gates and flip-flop storage devices. Consequently they are not often used.Sequential Circuits Introduction Digital electronics is classified into combinational logic and sequential logic. Clock pulses are distributed throughout the system in such a way that the flip-flops are affected only with the arrival of the synchronization pulse. They are stable and their timing can . Memory elements next state is also a function of external inputs and present state.

We can overcome this problem with the circuit below. Clock cycle time or clock period: the time interval between two consecutive rising or falling edges of the clock.easily be broken down into independent discrete steps. is combinational logic with some feedback to maintain its current value. The circuit below is the same as the inverters connected back to back with provision to set the state of each gate (NOR gate with both inputs shorted is like a inverter). when LOW. Clock Frequency = 1 / clock cycle time (measured in cycles per second or Hz) Example:Clock cycle time = 10ns clock frequency = 100Mhz Concept of Sequential Logic A sequential circuit as seen in the last page. output keeps toggling. There is no way to tell. like a memory cell. The memory element we get is an RS Latch with active high Enable. When HIGH. I am not going to explain the operation. . The effect is that output oscillates between HIGH and LOW (i. Enable. A clock signal is a periodic square wave that indefinitely switches from 0 to 1 and from 1 to 0 at fixed intervals. when HIGH. Normally input enable signals can be of two types. which is basically cascading two inverters. presents S and R to the sequential logic input (the above circuit two NOR Gates). which is a simple NOT gate whose output is connected to its input. but in the above circuit. then oscillation frequency would be (on time + off time = 20ns) 50Mhz. masks the input S and R. as it is clear from the truth table. 1 and 0). y Level Sensitive or ( LATCH) y Edge Sensitive or (Flip-Flop) Level Sensitive: The circuit below is a modification of the above one to have level sensitive enable input. The equivalent circuit is the same as having a buffer with its output connected to its input. If we could know or set the value we would have a simple 1-bit storage/memory element. thus avoids toggling. in other words there is no enable signal to control when the input is sampled. The basic idea of having the feedback is to store the value or hold the value. Thus Enable. each of which is considered separately. we can not control when the input should be sampled. S 0 0 0 1 1 R 0 0 1 0 1 Q 0 1 X X X Q+ 0 1 0 1 0 There still seems to be some problem with the above configuration. Assuming a wire delay of 0 and a gate delay of 10ns. transfers input S and R to the sequential cell transparently. so this kind of sequential circuits are called transparent Latch.e. Oscillation frequency depends on gate delay and wire delay. To understand the basics let's consider the basic feedback logic circuit below. But there is a problem here too: each gate output value is stable. S is called set and R is called Reset. but what will it be? Or in other words buffer output can not be known. so that the feedback is in-phase.

So in simple words when S is HIGH and R is LOW. (This circuit is as we saw in the last page. Assuming Q = 0 and Q' = 1 as initial condition. Latches and Flip-Flops There are two types types of sequential circuits. As seen in last section. S and R. The output of the S-R latch depends on current as well as previous inputs or state. Synchronous Circuits. The S input is used to produce HIGH on Q ( i. y When S = 0 and R = 0: If we assume Q = 1 and Q' = 0 as initial condition.e. so it always holds the opposite value of Q. S 0 0 0 1 1 R 0 0 1 0 1 Q 0 1 X X X Q+ 0 1 0 1 0 The operation has to be analyzed with the 4 inputs combinations together with the 2 possible previous states.Edge Sensitive: The circuit below is a cascade of two level sensitive memory elements. The R input is used to produce LOW on Q (i. So it is clear that when both S and R inputs are LOW. So in simple words when S is LOW and R is HIGH. output Q is HIGH. let's look at each of them in detail in accordance to what is taught in colleges. Flip-flops and latches which use this control signals are called synchronous circuits. Q' is Q complementary output. y y y RS Latch RS latch have two inputs. store binary 1 in flip-flop). the output is retained as before the application of inputs. So the Edge Sensitive element we get is called negative edge RS flip-flop. You are always welcome to suggest if this can be written better in any way. store binary 0 in flip-flop). then output Q after input is applied would be Q = (R + Q')' = 1 and Q' = (S + Q)' = 0.e. output Q is LOW. then output Q after the input applied would be Q = (R + Q')' = 0 and Q' = (S + Q)' = 1. (i.e. this HIGH to LOW transition is called falling edge. The circuit and the truth table of RS latch is shown below.e. and its state (value stored) can change as soon as its inputs change. then output Q after input is applied would be Q = (R + Q')' = 1 and Q' = (S + Q)' = 0. When S = 0 and R = 1: If we assume Q = 1 and Q' = 0 as initial condition. The net effect is input RS is moved to Q and Q' when CLK changes state from HIGH to LOW. So if they don't use clock inputs. y y . then output Q after the input applied would be Q = (R + Q')' = 1 and Q' = (S + Q)' = 0. then output Q after input is applied would be Q = (R + Q')' = 0 and Q' = (S + Q)' = 1. The first RS latch (i. the first memory element) will be enabled when CLK input is HIGH and the second RS latch will be enabled when CLK is LOW. Assuming Q = 0 and Q' = 1 as initial condition. then they are called asynchronous circuits. When S = 1 and R = 0: If we assume Q = 1 and Q' = 0 as initial condition. Latches and Flip-flops are one and the same with a slight variation: Latches have level sensitive control signal input and Flip-flops have edge sensitive control signal input. but arranged to look beautiful :-) ). with a phase shift in the enable input between first memory element and second memory element. then output Q after the input applied would be Q = (R + Q')' = 0 and Q' = (S + Q)' = 1. Asynchronous Circuits. there is no state change). S is called set and R is called reset. Assuming Q = 0 and Q' = 1 as initial condition. Now that we know the sequential circuits basics.

Hold Time: Minimum time period during which data must be stable after the clock has made a valid transition.e. So in this case the R = 0 and S = 0 case becomes the invalid case. LOW in both the outputs basically is wrong. which results in both Q and Q' set to LOW (i.e. for a posedge triggered flip-flop. for a posedge triggered flip-flop. it drives LOW to both inputs of RS latch. S 1 1 0 1 0 R 1 1 1 0 0 Q 0 1 X X X Q+ 0 1 0 1 1 If you look closely. RS Latch with Clock We have seen this circuit earlier with two possible input configurations: one with level sensitive input and one with edge sensitive input. As we saw in previous page. so this case is invalid. R and S in the case of RS flip-flop) should be stable for at least 1 ns after clock has made transition from 0 to 1. The circuit and Truth table of RS latch using NAND is shown below. values are retained (i. The circuit below shows the level sensitive RS latch. For example.e. the output does not change). . there is no control signal (i. Q = Q'). Since all the sequential circuits are built around the RS latch. with a setup time of 2 ns. When Enable E is HIGH.e. so this kind of latches or flip-flops are called asynchronous logic elements. when both inputs of a NOR latch are low. both the AND gates act as buffers and thus R and S appears at the RS latch input and it functions like a normal RS latch. y Setup and Hold Time For synchronous flip-flops. The waveform below shows the operation of NOR gates based RS Latch. They are y y Setup Time: Minimum time period during which data must be stable before the clock makes a valid transition. For example. When Enable E is LOW. we have special requirements for the inputs with respect to clock signal input.e.When S = 1 and R =1 : No matter what state Q and Q' are in. with a hold time of 1 ns. The only difference is that NAND is NOR gate dual form (Did I say that in Logic gates section?). no clock and no enable). Input Data (i. y It is possible to construct the RS latch using NAND gates (of course as seen in Logic gates section). we will concentrate on synchronous circuits and not on asynchronous circuits. R and S in the case of RS flip-flop) should be stable for at least 2 ns before clock makes transition from 0 to 1. application of 1 at input of NOR gate always results in 0 at output of NOR gate. Input Data (i. Control signal "Enable" E is used to gate the input S and R to the RS Latch.

Thus we have D Latch: the same as the RS latch. with the only difference that there is only one input.If data makes transition within this setup window and before the hold window. D latch is called D transparent latch for the reasons explained earlier. which is similar to the RS latch one. You could refer to tidbits section to know more information on this topic. y D Latch The RS latch seen earlier contains ambiguous state. which is not there in the RS latch. then the flip-flop output is not predictable. Delay flip-flop or delay latch is another name used. This is done by connecting S and R together with an inverter. output toggles. but with R removed. The waveform below shows input S (R is not shown). instead of two (R and S). D 1 0 Q X X Q+ 1 0 Below is the D latch waveform. . y JK Latch The ambiguous state output in the RS latch was eliminated in the D latch by joining the inputs with an inverter. to eliminate this condition we can ensure that S and R are never equal. and flip-flop enters what is known as meta stable state. In real world designs (ASIC/FPGA Designs) only D latches/Flip-Flops are used. It takes some time for the flip-flop to settle down. The only difference we see here is output feedback to inputs. The ambiguous state has been eliminated here: when both inputs are high. and CLK and output Q (Q' is not shown) for a SR posedge flip-flop. But the D latch has a single input. The whole process is called metastability. Below is the truth table and circuit of D latch. In this state flip-flop output oscillates between 0 and 1. This input is called D or Data input. JK latch is similar to RS latch in that it has 2 inputs J and K as shown figure below.

It is called T latch as.J 1 1 1 0 K 1 1 0 1 Q 0 1 1 0 y T Latch When the two inputs of JK latch are shorted. output toggles. when input is held HIGH. T 1 1 0 0 Q 0 1 1 0 Q+ 1 0 1 0 . a T Latch is formed.