Nagendra Krishnapura
18 October 2014
1 / 135
Motivation
2 / 135
Outline
3 / 135
Negative feedback with integrator as the central
element
4 / 135
Outline
5 / 135
Traditional introduction to negative feedback systems
Vi Vo
+
Σ A
β
• Algebraic system—cannot explain evolution over time
• Unstable with arbitrarily small loop delay
• Ideal delay Td in the loop ⇒ oscillations with a period 2Td
• Real systems have nonzero delay and don’t respond
instantaneously
6 / 135
Intuitive understanding of negative feedback systems
7 / 135
Example: Driving a car at a given target speed
target speed
speed error output
Σ controller
+
speedometer
speedometer reading
• Compare the sensed speed to the target
• Speedometer reading to desired speed
• Compute (mentally) the difference
• ⇒ Look at the speedometer!
• Keep accelerating (or braking) until error goes to zero
8 / 135
Example: Driving a car at a given target speed
target speed
speed error output
Σ controller
+
speedometer
speedometer reading
• You don’t know how much to press the accelerator or the
brake to obtain the desired speed
• You keep on doing it until the sensed speed is the same as
the target
9 / 135
Other examples
• Driving a car
• Controlling the volume: Keep turning the volume knob until
the sensed volume (what your hear) matches target
volume (that you find comfortable)
10 / 135
Nature of the controller
target constant
(e.g. speed) error output
Σ controller
+
stuck sensor
(e.g. speedometer)
sensor output stuck
large error
large error
output
error
11 / 135
Negative feedback system with an integrator
12 / 135
Negative feedback amplifier
Vi Ve Vo
Σ ωu dt
+
(k1)R
Vfb
R
computing
the error
sensing
the output
13 / 135
Integrator in the negative feedback amplifier
Vo [V]
4 Ve=1V
Ve Vo = ωu Ve dt 3 ωu = 109 rad/s
ωu dt
2
1 ωu = 2.5x108 rad/s
t [ns]
1 2 3 4
• Proportionality constant ωu
• Slope of the output = ωu Ve
14 / 135
Integrator: Frequency domain
ωu/jω
ωu=109 rad/s
20dB/decade ωu=2.5x108 rad/s
ωu V (s) ω (log)
Ve(s) ωu Vo(s) = e 107 108 109
s [rad/s]
s <ωu/jω
107 108 109
ω (log)
−π/2 [rad/s]
15 / 135
Integrator: Summary
Vo [V]
4 Ve=1V
Ve Vo = ωu Ve dt 3 ωu = 109 rad/s
ωu dt
2
1 ωu = 2.5x108 rad/s
t [ns]
1 2 3 4
ωu/jω
ωu V (s) 20dB/decade
Ve(s) ωu Vo(s) = e
s
s
ω (log)
107 108 109
[rad/s]
16 / 135
Negative feedback amplifier with constant input
Negative feedback amplifier, k=4, ω =109 rad/s Negative feedback amplifier, k=4, ω =109 rad/s
u u
5 5
Input V
i
4.5 Feedback V 4.5
f
4 Error Ve 4
3.5 3.5
3 3
Volts
Volts
2.5 2.5
2 2
1.5 1.5
1 1
Ideal output 4Vi
0.5 0.5 Actual output Vo
0 0
0 1 2 3 4 5 6 0 1 2 3 4 5 6
time [ns] time [ns]
17 / 135
Negative feedback amplifier with constant input
4.5
4
Vi Ve Vo
ωu dt
+ Σ
3.5
 (k1)R 3
Vf
Volts
2.5
2
R
1.5 Input Vi
Ideal output 4Vi
1
Initial condition=0V
0.5 Initial condition=2V
Initial condition=5V
0
0 1 2 3 4 5 6
time [ns]
dVo Vo
= ωu Vi − (1)
dt k
ωu ωu
Vo (t) = kVi 1 − exp(− t) + Vo (0) exp(− t) (2)
k k
18 / 135
Negative feedback amplifier—Steady state
Vi Ve=0 Vo
Σ ωu dt
+
(k1)R
Vfb = Vi
R
19 / 135
Opamp for implementing a negative feedback amplifier
Vi +
Vi Ve Vo + Vo
Σ ωu dt Ve ωu
+  −
(k1)R
(k1)R
Vfb
Vfb
R
computing
the error
20 / 135
Time domain behavior with constant/step inputs
Vi +
Vi Ve Vo + Vo
Σ ωu dt Ve ωu
+  −
(k1)R
(k1)R
Vfb
Vfb
R
computing
the error
1 dVo Vo
= Vi −
ωu dt k
ω
u
Vo (t) = kVp 1 − exp − t
k
• Time constant k /ωu
• Asymptotically reaches Vo = kVi or Vfb = Vi
21 / 135
Relation to frequency domain analysis
ωu ωu,loop
Loop gain L(s) = =
ks s
Frequency domain:
• Unity loop gain frequency ωu,loop
• Significant negative feedback up to ωu,loop ⇒ nearly ideal
behavior up to ωu,loop (Closed loop Bandwidth)
1
τloop =
ωu,loop
Time domain:
• Unit step response of the loop gain
= t/(1/ωu,loop ) = t/τloop
• Closed loop response time constant = 1/ωu,loop = τloop
22 / 135
Advantages of this formulation
23 / 135
Controlled sources using an opamp
24 / 135
Voltage controlled voltage source
Vi +
Vo
−
(k1)R
Vfb = Vi
R
• VCVS: Vo = kVi
• Compare Vo /k to Vi and drive the output with the integral
of the error
• For constant Vi , Vo = kVi in steady state
25 / 135
Current controlled voltage source
0 +
Vo
−
Ii Rf
VoIiRf
• VCVS: Vo = Rf Ii
• Compare Vo − Rf Ii to 0 and drive the output with the
integral of the error
• For constant Ii , Vo = Rf Ii in steady state
26 / 135
Voltage controlled current source
Vi + Io
Vopa load
−
+ V
− opa
Io
Io/Gm
R=1/Gm
• VCCS: Io = Gm Vi
• Compare Io /Gm to Vi and drive the output with the integral
of the error
• For constant Vi , Io = Gm Vi in steady state
27 / 135
Current controlled current source
0 + Io
Vopa load
−
+ V
− opa
Ii (k1)R Io
IoRkIiR
Ii R
• CCCS: Io = kIi
• Compare (Io − kIi )R to 0 and drive the output with the
integral of the error
• For constant Ii , Io = kIi in steady state
28 / 135
Negative feedback amplifier with delay
29 / 135
Effect of delay on negative feedback
3
target
2.5 output
feedback
2 error
1.5
0.5
−0.5
−1
−1.5
−2
0 1 2 3 4 5
0.5
−0.5
−1
−1.5
0 2 4 6 8 10
32 / 135
Negative feedback amplifier with delay in the loop
Vi Ve Vo
Σ ωu dt
+
(k1)R
Vfb
delay Td
R
• Td /τloop ≤ 1/e(= 0.367): No overshoot
• 1/e < Td /τloop < π/2: Overshoot + ringing
• π/2 < Td /τloop : Unstable
1.8
1.6
1.4
Vo [normalized to kVi]
1.2
0.8
Td/(k/ωu) = 0
0.6
T /(k/ω ) = 1/e
d u
0.4 T /(k/ω ) = 0.5
d u
Td/(k/ωu) = 1.0
0.2
T /(k/ω ) = 1.5
d u
0
0 2 4 6 8 10
time [normalized to k/ω ]
u
34 / 135
Negative feedback amplifier with delay in the loop
35 / 135
Eliminating instability in presence of delay
36 / 135
Delays in circuit implementation—parasitic poles and zeros
QM
ωu,loop (1 + s/zk )
Loop gain L(s) = · QNk =1
s
 {z }  k =2 (1{z+ s/pk )}
Ideal Parasitic
slope=ωu,loop slope=ωu,loop
Td Td
t t
Unit step response of L(s) is a ramp of slope ωu,loop (same as
P PM
ideal) with a delay Td = N k =1 1/pk − k =1 1/zk
37 / 135
Closed loop response with equivalent delay
38 / 135
Advantages of this formulation
39 / 135
Advantages of this formulation
• Traditional viewpoint
• Memoryless amplifier (loop gain) in the ideal case
• Frequency dependence as nonideal feature
• Proposed viewpoint
• Integrator in the ideal case (∞ dc gain)
• Finite dc gain due to nonideal implementation
• As easy as the “gain model” to convert to ideal opamps
40 / 135
Opamp models
Vout/Vd (dB)
finite dc gain model: A0
first order model: A0/(1+s/ωd)
integrator model: ωu/s
full model: A0/(1+s/ωd)(1+s/p2)(1+s/p3) ...
A0
p2 p3
ωd ωu ω
41 / 135
Advantages of this formulation
42 / 135
Advantages of this formulation
43 / 135
Advantages of this formulation
44 / 135
Advantages of this formulation
45 / 135
References
Adel S. Sedra and Kenneth C. Smith, Microelectronic Circuits, 6th ed., Oxford University Press 2009.
Paul R. Gray, Paul J. Hurst, Stephen H. Lewis, Robert G. Meyer, Analysis and Design of Analog Integrated
Circuits, 5th ed., Wiley 2009.
Nagendra Krishnapura, “Introducing Negative Feedback with an Integrator as the Central Element,” Proc.
2012 IEEE ISCAS, May 2012.
Nagendra Krishnapura, “Synthesis Based Introduction to Opamps and Phase Locked Loops,” Proc. 2012
IEEE ISCAS, May 2012.
Karl J. Astrom and Richard M. Murray, “Feedback Systems: An Introduction for Scientists and Engineers,”
Available:
http://www.cds.caltech.edu/∼murray/amwiki/index.php/Main_Page
Hal Smith, An Introduction to Delay Differential Equations with Applications to the Life Sciences, 1st ed.,
Springer 2010.
46 / 135
Synthesis of opamp topologies
47 / 135
Opamp (integrator) realization
+ + Igm
Vout Vout,buf
Ve − 1

Gm1 C1
Z
Gm1
Vo = Ve dt (3)
C1
Z
= ωu Ve dt (4)
(5)
• Gm − C integrator
• ωu = Gm1 /C1
48 / 135
Opamp (integrator) realization—Finite dc gain
+ + Igm
Vout Vout,buf
Ve − 1

Gm1 Ro1 C1
49 / 135
Steady state error due to finite dc gain
Step response
1
0.9
0.8
0.7
0.6
0.5
V
0.4
0.3
0.2
0.1 Ideal
Ao=10
0
0 2 4 6 8 10
t/τ
50 / 135
Opamp (integrator) realization
+ + Igm
Vout Vout,buf
Ve − 1

Gm1 Ro1 C1
51 / 135
Transimpedance amplifier for better IV conversion
part of IGm(=Vo/Rout)
IGm Ro1 Zc
52 / 135
Transimpedance amplifier for better IV conversion
smaller part of
IGm(=Vx/Rout) VoIGmZc Zc
part of IGm(=Vo/Rout)
IGm Ro1 Zc IGm Ro1
+ −
Vo
Vx ωu
 +
53 / 135
Improved IV conversion—Two stage opamp
+ + Igm
Ve −

Gm1 Ro1 C1
54 / 135
Improved IV conversion—Two stage opamp
C1
Ve=VoIGmZc
integrator
+ + Igm + Igm
− Vo
Ve − Ve −ωu2 dt
  +
monitors Ve and
continuously adjusts
Vo until Ve→0
55 / 135
Improved IV conversion—Two stage opamp
C1
Ve=VoIGmZc
integrator
+ + Igm + Igm
− Vo
Ve − Ve −ωu2 dt
  +
monitors Ve and
C1 continuously adjusts
Vo until Ve→0
+ Igm
−
Ve −
 +
+
Gm1 Ro1
Gm2 Ro2 C2
56 / 135
Negative feedback amplifier: Frequency domain
ωu/s A(jω)
loop gain
Vi Ve Vo
ωu dt
+ Σ
 (k1)R ωu ω (log)
ωu/k
Vf Vo/Vi
ideal over this band
R
k
ω (log)
ωu/k
57 / 135
Negative feedback amplifier: Frequency domain
9
Negative feedback amplifier, k=4, ω =109 rad/s Negative feedback amplifier, k=4, ω =10 rad/s
u
u
1
1 10
0.8
Magnitude
0
0.6 10
0.4
−1
0.2 10
ω [Grad/s]
−2 −1 0 1
10 10 10 10
0
−0.4
Phase
−0.6 −50
−0.8
−1 −100 −2 −1 0 1
−1 −0.5 0 0.5 1 10 10 10 10
σ [Grad/s] ω [Grad/s]
ωu Vo
Vo (s) = Vi − (6)
s k
Vo (s) k
= (7)
Vi (s) 1 + ωus/k
Vo (jω) k
= jω
(8)
Vi (jω) 1+ ωu /k
Vo (jω) k Vo (jω) ω
V (jω) = r ; ∠ = − tan−1 (9)
i
2 Vi (jω) ωu /k
1 + ωuω/k
59 / 135
Negative feedback amplifier: Low frequency input
9
Vo (jω) k
V (jω) = (10)
Negative feedback amplifier, k=4, ω =10 rad/s
4
u r 2
input i ω
3 ideal output
actual output 1+ ωu /k
2
1 Vo (jω) ω
∠ = − tan−1 (11)
Vi (jω) ωu /k
Volts
−1
(12)
Input at 0.1ωu/k
−2
−3
−4
0 50 100 150 200 250
time [ns] • Nearly ideal behavior
• Gain k , delay k /ωu
60 / 135
Negative feedback amplifier: High frequency input
9
Vo (jω) k
V (jω) = (13)
Negative feedback amplifier, k=4, ωu=10 rad/s
4
r 2
input i ω
3 ideal output
actual output 1+ ωu /k
2
1 Vo (jω) ω
∠ = − tan−1 (14)
Vi (jω) ωu /k
Volts
−1
(15)
Input at 10ωu/k
−2
−3
−4
0 0.5 1 1.5 2 2.5
time [ns] • Attenuated output
• Nearly 90◦ phase lag
61 / 135
Intuition about two stage opamp constraints
62 / 135
Further improved IV conversion—Three stage opamp
C1
Ve=VoIGmZc
integrator
+ + Igm + Igm
− Vo
Ve − Ve −ωu2 dt
  +
monitors Ve and
continuously adjusts
Vo until Ve→0
63 / 135
Further improved IV conversion—Three stage opamp
C1
Ve=VoIGmZc
integrator
+ + Igm + Igm
− Vo
Ve − Ve −ωu2 dt
  +
C2
+ Igm
− +
Ve Vout
 + − −
Gm1 Ro1 +
Gm2 Ro2
Gm3 Ro3 C3
two stage opamp
64 / 135
Further improved IV conversion—Three stage opamp
C1
C2
+ Igm
− +
Ve Vout
 + − −
Gm1 Ro1 +
Gm2 Ro2
Gm3 Ro3 C3
two stage opamp
65 / 135
Intuition about three stage opamp constraints
66 / 135
Follow up in the frequency domain
67 / 135
Opamp (integrator) realization—Finite dc gain
Vi + Igm
+
Ve  −
Gm1 Ro1 C1
68 / 135
Opamp realization—Supply extra current from another
source
monitor Ve and
continuously adjust
Ioff until Ve=0
Ioff
Vi + Igm Vi + Igm
+
Ve  − +
Ve  −
69 / 135
Opamp realization—Additional negative feedback control
integrator
+
Kpd,I dt
−
Gm2a Ioff
+ Igm
Vi Vo
Ve +
 −
Gm1 Ro1 C1
70 / 135
Opamp realization—Additional negative feedback control
integrator
+
+ +
Kpd,I dt −
− −
Gm2 Ro2 C2
Gm2a Ioff Gm2a Ioff
+ Igm opamp + Igm
Vi Vo Vi Vo
Ve +
 − Ve +
 −
71 / 135
Two stage feedforward opamp
+
+
−
−
Gm2 Ro2 C2 Gm2a Ioff
opamp + Igm
Vi
Ve +
 −
Gm1 Ro1 C1
72 / 135
Intuition about feedforward opamp constraints
73 / 135
Feedforward opamp settling
74 / 135
Feedforward opamp settling
Step response
1
0.9
0.8 1
0.7 0.99
0.6 0.98
0.5
V
0.97
0.4 0.96
45 46 47 48 49 50
0.3
Gm1 Ro1 C1
76 / 135
Follow up in the frequency domain
77 / 135
Advantages of this formulation
78 / 135
Synthesis of phase locked loop topologies
79 / 135
Outline
80 / 135
Phase locked loops
81 / 135
Local oscillator requirements
10kHz interchannel spacing
bandwidth
channel
Broadcast AM band spacing 0.15MHz Broadcast FM band
0.2MHz
1610kHz
fc
530kHz
88.2MHz
88MHz
108MHz
5kHz
channel channel
spacing spacing
0.2MHz 0.2MHz
GSM uplink band GSM downlink band
890.2MHz
960MHz
890MHz
935.2MHz
915MHz
935MHz
• Tuned to the desired channel frequency plus an
intermediate frequency (IF)
• Generate equally spaced frequencies from a reference
frequency 82 / 135
Frequency divider
Vref
R(N1)
fref fref/N
Vref/N N
R frequency
divider
83 / 135
Frequency multiplication analogous to voltage amplification
frequency
error
Vi Ve Vo fref fe fout
ωu dt ωu dt
+ Σ input + 
Σ
output
 (k1)R
Vf frequency frequency
1/N
R fout/N
84 / 135
Frequency multiplication
frequency difference
input zero, at steady state
signal fout = ffree+KvcoVctl
at fref fref Vctl
frequency
measure + Σ γ dt
output

signal
VCO at fout
fout/N
frequency
measure N
frequency
divider
85 / 135
Phase and frequency
• Sinusoid: cos(θ(t))
• Phase: θ(t)
• Instantaneous frequency: fi = 1 dθ(t)
2π dt
• Typically expressed as fi = fo + fe (t)
• fo : average frequency
• fe : instantaneous frequency error
R
• Phase θ(t) = 2πfo t + Φo + 2π fe (t)dt
• Phase θ(t) = 2πfo t + Φo + φ(t)
• Φo : phase offsetideal ramp versus time
• φ(t): instantaneous phase
86 / 135
Phase error
70
ideal phase
error
60 phase with error
50
40
30
20
10
−10
0 2 4 6 8 10
87 / 135
Integrate frequency difference ⇒ Phase difference
input
signal fout = ffree+KvcoVctl
at fref measure Vctl
frequency γ dt + Σ
 output
signal
measure phase VCO at fout
measure
γ dt frequency N
88 / 135
TypeI phase locked loop
fout = ffree+KvcoVctl
input signal at fref
phase Vctl
detector output signal
at fout
VCO
frequency
divider
• Phase detector and VCO in a loop
89 / 135
Voltage controlled oscillator
slope = Kvco
fout
Vctl fout=KvcoVctl+fo fo
Vctl
2πfot
Vctl + θvco
+
2πKvco dt Σ
90 / 135
Phase detector
φ1 Kpd(φ1φ2)
phase
φ2 detector
• Kpd : Phase detector gain in V/radian
• Ideal phase detector: assumed to have an output
Vpd = Kpd (φ1 − φ2 )
91 / 135
TypeI phase locked loop
In steady state, output signal at fout
Vctl = (foutffree)/Kvco (fout=Nfref at
input signal steady state)
at fref
Kpd∆Φ Vctl
Kpd
∆Φ = ΦrefΦout/N
phase VCO
detector
In steady state,
∆Φ = (foutffree)/KvcoKpd N
frequency
divider
92 / 135
Phase locked loop model
2πfot
2πfout/N t+Φvco/N
1/N
2πfot
1/N
2πfout/N t+Φout/N+φout/N
94 / 135
Phase locked loop model—incremental picture
φout/N
1/N
95 / 135
Phase locked loop model—frequency domain
φref(s) vctl(s) 2πKvco φout(s)
+ Σ Kpd
s

φout(s)/N
1/N
97 / 135
Phase detector
98 / 135
Tristate phase detector
1 QA
A A D Q
A
ref RST
B 1 0 +1 A
B RST
div
QB
B B 1
D Q
output=QAQB
99 / 135
Tristate phase detectorwaveforms
Tref Tref
+1 +1
A 1
A 1
+1 +1
B B
1 1
+1 +1
QA QA
+1 +1
QB QB
ΦrefΦdiv ΦdivΦref
A leading B A lagging B
100 / 135
Tristate phase detectorfrequency difference between inputs
1 QA
A A D Q
A
ref RST
B 1 0 +1 A
B RST
div
QB
B B 1
D Q
output=QAQB
101 / 135
Tristate phase detector output
Tref
+1
reference
1
reference
Tristate pdout
+1 phase
divider o/p
divider o/p detector
1
+1
pdout Average value = ∆Φ/π
1 Tref Output periodic at fref
∆Φ = ΦrefΦdiv
∞
∆Φ X n∆Φ
Vout (f ) = sinc δ(f − nfref )
2π n=−∞ 2π
∞
∆Φ ∆Φ X n∆Φ
Vout (t) = + sinc cos(2πnfref t)
2π π 2π
n=1
102 / 135
Tristate phase detector
103 / 135
Phase detectorOutput spectrum
∆Φ=π/2
0.6
0.4
0.2
−0.2
0 2 4 6 8 10
∆Φ=π/8
0.5
−0.5
0 2 4 6 8 10
f/f
ref
104 / 135
PLL with tristate phase detector—periodic error
Σn ancos(2πnfreft) ("error")
φvco/N
1/N
50
40
30
20
10
−10
0 2 4 6 8 10
106 / 135
PLL with tristate phase detector—frequency domain
E(s) E(j2πf) = Σn an/2 δ(f±nfref)
φvco(s)/N
1/N
107 / 135
TypeI PLL
dB
2πKpdKvco/N
ω
L/(1+L)
φout/φref
dB
20log(N)
ω
2πKpdKvco/N
(loop bandwidth)
109 / 135
Feedback system
In our system,
L(s)
Hclosedloop (s) = Hideal (s) (23)
1 + L(s)
(24)
Where Hideal (s) is the ideal closed loop gain (with L = ∞). This
can be approximated as
110 / 135
PLL with tristate phase detector—Output signal
Considering only the term at fref , and b1 ≪ 1
b1 = a1 H(j2πfref ) (34)
Kpd Kvco /jNfref
= a1 N
(35)
1 + Kpd Kvco /jNfref
Kpd Kvco
≈ a1 N
(36)
jNf ref
Nf−3dB ∆Φ
= 2∆Φ sinc (37)
fref 2π
112 / 135
Reference feedthrough—example
113 / 135
TypeI phase locked loop
frequency
divider
114 / 135
Changing the free running frequency of a VCO
Voff
Vctl (ffree+KvcoVoff)+KvcoVctl Vctl ffree’+KvcoVctl
Σ
VCO VCO
ffree’ = ffree+KvcoVoff
115 / 135
Slowly change the bias until ∆φ = 0
monitor ∆Φ and
continuously adjust
Voff until ∆Φ=0
+ output signal at fout
−
(fout=Nfref at
input signal steady state)
at fref Voff
Kpd∆Φ
Kpd Σ
∆Φ = ΦrefΦout/N
phase ffree’ VCO
detector
N
frequency
divider
116 / 135
Slowly change the bias until ∆φ = 0
integral
phase
detector In steady state,
Kpd,I ∆Φ dt Voff = (foutffree)/KvcoKpd
∆Φ Kpd,I dt
output signal at fout
(fout=Nfref at
input signal steady state)
at fref Voff
Kpd∆Φ
Kpd Σ
∆Φ = ΦrefΦout/N
phase ffree’ VCO
detector
In steady state,
∆Φ = 0 N
frequency
divider
117 / 135
TypeII phase locked loop
phase detector + loop filter
integral
phase
detector
Kpd,I ∆Φ dt
∆Φ Kpd,I dt
output signal at fout
proportional (fout=Nfref at
input signal phase steady state)
at fref detector
Kpd∆Φ
Kpd Σ
∆Φ = ΦrefΦout/N
VCO
In steady state,
∆Φ = 0 N
118 / 135
TypeII PLL with a tristate phase detector
119 / 135
TypeII PLL—phase model
zero at
steady state 2πfot
Kpd,I dt
2πfreft+Φref + Vctl + 2πfout t+Φout
+
+ Σ Σ 2πKvco dt Σ
 +
Kpd
2πfout/N t+Φout/N
1/N
120 / 135
TypeII PLL—incremental model
zero at
steady state
Kpd,I dt
2πfreft+Φref + Vctl 2πfout t+Φout
+ Σ Σ 2πKvco dt
 +
Kpd
2πfout/N t+Φout/N
1/N
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TypeII PLL—incremental model
Kpd,I
s
φref(s) + vctl(s) 2πKvco φout(s)
+ Σ Σ
s
 +
Kpd
φout(s)/N
1/N
122 / 135
TypeII PLL—Frequency domain
p1 > 2πKpdKvco/N
Kpd,I more poles can be used
s
φref(s) + vctl(s) 1 Vctl 2πKvco φout(s)
+ Σ Σ
1+s/p1 s
 +
Kpd
φout(s)/N
1/N
123 / 135
TypeII PLL—Implementation
Tref
reference
iout reference
iout
+1 tristate tristate
phase phase
reference
1 divider o/p
detector + divider o/p
detector
+
R1 proportional R1
∆Φ = ΦrefΦdiv proportional
output
+1 + integral
divider o/p 
output
1 C1
reference
iout
tristate
+Icp phase
pdout 
divider o/p
detector +
Icp C1 integral
output
proportional +IcpR
output

IcpR
integral
slope=Icp/C
output
124 / 135
Tristate phase detector with charge pump
Vdd
Icp
1 QA (UP)
D Q
A
ref RST iout
+
B RST R1
div proportional
QB (DN) + integral
D Q output
1
C1
Icp 
125 / 135
Noise sources in a PLL
Kpd,I vnc φvco
s
φref + 2πKvco φout
+ Σ Σ Σ
s
Σ
 +
Kpd
φout/N
1/N
ωu,loop z1 s
L(s) = 1+ (38)
s s z1
2πKpd Kvco Icp RKvco
ωu,loop = = (39)
N N
Kpd,I 1
z1 = = (40)
Kpd RC
φout (s) 1 + s/z1
= N (41)
φref (s) 1 + s/z1 + s2 /z1 ωu,loop
φout (s) N s/z1
= (42)
Vnc (s) Kpd 1 + s/z1 + s2 /z1 ωu,loop
φout (s) s2 /z1 ωu,loop
= (43)
φvco (s) 1 + s/z1 + s2 /z1 ωu,loop
127 / 135
TypeII PLL: transfer functions
L(s) 1 + s/z1
= (44)
1 + L(s) 1 + s/z1 + s2 /z1 ωu,loop
−5
/φ  [dB]
2
ref
1
−10
out
1/Nφ
−15 −1 −3 −2 −1 0
10 10 10 10
−20 ζ=4.08
ζ=0.3162
ζ=1
−25 −3 −2 −1 0 1
10 10 10 10 10
ω/ω
u,loop
20
10
Magnitude response [dB]
−10
−20
−30
−40
−50 φout/φref
φ /v *1V
out nc
−60
φout/φvco
−70 −2 −1 0 1 2
10 10 10 10 10
f/f
u,loop
(Example parameters:
N = 10, z1 = 0.1ωu,loop , N/Kpd = 2πKvco /ωu,loop = 25 V−1 )
• φout /φref : Lowpass with a dc gain N
• φout /vnc : Bandpass with peak gain N/Kpd = 25 V−1
• φout /φvco : Highpass with a high frequency gain of 1
130 / 135
TypeII PLL phase noise example
PLL phase noise components
−20
−40
−60
−80
dBc/Hz
−100
−120
−140 reference
ref. contribution to PLL
−160 VCO
VCO contribution to PLL
Total
−180 −2 −1 0 1 2
10 10 10 10 10
f/f
u,loop
(Example parameters:
N = 10, z1 = 0.1ωu,loop , N/Kpd = 2πKvco /ωu,loop = 25 V−1 )
• Reference contribution dominant below 0.1ωu,loop
• VCO contribution dominant above 0.1ωu,loop
• VCO contribution reduced by the loop upto ωu,loop
• Charge pump and loop filter noise ignored in the above
131 / 135
Intuition about the Phase locked loop
132 / 135
Analysis of typeII phase locked loop
133 / 135
Conclusions
134 / 135
References
Paul R. Gray, Paul J. Hurst, Stephen H. Lewis, Robert G. Meyer, Analysis and Design of Analog Integrated
Circuits, 5th ed., Wiley 2009.
Nagendra Krishnapura, “Introducing negative feedback with an integrator as the central element,” Proc. 2012
IEEE ISCAS, May 2012.
Roland Best, Phase Locked Loops: Design, Simulation and Applications, 5th ed., McGrawHill 2007.
Stanley Goldman, Phase Locked Loop Engineering Handbook for Integrated Circuits, Artech House 2007.
Behzad Razavi, Design of Analog CMOS Integrated Circuits, 1st edition, McGrawHill, 2000.
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