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# Synthesis of opamp and phase-locked loop

## topologies from first principles

IEEE CAS SBC Workshop on
Advanced Topics in VLSI Circuit Design
Roorkee, India

Nagendra Krishnapura

## Department of Electrical Engineering

Indian Institute of Technology, Madras
Chennai, 600036, India

18 October 2014
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Motivation

## • Intuition before full blown analysis

• Synthesis instead of ad-hoc introduction
• Time domain reasoning/analysis
• More intuitive
• Exact analysis difficult for complex systems
• Frequency domain analysis
• More abstract
• Can handle complex systems easily

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Outline

## • Negative feedback with integrator as the central element

• Synthesis of opamp topologies
• Synthesis of phase locked loop topologies
• Conclusions

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Negative feedback with integrator as the central
element

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Outline

## • Traditional introduction to negative feedback systems

• Integrator as controller in a negative feedback system
• Intuition and analysis in the time domain
• Pedagogical advantages of the proposed introduction
• Conclusions

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Traditional introduction to negative feedback systems

Vi Vo
+-
Σ A

β
• Algebraic system—cannot explain evolution over time
• Unstable with arbitrarily small loop delay
• Ideal delay Td in the loop ⇒ oscillations with a period 2Td
• Real systems have non-zero delay and don’t respond
instantaneously

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Intuitive understanding of negative feedback systems

## controller: change the output

until error goes to zero
target
(e.g. speed) error output
Σ controller
+-
sensor
(e.g. speedometer)
sensor output
(e.g. speedometer reading)
• Compare the sensed output to the target (desired output)
• Continuously change the output until the output
approaches the target

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Example: Driving a car at a given target speed

## controller: accelerate or brake

until speed error goes to zero

target speed
speed error output
Σ controller
+-
speedometer

speedometer reading
• Compare the sensed speed to the target
• Speedometer reading to desired speed
• Compute (mentally) the difference
• ⇒ Look at the speedometer!
• Keep accelerating (or braking) until error goes to zero
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Example: Driving a car at a given target speed

## controller: accelerate or brake

until speed error goes to zero

target speed
speed error output
Σ controller
+-
speedometer

speedometer reading
• You don’t know how much to press the accelerator or the
brake to obtain the desired speed
• You keep on doing it until the sensed speed is the same as
the target
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Other examples

• Driving a car
• Controlling the volume: Keep turning the volume knob until
the sensed volume (what your hear) matches target
volume (that you find comfortable)

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Nature of the controller

target constant
(e.g. speed) error output
Σ controller
+-
stuck sensor
(e.g. speedometer)
sensor output stuck

large error
large error
output
error

t t

## • Controller integrates the error

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Negative feedback system with an integrator

## integrator: change the output

until error goes to zero
target
(e.g. speed) error output
Σ γ dt
+-
sensor
(e.g. speedometer)
sensor output
(e.g. speedometer reading)

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Negative feedback amplifier

Vi Ve Vo
Σ ωu dt
+-

(k-1)R
Vfb

R
computing
the error
sensing
the output

## • Need the output Vo to be gain k times the input Vi

• Compare Vo /k to Vi and integrate the error
• Steady state when Vo = kVi for constant Vi

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Integrator in the negative feedback amplifier

Vo [V]

4 Ve=1V
Ve Vo = ωu Ve dt 3 ωu = 109 rad/s
ωu dt
2
1 ωu = 2.5x108 rad/s
t [ns]
1 2 3 4

• Proportionality constant ωu
• Slope of the output = ωu Ve

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Integrator: Frequency domain

|ωu/jω|
ωu=109 rad/s
-20dB/decade ωu=2.5x108 rad/s

ωu V (s) ω (log)
Ve(s) ωu Vo(s) = e 107 108 109
s [rad/s]
s <ωu/jω
107 108 109
ω (log)
−π/2 [rad/s]

## • Described by a single parameter ωu

• ωu : “unity gain frequency”
• Higher ωu ⇒ higher gain magnitude for all frequencies

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Integrator: Summary

Vo [V]

4 Ve=1V
Ve Vo = ωu Ve dt 3 ωu = 109 rad/s
ωu dt
2
1 ωu = 2.5x108 rad/s
t [ns]
1 2 3 4

|ωu/jω|
ωu V (s) -20dB/decade
Ve(s) ωu Vo(s) = e
s
s
ω (log)
107 108 109
[rad/s]

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Negative feedback amplifier with constant input

Negative feedback amplifier, k=4, ω =109 rad/s Negative feedback amplifier, k=4, ω =109 rad/s
u u
5 5
Input V
i
4.5 Feedback V 4.5
f
4 Error Ve 4

3.5 3.5

3 3
Volts

Volts
2.5 2.5

2 2

1.5 1.5

1 1
Ideal output 4Vi
0.5 0.5 Actual output Vo
0 0
0 1 2 3 4 5 6 0 1 2 3 4 5 6
time [ns] time [ns]

## • Error reduces as feedback Vf ramps up

• Reduced error slows the rate of output ramp

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Negative feedback amplifier with constant input

## Negative feedback amplifier, k=4, ω =109 rad/s

u
5

4.5

4
Vi Ve Vo
ωu dt
+ Σ
3.5

- (k-1)R 3
Vf

Volts
2.5

2
R
1.5 Input Vi
Ideal output 4Vi
1
Initial condition=0V
0.5 Initial condition=2V
Initial condition=5V
0
0 1 2 3 4 5 6
time [ns]
 
dVo Vo
= ωu Vi − (1)
dt k
 ωu  ωu
Vo (t) = kVi 1 − exp(− t) + Vo (0) exp(− t) (2)
k k
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Negative feedback amplifier—Steady state

Vi Ve=0 Vo
Σ ωu dt
+-
(k-1)R

Vfb = Vi
R

## • Zero state error for a constant input Vi (Vo = kVi )

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Opamp for implementing a negative feedback amplifier

Vi +
Vi Ve Vo + Vo
Σ ωu dt Ve ωu
+- - −

(k-1)R
(k-1)R
Vfb
Vfb

R
computing
the error

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Time domain behavior with constant/step inputs

Vi +
Vi Ve Vo + Vo
Σ ωu dt Ve ωu
+- - −

(k-1)R
(k-1)R
Vfb
Vfb

R
computing
the error

1 dVo Vo
= Vi −
ωu dt k
  ω 
u
Vo (t) = kVp 1 − exp − t
k
• Time constant k /ωu
• Asymptotically reaches Vo = kVi or Vfb = Vi
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Relation to frequency domain analysis

ωu ωu,loop
Loop gain L(s) = =
ks s
Frequency domain:
• Unity loop gain frequency ωu,loop
• Significant negative feedback up to ωu,loop ⇒ nearly ideal
behavior up to ωu,loop (Closed loop Bandwidth)

1
τloop =
ωu,loop
Time domain:
• Unit step response of the loop gain
= t/(1/ωu,loop ) = t/τloop
• Closed loop response time constant = 1/ωu,loop = τloop

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Advantages of this formulation

## • Not instantaneous-unrealistic anyway

• Time evolution naturally built in
• Synthesis from common experience of negative feedback
based adjustment in the time domain-amplifier not
arbitrarily thrown in
• Intuition and key results obtained from time domain
reasoning
• Exponential settling

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Controlled sources using an opamp

## Our opamp compares voltages; Therefore, voltages have to be

compared for all controlled sources; “opamps” that compare
currents can also be used
• VCVS: Vo = kVi ; Compare Vo /k to Vi
• CCVS: Vo = Rf Ii ; Compare Vo − Rf Ii to 0
• VCCS: Io = Gm Vi ; Compare Io /Gm to Vi
• VCVS: Io = kIi ; Compare Io R − kIi R to 0

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Voltage controlled voltage source

Vi +
Vo

(k-1)R

Vfb = Vi
R

• VCVS: Vo = kVi
• Compare Vo /k to Vi and drive the output with the integral
of the error
• For constant Vi , Vo = kVi in steady state
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Current controlled voltage source

0 +
Vo

Ii Rf
Vo-IiRf

• VCVS: Vo = Rf Ii
• Compare Vo − Rf Ii to 0 and drive the output with the
integral of the error
• For constant Ii , Vo = Rf Ii in steady state
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Voltage controlled current source

Vi + Io
Vopa load

+ V
− opa

Io
Io/Gm
R=1/Gm

• VCCS: Io = Gm Vi
• Compare Io /Gm to Vi and drive the output with the integral
of the error
• For constant Vi , Io = Gm Vi in steady state
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Current controlled current source

0 + Io
Vopa load

+ V
− opa
Ii (k-1)R Io
IoR-kIiR
Ii R

• CCCS: Io = kIi
• Compare (Io − kIi )R to 0 and drive the output with the
integral of the error
• For constant Ii , Io = kIi in steady state
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Negative feedback amplifier with delay

## controller: change the output controller: change the output

until error goes to zero until error goes to zero
target error output target error output
Σ controller Σ controller
+- +-
sensor sensor
(delay Td) delay Td
sensed output sensed output

## • Delay is inherent in negative feedback loops. e.g.

Speedometer’s delay in “computing” speed
• Excess delays can occur in any part of the
system-modeled in the feedback path

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Effect of delay on negative feedback
3
target
2.5 output
feedback
2 error
1.5

0.5

−0.5

−1

−1.5

−2
0 1 2 3 4 5

## • Don’t know that we have already reached the target

• Overshoot the target and then start falling
• The process repeats on the other side—ringing or
oscillation
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Effect of delay on negative feedback
2.5
target
output
2
feedback
error
1.5

0.5

−0.5

−1

−1.5
0 2 4 6 8 10

## • Don’t know that we have already reached the target

• Overshoot the target and then start falling
• The process repeats on the other side—ringing or
oscillation
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Negative feedback amplifier with delay-Intuition

## • A small delay doesn’t matter—How small?

• If there is a long delay, integrate more slowly to avoid
overshoot—How slowly?

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Negative feedback amplifier with delay in the loop

Vi Ve Vo
Σ ωu dt
+-

(k-1)R
Vfb
delay Td

R
• Td /τloop ≤ 1/e(= 0.367): No overshoot
• 1/e < Td /τloop < π/2: Overshoot + ringing
• π/2 < Td /τloop : Unstable

## In practice we need a “well behaved” response (limited

overshoot)
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Negative feedback amplifier with delay in the loop
2

1.8

1.6

1.4
Vo [normalized to kVi]

1.2

0.8
Td/(k/ωu) = 0
0.6
T /(k/ω ) = 1/e
d u
0.4 T /(k/ω ) = 0.5
d u
Td/(k/ωu) = 1.0
0.2
T /(k/ω ) = 1.5
d u
0
0 2 4 6 8 10
time [normalized to k/ω ]
u
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Negative feedback amplifier with delay in the loop

## Td /τloop ≤ 1/e 0.445 0.465 0.5 0.585 0.695

(0.367)

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Eliminating instability in presence of delay

## • Stability governed by the ratio of Td to τloop

• Reduce Td : Faster circuit/technology
• Increase τloop ⇒ Decrease ωu,loop : Slower integration

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Delays in circuit implementation—parasitic poles and zeros

QM
ωu,loop (1 + s/zk )
Loop gain L(s) = · QNk =1
s
| {z } | k =2 (1{z+ s/pk )}
Ideal Parasitic

slope=ωu,loop slope=ωu,loop
Td Td

t t
Unit step response of L(s) is a ramp of slope ωu,loop (same as
P PM
ideal) with a delay Td = N k =1 1/pk − k =1 1/zk

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Closed loop response with equivalent delay

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Advantages of this formulation

## • Not instantaneous-unrealistic anyway

• Time evolution naturally built in
• Synthesis from common experience of negative feedback
based adjustment in the time domain-amplifier not
arbitrarily thrown in
• Intuition and key results obtained from time domain
reasoning
• Exponential settling
• Possibility of ringing, overshoot, and instability

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Advantages of this formulation

• Traditional viewpoint
• Memoryless amplifier (loop gain) in the ideal case
• Frequency dependence as non-ideal feature
• Proposed viewpoint
• Integrator in the ideal case (∞ dc gain)
• Finite dc gain due to non-ideal implementation
• As easy as the “gain model” to convert to ideal opamps

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Opamp models

|Vout/Vd| (dB)
finite dc gain model: A0
first order model: A0/(1+s/ωd)
integrator model: ωu/s
full model: A0/(1+s/ωd)(1+s/p2)(1+s/p3) ...

A0

p2 p3
ωd ωu ω

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Advantages of this formulation

## • ωu,loop more fundamental characteristic of the negative

feedback loop than dc loop gain
• Increasing ωu,loop requires higher power
• Increasing dc loop gain indirectly influences power

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Advantages of this formulation

## • Loop gain of all feedback systems has integrator-like

behavior over some frequency range
• Nyquist plot should enter the unity circle near the negative
imaginary axis
• Bode plot should have −20 dB/decade slope near the unity
gain frequency

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Advantages of this formulation

## • Clear why fastest negative feedback systems are slower

than fastest open loop systems
• Clear why max. speed of negative feedback systems
increases with technology

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Advantages of this formulation

## • Leads directly to opamp and phase locked loop topologies

45 / 135
References

Adel S. Sedra and Kenneth C. Smith, Microelectronic Circuits, 6th ed., Oxford University Press 2009.

Paul R. Gray, Paul J. Hurst, Stephen H. Lewis, Robert G. Meyer, Analysis and Design of Analog Integrated
Circuits, 5th ed., Wiley 2009.

Nagendra Krishnapura, “Introducing Negative Feedback with an Integrator as the Central Element,” Proc.
2012 IEEE ISCAS, May 2012.

Nagendra Krishnapura, “Synthesis Based Introduction to Opamps and Phase Locked Loops,” Proc. 2012
IEEE ISCAS, May 2012.

Karl J. Astrom and Richard M. Murray, “Feedback Systems: An Introduction for Scientists and Engineers,”
Available:
http://www.cds.caltech.edu/∼murray/amwiki/index.php/Main_Page

## Barrie Gilbert, “Opamp myths,” Available: http://pe2bz.philpem.me.uk/

Parts-Active/IC-Analog/OpAmps/OpAmpMyths/c007-OpAmpMyths.htm

Hal Smith, An Introduction to Delay Differential Equations with Applications to the Life Sciences, 1st ed.,
Springer 2010.

## Nagendra Krishnapura, “EE5390: Analog Integrated Circuit Design,” Available:

http://www.ee.iitm.ac.in/∼nagendra/videolectures

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Synthesis of opamp topologies

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Opamp (integrator) realization
+ + Igm
Vout Vout,buf
Ve − 1
-
Gm1 C1

Z
Gm1
Vo = Ve dt (3)
C1
Z
= ωu Ve dt (4)
(5)

• Gm − C integrator
• ωu = Gm1 /C1
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Opamp (integrator) realization—Finite dc gain

+ + Igm
Vout Vout,buf
Ve − 1
-
Gm1 Ro1 C1

## • Finite Ro1 ⇒ Finite dc gain ⇒ Steady state error

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Steady state error due to finite dc gain
Step response
1

0.9

0.8

0.7

0.6

0.5
V

0.4

0.3

0.2

0.1 Ideal
Ao=10
0
0 2 4 6 8 10
t/τ
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Opamp (integrator) realization

+ + Igm
Vout Vout,buf
Ve − 1
-
Gm1 Ro1 C1

## • Simplest realization: Single stage opamp

• Enhanced Ro1 : Cascode opamp (But, same ωu )

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Transimpedance amplifier for better I-V conversion
part of IGm(=Vo/Rout)
IGm Ro1 Zc

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Transimpedance amplifier for better I-V conversion
smaller part of
IGm(=Vx/Rout) Vo-IGmZc Zc
part of IGm(=Vo/Rout)
IGm Ro1 Zc IGm Ro1
+ −
Vo
Vx ωu
- +

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Improved I-V conversion—Two stage opamp

+ + Igm
Ve −
-
Gm1 Ro1 C1

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Improved I-V conversion—Two stage opamp
C1
Ve=Vo-IGmZc
integrator
+ + Igm + Igm
− Vo
Ve − Ve −ωu2 dt
- - +

## Gm1 Ro1 C1 Gm1 Ro1

monitors Ve and
continuously adjusts
Vo until Ve→0

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Improved I-V conversion—Two stage opamp
C1
Ve=Vo-IGmZc
integrator
+ + Igm + Igm
− Vo
Ve − Ve −ωu2 dt
- - +

## Gm1 Ro1 C1 Gm1 Ro1

monitors Ve and
C1 continuously adjusts
Vo until Ve→0

+ Igm

Ve −
- +
+
Gm1 Ro1
Gm2 Ro2 C2

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Negative feedback amplifier: Frequency domain

ωu/s |A(jω)|
loop gain
Vi Ve Vo
ωu dt
+ Σ
- (k-1)R ωu ω (log)
ωu/k
Vf |Vo/Vi|
ideal over this band
R
k
ω (log)
ωu/k

## • Desired behavior in the region where loop gain is high

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Negative feedback amplifier: Frequency domain
9
Negative feedback amplifier, k=4, ω =109 rad/s Negative feedback amplifier, k=4, ω =10 rad/s
u
u
1
1 10

0.8

Magnitude
0
0.6 10

0.4
−1
0.2 10
ω [Grad/s]

−2 −1 0 1
10 10 10 10
0

## −0.2 Pole at −250Mrad/s 0

−0.4

Phase
−0.6 −50

−0.8

−1 −100 −2 −1 0 1
−1 −0.5 0 0.5 1 10 10 10 10
σ [Grad/s] ω [Grad/s]
 
ωu Vo
Vo (s) = Vi − (6)
s k
Vo (s) k
= (7)
Vi (s) 1 + ωus/k

## • First order response; DC gain = k , pole at ωu /k

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Negative feedback amplifier: Sinusoidal input

Vo (jω) k
= jω
(8)
Vi (jω) 1+ ωu /k

Vo (jω) k Vo (jω) ω
V (jω) = r ; ∠ = − tan−1 (9)

i
 2 Vi (jω) ωu /k
1 + ωuω/k

## • dc gain: k (= desired value)

• 3 dB bandwidth: ωu /k

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Negative feedback amplifier: Low frequency input

9
Vo (jω) k
V (jω) = (10)
Negative feedback amplifier, k=4, ω =10 rad/s
4
u r  2
input i ω
3 ideal output
actual output 1+ ωu /k
2

1 Vo (jω) ω
∠ = − tan−1 (11)
Vi (jω) ωu /k
Volts

−1
(12)
Input at 0.1ωu/k
−2

−3

−4
0 50 100 150 200 250
time [ns] • Nearly ideal behavior
• Gain k , delay k /ωu

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Negative feedback amplifier: High frequency input

9
Vo (jω) k
V (jω) = (13)
Negative feedback amplifier, k=4, ωu=10 rad/s
4
r  2
input i ω
3 ideal output
actual output 1+ ωu /k
2

1 Vo (jω) ω
∠ = − tan−1 (14)
Vi (jω) ωu /k
Volts

−1
(15)
Input at 10ωu/k
−2

−3

−4
0 0.5 1 1.5 2 2.5
time [ns] • Attenuated output
• Nearly 90◦ phase lag

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Intuition about two stage opamp constraints

Gm1 G
< m2
C C2

## • Bias current determined by Gm

• Higher bias current in the second stage

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Further improved I-V conversion—Three stage opamp
C1
Ve=Vo-IGmZc
integrator
+ + Igm + Igm
− Vo
Ve − Ve −ωu2 dt
- - +

## Gm1 Ro1 C1 Gm1 Ro1

monitors Ve and
continuously adjusts
Vo until Ve→0

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Further improved I-V conversion—Three stage opamp
C1
Ve=Vo-IGmZc
integrator
+ + Igm + Igm
− Vo
Ve − Ve −ωu2 dt
- - +

## Gm1 Ro1 C1 Gm1 Ro1 monitors Ve and

continuously adjusts
C1 Vo until Ve→0

C2

+ Igm
− +
Ve Vout
- + − −

Gm1 Ro1 +
Gm2 Ro2
Gm3 Ro3 C3
two stage opamp
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Further improved I-V conversion—Three stage opamp

C1

C2

+ Igm
− +
Ve Vout
- + − −

Gm1 Ro1 +
Gm2 Ro2
Gm3 Ro3 C3
two stage opamp

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Intuition about three stage opamp constraints

Gm1 G G
< m2 < m3
C C2 C3

## • Bias current determined by Gm

• Higher bias currents in the third stage, second stage

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Follow up in the frequency domain

## Analyze in frequency domain and relate to time domain results

and intuition
• Two stage opamp
• DC gain
• Pole locations, pole splitting (with load)
• Stability constraints
• RHP zero and its cancellation
• Three stage opamp
• DC gain
• Pole locations
• Stability constraints
• Zero pair and their optimization

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Opamp (integrator) realization—Finite dc gain

Vi + Igm
+
Ve - −

Gm1 Ro1 C1

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Opamp realization—Supply extra current from another
source

monitor Ve and
continuously adjust
Ioff until Ve=0
Ioff
Vi + Igm Vi + Igm
+
Ve - − +
Ve - −

## Gm1 Ro1 C1 Gm1 Ro1 C1

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Opamp realization—Additional negative feedback control

integrator
+
Kpd,I dt

Gm2a Ioff
+ Igm
Vi Vo
Ve +
- −

Gm1 Ro1 C1

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Opamp realization—Additional negative feedback control

integrator
+
+ +
Kpd,I dt −
− −
Gm2 Ro2 C2
Gm2a Ioff Gm2a Ioff
+ Igm opamp + Igm
Vi Vo Vi Vo
Ve +
- − Ve +
- −

## Gm1 Ro1 C1 Gm1 Ro1 C1

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Two stage feedforward opamp

+
+

Gm2 Ro2 C2 Gm2a Ioff
opamp + Igm
Vi
Ve +
- −

Gm1 Ro1 C1

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Intuition about feedforward opamp constraints

## • Additional path slower than main path

• Doesn’t contribute to extra power consumption

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Feedforward opamp settling

## • Additional path too fast

• Overshoot, instability
• Additional path too slow
• Initial settling to low accuracy
• Creeps up to high accuracy
• “Pole-zero” doublet problem
• Not suitable for step-like outputs
• Lower power consumption for smoother outputs

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Feedforward opamp settling
Step response
1

0.9

0.8 1

0.7 0.99

0.6 0.98

0.5
V

0.97

0.4 0.96
45 46 47 48 49 50
0.3

## 0.2 Single stage opamp, A =100

o
Single stage opamp, A =10
0.1 o
Feedforward opamp, A =100, 10
o
0
0 10 20 30 40 50
t/τ
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Three stage feedforward opamp
+
+

Gm3 Ro3 C3 Gm3a
+
+

Gm2 Ro2 C2
two stage Gm2a Ioff
feedforward opamp + Igm
Vi Vo
Ve +
- −

Gm1 Ro1 C1

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Follow up in the frequency domain

## Analyze in frequency domain and relate to time domain results

and intuition
• Two stage feedforward opamp
• Closed loop response
• Zero location
• Pole-zero doublet
• Three stage opamp
• Closed loop response
• Location of zeros
• Poles and zeros

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Advantages of this formulation

## • Easy derivation of actual implementation of opamps

• Mysterious looking steps leading to stabilization are
removed
• Intuitive understanding of constraints in Miller and
feedforward opamps

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Synthesis of phase locked loop topologies

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Outline

## • Phase locked loop (PLL) requirements

• PLL frequency multiplier
• Derivation
• Phase model
• Type-I PLL
• Practical phase detectors
• Type-I PLL limitations
• Type-II PLL
• Feedback systems and stability
• Type-II PLL
• LC oscillator
• Programmable frequency divider

80 / 135
Phase locked loops

## • Frequency synthesizers in radios for local oscillators

• Frequency multiplication for reference clock generation
• Phase alignment

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Local oscillator requirements
10kHz interchannel spacing
bandwidth
channel
Broadcast AM band spacing 0.15MHz Broadcast FM band
0.2MHz

1610kHz
fc
530kHz

88.2MHz
88MHz

108MHz
5kHz

channel channel
spacing spacing
0.2MHz 0.2MHz
GSM uplink band GSM downlink band
890.2MHz

960MHz
890MHz

935.2MHz
915MHz

935MHz
• Tuned to the desired channel frequency plus an
intermediate frequency (IF)
• Generate equally spaced frequencies from a reference
frequency 82 / 135
Frequency divider

Vref

R(N-1)
fref fref/N
Vref/N N
R frequency
divider

## • Digital frequency divider can generate multiple frequencies

• Frequencies not equally spaced
• Reference frequency higher than output frequencies

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Frequency multiplication analogous to voltage amplification

frequency
error
Vi Ve Vo fref fe fout
ωu dt ωu dt
+ Σ input + -
Σ
output
- (k-1)R
Vf frequency frequency
1/N
R fout/N

84 / 135
Frequency multiplication

frequency difference
input zero, at steady state
signal fout = ffree+KvcoVctl
at fref fref Vctl
frequency
measure + Σ γ dt
output
-
signal
VCO at fout
fout/N
frequency
measure N

frequency
divider

85 / 135
Phase and frequency

• Sinusoid: cos(θ(t))
• Phase: θ(t)
• Instantaneous frequency: fi = 1 dθ(t)
2π dt
• Typically expressed as fi = fo + fe (t)
• fo : average frequency
• fe : instantaneous frequency error
R
• Phase θ(t) = 2πfo t + Φo + 2π fe (t)dt
• Phase θ(t) = 2πfo t + Φo + φ(t)
• Φo : phase offset-ideal ramp versus time
• φ(t): instantaneous phase

86 / 135
Phase error
70
ideal phase
error
60 phase with error

50

40

30

20

10

−10
0 2 4 6 8 10
87 / 135
Integrate frequency difference ⇒ Phase difference

input
signal fout = ffree+KvcoVctl
at fref measure Vctl
frequency γ dt + Σ
- output
signal
measure phase VCO at fout

measure
γ dt frequency N

## measure phase frequency

measure phase difference divider

88 / 135
Type-I phase locked loop

fout = ffree+KvcoVctl
input signal at fref
phase Vctl
detector output signal
at fout
VCO

frequency
divider
• Phase detector and VCO in a loop

89 / 135
Voltage controlled oscillator
slope = Kvco
fout
Vctl fout=KvcoVctl+fo fo

Vctl

2πfot

Vctl + θvco
+
2πKvco dt Σ

## • fvco = fo + Kvco Vctl

• fo : Free running frequency
R
• θvco = 2πfo t + 2πKvco Vctl dt
• Kvco : VCO gain in Hz/V

90 / 135
Phase detector

φ1 Kpd(φ1-φ2)
phase
φ2 detector
• Kpd : Phase detector gain in V/radian
• Ideal phase detector: assumed to have an output
Vpd = Kpd (φ1 − φ2 )

91 / 135
Type-I phase locked loop
In steady state, output signal at fout
Vctl = (fout-ffree)/Kvco (fout=Nfref at
input signal steady state)
at fref
Kpd∆Φ Vctl
Kpd
∆Φ = Φref-Φout/N
phase VCO
detector
In steady state,
∆Φ = (fout-ffree)/KvcoKpd N

frequency
divider

## • Phase offset ∆Φ = (fout − ffree )/Kvco Kpd between input and

feedback signals
• |∆Φ| limited to ±nπ due to periodic nature of phase
• Limited lock range |fout − ffree |

92 / 135
Phase locked loop model
2πfot

## 2πfreft+Φref Vctl + 2πfout t+Φout

+
+ Σ Kpd 2πKvco dt Σ
-

2πfout/N t+Φvco/N
1/N

## Vctl = 2π(fref-fout/N)t + Φref - Φout/N

At steady state, fref=fout/N; Vctl = Φref - Φout/N

## • Modelled in terms of phases of signals

• At steady state (lock), Vctl is a constant ⇒ fref = fout /N
• The loop locks with
Vctl = Kpd (Φref − Φout /N) = (Nfref − fo )/Kvco —This is the
“operating point” of the circuit
93 / 135
Phase locked loop model

2πfot

## 2πfreft+Φref+φref Vctl+vctl + 2πfout t+Φout+φout

+
+ Σ Kpd 2πKvco dt Σ
-

1/N
2πfout/N t+Φout/N+φout/N

## • An increment φref in the input phase causes increments

φout , vctl

94 / 135
Phase locked loop model—incremental picture

## φref vctl φout

+ Σ Kpd 2πKvco dt
-

φout/N
1/N

## • An increment φref in the input phase causes increments

φout , vctl
• Type-I loop—One integrator in the loop
• “Phase model” of the PLL

95 / 135
Phase locked loop model—frequency domain
φref(s) vctl(s) 2πKvco φout(s)
+ Σ Kpd
s
-

φout(s)/N
1/N

## • Loop gain L(s) = 2πKpd Kvco /Ns

• Transfer function
φout (s)/φref (s) = N/(1 + Ns/(2πKpd Kvco ))
• Type-I loop—One integrator in the loop
• Closed loop bandwidth (= unity loop gain frequency)
= 2πKpd Kvco /N rad/s
96 / 135
Type-I PLL—limitations

## • Phase error when locked (fout = Nfref ):

• Φref − Φout /N = (Nfref − fo )/Kvco Kpd
• dc value of Kpd matters; We have a constant Kpd
• |Φref − Φout /N| < 2π ⇒ |fout − fo | < 2πKpd Kvco
• Lock range limited by periodicity of phase detector
• Period of all phase detectors not necessarily ±2π
• Commonly used three state phase detector periodic with
±2π
• Kpd Kvco large for wide lock range

97 / 135
Phase detector

## • Frequency divider output has a varying duty cycle

• Phase detector should sensitive to duty cycle
• XOR gate etc. are not preferable
• Phase detector should be sensitive only to rising edges (or
only to falling edges) of inputs

98 / 135
Tri-state phase detector

1 QA
A A D Q
A
ref RST
B -1 0 +1 A
B RST
div
QB
B B 1
D Q

output=QA-QB

## • Output +1, −1, 0

• +1 if reference leads divider output
• −1 if reference lags divider output
• 0 if reference coincides with divider output

99 / 135
Tri-state phase detector-waveforms

Tref Tref

+1 +1
A -1
A -1

+1 +1
B B
-1 -1

+1 +1
QA QA
+1 +1
QB QB

Φref-Φdiv Φdiv-Φref

A leading B A lagging B

## • Flip flops assumed to be reset instantaneously

100 / 135
Tri-state phase detector-frequency difference between inputs

1 QA
A A D Q
A
ref RST
B -1 0 +1 A
B RST
div
QB
B B 1
D Q

output=QA-QB

## • fA > fB : Eventually get two consecutive edges of A

• Circulates between 0 and +1 states: Average output > 0
• Similarly, average output > 0 for fA < fB
This detector is a phase/frequency detector (PFD)

101 / 135
Tri-state phase detector output
Tref
+1
reference
-1
reference
Tri-state pdout
+1 phase
divider o/p
divider o/p detector
-1

+1
pdout Average value = ∆Φ/π
-1 Tref Output periodic at fref

∆Φ = Φref-Φdiv

∞  
∆Φ X n∆Φ
Vout (f ) = sinc δ(f − nfref )
2π n=−∞ 2π
∞  
∆Φ ∆Φ X n∆Φ
Vout (t) = + sinc cos(2πnfref t)
2π π 2π
n=1
102 / 135
Tri-state phase detector

## • Output average value = ∆Φ/2π

• Kpd = 1/2π
• Phase detector offset = 0
• Loop locks with ∆Φ = Φref − Φout /N = 0 for Nfref = fo
• Input range = ±2π
• PLL lock range = fo − 2πKpd Kvco < fout < fo + 2πKpd Kvco
• Output contains fref and its harmonics
P
• Output = 1/2π (∆Φ + n an cos(2πnfref t))
• Periodic signal in addition to Kpd ∆Φ

## All real phase detectors have a periodic “error” in addition to the

“dc” term proportional to phase error

103 / 135
Phase detector-Output spectrum
∆Φ=π/2
0.6

0.4

0.2

−0.2
0 2 4 6 8 10

∆Φ=π/8
0.5

−0.5
0 2 4 6 8 10
f/f
ref
104 / 135
PLL with tri-state phase detector—periodic error
Σn ancos(2πnfreft) ("error")

## φref + vctl φout

+ Σ + Σ Kpd 2πKvco dt
-

φvco/N
1/N

## • Error e(t) added to the input of the phase detector

• Disturbances in the VCO output phase φout (t) even with a
perfect reference (φref (t) = 0)
• VCO output: cos(2πNfref t + NΦref + φout (t))
• VCO output not periodic at Nfref
105 / 135
Phase error
70
ideal phase
error
60 phase with error

50

40

30

20

10

−10
0 2 4 6 8 10
106 / 135
PLL with tri-state phase detector—frequency domain
E(s) E(j2πf) = Σn an/2 δ(f±nfref)

+ Σ + Σ Kpd
s
-

φvco(s)/N
1/N

## φref(s) = 0 for a perfectly periodic reference

• Transfer function from the error to the output
φout (s)/E(s) = φout (s)/φref (s) = N/(1 + Ns/(2πKpd Kvco ))
P
• E(j2πf ) = n (an /2)δ(f ± nfref )

107 / 135
Type-I PLL

## φout (s) φout (s)

= (16)
E(s) φref (s)
2πKpd Kvco /Ns
= N (17)
1 + 2πKpd Kvco /Ns
1
= N (18)
1 + sN/2πKpd Kvco
(19)
Loop gain
2πKpd Kvco
L(s) = (20)
Ns
Closed loop bandwidth (Hz)
Kpd Kvco
f−3dB = (21)
N
108 / 135
Type-I PLL

dB

2πKpdKvco/N
ω
L/(1+L)
|φout/φref|
dB
20log(N)
ω
2πKpdKvco/N

(loop bandwidth)

109 / 135
Feedback system
In our system,

## φout (s) 2πKpd Kvco /Ns

= N (22)
E(s) 1 + 2πKpd Kvco /Ns

## In general, in a feedback system with a loop gain L(s)

L(s)
Hclosedloop (s) = Hideal (s) (23)
1 + L(s)
(24)

Where Hideal (s) is the ideal closed loop gain (with L = ∞). This
can be approximated as

## Hclosedloop (s) = Hideal (s)L(s) |L| ≪ 1 (25)

= Hideal (s) |L| ≫ 1 (26)

110 / 135
PLL with tri-state phase detector—Output signal
Considering only the term at fref , and b1 ≪ 1

## Vout (t) = cos(2πNfref t + b1 sin(2πfref t)) (27)

= cos(2πNfref t) cos(b1 sin(2πfref t)) (28)
− sin(2πNfref t) sin(b1 sin(2πfref t)) (29)
≈ cos(2πNfref t) − b1 sin(2πfref t) sin(2πNfref t)(30)
= cos(2πNfref t) (31)
−b1 /2 cos(2π(N − 1)fref t) (32)
−b1 /2 cos(2π(N + 1)fref t) (33)

## • Spurious tones in the output at a spacing of ±fref from the

desired frequency—“Reference feedthrough”
• In general, spurious tones will be present at ±nfref from the
desired PLL output
111 / 135
Reference feedthrough

b1 = a1 |H(j2πfref )| (34)

Kpd Kvco /jNfref
= a1 N
(35)
1 + Kpd Kvco /jNfref

Kpd Kvco
≈ a1 N
(36)
jNf ref

Nf−3dB ∆Φ
= 2∆Φ sinc (37)
fref 2π

## • Maximum value of b1 = 4Kpd Kvco when ∆Φ = π

112 / 135
Reference feedthrough—example

## • To generate 1 GHz from 1 MHz reference

• b1 /2 = 10−2 (spurious tones at (N ± 1)fref 40 dB below the
fundamental output at Nfref )
• N = 103
• ∆φ = π (locked with a phase shift of π)
• f−3dB /fref = 5 × 10−6 ⇒ f−3dB = 5 Hz
• Lock range = 2πNf−3dB ≈ 10π kHz
• Lock range is too small; Can’t switch to the next channel
which is 1 MHz away!
• May not be able to lock for any value of N, unless the free
running frequency happens to be Nfref for some N

113 / 135
Type-I phase locked loop

## In steady state, output signal at fout

Vctl = (fout-ffree)/Kvco (fout=Nfref at
input signal steady state)
at fref
Kpd∆Φ Vctl
Kpd
∆Φ = Φref-Φout/N
phase VCO
detector
In steady state,
∆Φ = (fout-ffree)/KvcoKpd N

frequency
divider

## ∆Φ = 0 if fout happens to be equal to fref . Zero spurs!

114 / 135
Changing the free running frequency of a VCO

Voff
Vctl (ffree+KvcoVoff)+KvcoVctl Vctl ffree’+KvcoVctl
Σ

VCO VCO
ffree’ = ffree+KvcoVoff

## • Add a bias to the input to change the free running

frequency

115 / 135
Slowly change the bias until ∆φ = 0
monitor ∆Φ and
continuously adjust
Voff until ∆Φ=0
+ output signal at fout

(fout=Nfref at
input signal steady state)
at fref Voff
Kpd∆Φ
Kpd Σ
∆Φ = Φref-Φout/N
phase ffree’ VCO
detector
N

frequency
divider

## • Slowly change the bias Voff until ∆φ = 0

116 / 135
Slowly change the bias until ∆φ = 0
integral
phase
detector In steady state,
Kpd,I ∆Φ dt Voff = (fout-ffree)/KvcoKpd
∆Φ Kpd,I dt
output signal at fout
(fout=Nfref at
input signal steady state)
at fref Voff
Kpd∆Φ
Kpd Σ
∆Φ = Φref-Φout/N
phase ffree’ VCO
detector
In steady state,
∆Φ = 0 N

frequency
divider

## • Measure ∆φ and integrate it to control Voff

117 / 135
Type-II phase locked loop
phase detector + loop filter
integral
phase
detector
Kpd,I ∆Φ dt
∆Φ Kpd,I dt
output signal at fout
proportional (fout=Nfref at
input signal phase steady state)
at fref detector
Kpd∆Φ
Kpd Σ
∆Φ = Φref-Φout/N
VCO

In steady state,
∆Φ = 0 N

## • Proportional + integral loop filter

118 / 135
Type-II PLL with a tri-state phase detector

## • Lock range is not limited by the phase detector

• Loop locks with zero phase difference between reference
and feedback signals
• tri-state phase detector output is zero for zero input phase
difference ⇒ No reference feedthrough!
• Reference feedthrough does exist in reality due to
mismatches

119 / 135
Type-II PLL—phase model

zero at
steady state 2πfot
Kpd,I dt
2πfreft+Φref + Vctl + 2πfout t+Φout
+
+ Σ Σ 2πKvco dt Σ
- +
Kpd

2πfout/N t+Φout/N
1/N

## dVctl/dt α 2π(fref-fout/N)t + Φref - Φout/N

At steady state, fref=fout/N; Φref - Φout/N = 0;

## • Proportional + integral loop filter

120 / 135
Type-II PLL—incremental model

zero at
steady state
Kpd,I dt
2πfreft+Φref + Vctl 2πfout t+Φout
+ Σ Σ 2πKvco dt
- +
Kpd

2πfout/N t+Φout/N
1/N

## dVctl/dt α 2π(fref-fout/N)t + Φref - Φout/N

At steady state, fref=fout/N; Φref - Φout/N = 0;

## • Proportional + integral loop filter

121 / 135
Type-II PLL—incremental model

Kpd,I
s
φref(s) + vctl(s) 2πKvco φout(s)
+ Σ Σ
s
- +
Kpd

φout(s)/N
1/N

## • Proportional + integral loop filter

122 / 135
Type-II PLL—Frequency domain

p1 > 2πKpdKvco/N
Kpd,I more poles can be used
s
φref(s) + vctl(s) 1 Vctl 2πKvco φout(s)
+ Σ Σ
1+s/p1 s
- +
Kpd

φout(s)/N
1/N

123 / 135
Type-II PLL—Implementation
Tref
reference
iout reference
iout
+1 tri-state tri-state
phase phase
reference
-1 divider o/p
detector + divider o/p
detector
+
R1 proportional R1
∆Φ = Φref-Φdiv proportional
output
+1 + integral
divider o/p -
output
-1 C1
reference
iout
tri-state
+Icp phase
pdout -
divider o/p
detector +
-Icp C1 integral
output
proportional +IcpR
output
-
-IcpR

integral
slope=Icp/C
output

## • Phase detector with a current output (±Icp )

• Integral term Kpd,I /s: Current flowing into a capacitor C1
• Proportional term Kpd : Current flowing into a resistor R1
• Series RC to obtain the sum
• Kpd = Icp R1 /2π; Kpd,I = Icp C1 /2π

124 / 135
Tri-state phase detector with charge pump
Vdd

Icp

1 QA (UP)
D Q
A
ref RST iout

+
B RST R1
div proportional
QB (DN) + integral
D Q output
1
C1
Icp -

## • QA and QB drive a charge pump

• Charge driven into the loop filter Icp Tref ∆Φ/2π

125 / 135
Noise sources in a PLL
Kpd,I vnc φvco
s
φref + 2πKvco φout
+ Σ Σ Σ
s
Σ
- +
Kpd

φout/N
1/N

## • Noise can be added as φref (reference phase noise,

charge-pump noise, divider output phase noise) or
vnc (loop filter noise) or φvco (VCO phase noise)
• Need to compute transfer functions from each of these
noise sources to φout
126 / 135
Type-II PLL: transfer functions

 
ωu,loop z1 s
L(s) = 1+ (38)
s s z1
2πKpd Kvco Icp RKvco
ωu,loop = = (39)
N N
Kpd,I 1
z1 = = (40)
Kpd RC
φout (s) 1 + s/z1
= N (41)
φref (s) 1 + s/z1 + s2 /z1 ωu,loop
φout (s) N s/z1
= (42)
Vnc (s) Kpd 1 + s/z1 + s2 /z1 ωu,loop
φout (s) s2 /z1 ωu,loop
= (43)
φvco (s) 1 + s/z1 + s2 /z1 ωu,loop

127 / 135
Type-II PLL: transfer functions

L(s) 1 + s/z1
= (44)
1 + L(s) 1 + s/z1 + s2 /z1 ωu,loop

## • Two poles and a zero

• Zero z1 = Kpd,I /Kpd
p
• Natural frequency ωn = 2πKpd,I Kvco /N
p p
• Quality factor Q = z1 /ωu,loop = NKpd,I /2πKvco /Kpd
p
• Damping factor ζ = 1/2Q = 1/2 ωu,loop /z1
• For well separated (real) poles (z1 ≪ ωu,loop ),
p1 ≈ z1 + z12 /ωu,loop ≈ z1 , p2 ≈ ωu,loop − z1 ,
• Pole zero doublet {p1 , z1 }; p1 at a slightly higher frequency
than z1
128 / 135
Type-II PLL: transfer functions
5

−5
/φ | [dB]

2
ref

1
−10
out
1/N|φ

−15 −1 −3 −2 −1 0
10 10 10 10

−20 ζ=4.08
ζ=0.3162
ζ=1
−25 −3 −2 −1 0 1
10 10 10 10 10
ω/ω
u,loop

## φout (s) 1 + s/z1

= N (45)
φref (s) 1 + s/z1 + s2 /z1 ωu,loop

## • Peaking in |φout /φref | because of the zero

• Damping factor ζ ≫ 1 to avoid peaking ⇒ slow settling
129 / 135
Type-II PLL: transfer functions
PLL transfer functions
30

20

10
Magnitude response [dB]

−10

−20

−30

−40

−50 φout/φref
φ /v *1V
out nc
−60
φout/φvco
−70 −2 −1 0 1 2
10 10 10 10 10
f/f
u,loop

(Example parameters:
N = 10, z1 = 0.1ωu,loop , N/Kpd = 2πKvco /ωu,loop = 25 V−1 )
• |φout /φref |: Lowpass with a dc gain N
• |φout /vnc |: Bandpass with peak gain N/Kpd = 25 V−1
• |φout /φvco |: Highpass with a high frequency gain of 1
130 / 135
Type-II PLL phase noise example
PLL phase noise components
−20

−40

−60

−80
dBc/Hz

−100

−120

−140 reference
ref. contribution to PLL
−160 VCO
VCO contribution to PLL
Total
−180 −2 −1 0 1 2
10 10 10 10 10
f/f
u,loop

(Example parameters:
N = 10, z1 = 0.1ωu,loop , N/Kpd = 2πKvco /ωu,loop = 25 V−1 )
• Reference contribution dominant below 0.1ωu,loop
• VCO contribution dominant above 0.1ωu,loop
• VCO contribution reduced by the loop upto ωu,loop
• Charge pump and loop filter noise ignored in the above
131 / 135
Intuition about the Phase locked loop

## • Reason for using a phase detector for frequency synthesis

• Reason for an additional integrator in the loop filter
• Integral path for adjusting Voff slower than the main
path (type-I)
• PLL bandwidth (unity loop gain frequency) is the same as in
the type-I loop
• Presence of a zero before the PLL bandwidth (unity loop
gain frequency)
• Integral path influences the phase transfer functions only
well below the PLL bandwidth

132 / 135
Analysis of type-II phase locked loop

## • Pole zero locations

• Phase (jitter) transfer functions
• Higher order loop filter for higher spur suppression

133 / 135
Conclusions

## • Negative feedback: Continuous adjustment to reduce error

• Integrator is the key element of the negative feedback loop
• Implementing a voltage integrator and seeking to improve
its performance leads to commonly used opamp topologies
• Implementing a negative feedback frequency multiplier and
seeking to improve its performance leads to type-I and II
phase locked loops
• Valuable intuition gained before embarking on analysis

134 / 135
References

Paul R. Gray, Paul J. Hurst, Stephen H. Lewis, Robert G. Meyer, Analysis and Design of Analog Integrated
Circuits, 5th ed., Wiley 2009.

## R. D. Middlebrook, “Methods of design-oriented analysis: Low-entropy expressions,” New Approaches to

Undergraduate Education IV, Santa Barbara, 26-31 July 1992.

Nagendra Krishnapura, “Introducing negative feedback with an integrator as the central element,” Proc. 2012
IEEE ISCAS, May 2012.

## Shanthi Pavan, “EC201: Analog Circuits,” Available:

http://www.ee.iitm.ac.in/∼nagendra/videolectures

## Floyd M. Gardner, Phaselock Techniques, 3rd ed., Wiley-Interscience 2005.

Roland Best, Phase Locked Loops: Design, Simulation and Applications, 5th ed., McGraw-Hill 2007.

Stanley Goldman, Phase Locked Loop Engineering Handbook for Integrated Circuits, Artech House 2007.

Behzad Razavi, Design of Analog CMOS Integrated Circuits, 1st edition, McGraw-Hill, 2000.

## Nagendra Krishnapura, “EE5390: Analog Integrated Circuit Design,” Available:

http://www.ee.iitm.ac.in/∼nagendra/videolectures

135 / 135