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# Expt No: Date:

## DESIGN ENTRY AND SIMULATION OF SEQUENTIAL CIRCUITS

AIM:

To design and implement the following sequential circuits using Verilog HDL
and verify using the testbench

1. Counters
2. Finite State Machine

APPARATUS REQUIRED:

 Xilinx 14.3

THEORY:

Counters

## Synchronous counters are distinguished from asynchronous counters in that

clock pulses are applied to the CP inputs of all flip-flops. The common pulse triggers
all the flip-flops simultaneously, rather than one at a time in succession as in
asynchronous counter. The decision whether a flip-flop is to be complemented or not
is determined from the values of the J and K inputs at the time of the pulse. If J = K =
0, the flip-flop remains unchanged. If J = K = 1, the flip-flop complements. In a
synchronous binary ripple counter, the flip-flop in the lowest-order position is
complemented with very pulse. This means that it’s J and K inputs must be
maintained at logic-1. A flip-flop in any other position is complemented with a pulse
provided all the bits in the lower-order positions are equal to 1, because the lower-
order bits (when all 1’s) will change to 0’s on the next count pulse. The binary count
dictates the next higher-order bit is complemented. Synchronous binary counters
have a regular pattern and can easily be constructed with complementing flip-flops (
J K or T Type) and gates.

## Finite State Machine

Designing a synchronous finite state machine (FSM) is a common task for a
digital logic engineer. A finite state machine can be divided in to two types: Moore
and Mealy state machines. The current state of the machine is stored in the state
memory, a set of n flip-flops clocked by a single clock signal (hence “synchronous”
state machine). The state vector (also current state, or just state) is the value currently
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stored by the state memory. The next state of the machine is a function of the state
vector in Moore; function of state vector and the inputs in Mealy.

PROCEDURE:

1. Start Xilinx ISE 14.3, click on “CREATE A NEW PROJECT” and then click on
Next.
2. Select your working directory, give the name of the project, then click on
“NEXT”.
3. Select the device family (Spartan 3E), Device (XC3S250E), package (PQ208),
Speed grade (4), Synthesis tool (XST [VHDL/VERILOG]), simulator (ISim) and
preferred language (Verilog) from the available device list, and then click
“NEXT” and click FINISH.
4. Write the HDL code and be careful to give the entity name the same as project
name.
5. In the design window change into simulation and double click behavioral
check syntax.
6. If the HDL code is error free a green check mark will be shown on the
behavioral check syntax.
7. Select simulation then double click on “Simulate Behavioral Model” (here we
can change the level of abstraction. i.e. structural/behavioral/dataflow/switch
level)
8. If there is zero error a new window will be shown. Apply the desired input as
1’s and 0’s and check whether the outputs are correct or not in the output
waveform.
9. Create a new verilog test fixture and give the various input constraints and
save the file and check if any errors are present.
10. Simulate the testbench and analyze the output waveform.

COUNTER
Logic Diagram:

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State Diagram

## Up Counter Design using Behavioral Down Counter Design using

Modelling Behavioral Modelling
module counter_up(out,clk,reset); module
output [3:0]out; counter_up_down(out,clk,reset);
input clk, reset; output [3:0]out;
reg [3:0] out; input clk, reset;
always @(negedge clk or posedge reset) reg [3:0] out;
if(reset) always @(negedge clk or posedge
out <=4'b0000; reset)
else if(reset)
out<=out+1; out <=4'b0000;
endmodule else
out<=out-1;
endmodule

## Up/Down Counter Design using Mod-10 Counter Design

Behavioral Modelling module counter_ten(out,clk,reset);
module output [3:0]out;
counter_up_down(out,clk,reset,control); input clk, reset;
output [3:0]out; reg [3:0] out;
input clk, reset,control; always @(posedge clk or posedge
reg [3:0] out; reset)
always @(negedge clk or posedge reset) begin
if(reset) if(clk)
out <=4'b0000; if(reset)

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## else out <=4'b0000;

if (control) else
out<=out+1; if (out==4'b1001)
else out<=0;
out<=out-1; else
endmodule out<=out+1;
end
endmodule

## Counter Design using Structural JK Flip-Flop Design using Behavioral

Modelling Modelling
module module jkff (q,qbar,j,k,clk,reset);
counter_strutural(q,qbar,clk,reset); output q,qbar;
output [3 : 0] q; input j,k,clk,reset;
output [3 : 0] qbar; reg q,qbar;
input clk,reset; always @ (negedge clk or reset)
wire [0 : 1] temp; if (~reset)
reg high; begin
initial q = 1'b0;
high = 1'b1; qbar = 1'b1;
jkff ff1 (q[0],qbar[0],high,high,clk,reset); end
jkff ff2 else if (reset)
(q[1],qbar[1],high,high,q[0],reset); begin
jkff ff3 if (j==0 && k ==0)
(q[2],qbar[2],high,high,q[1],reset); begin
jkff ff4 q = q;
(q[3],qbar[3],high,high,q[2],reset); qbar = qbar;
endmodule end
else if ( j== 0 && k ==1)
Counter Design using Behavioral begin
Modelling q = 1'b0;
qbar = 1'b1;
module counter(clk, reset,result); //,ena end
input clk, reset; else if (j==1 && k == 0)
output [3:0]result; begin
reg [3:0] result; q = 1'b1;
qbar = 1'b0;
always @(negedge clk or posedge end
reset) else if (j ==1 && k ==1)
begin begin
if (reset) q = ~q;

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## result = 0; qbar = ~qbar;

end
else else
result = result + 1; begin
end q = 1'bz;
endmodule qbar = 1'bz;
end
end
endmodule

## FSM Design using Behavioral Modelling

module m1011( clk, rst, inp, outp);

output outp;

reg outp;

## always @( posedge clk, rst )

begin
if( rst )
state <= 2'b00;
else
begin
case( {state,inp} )
3'b000: begin
state <= 2'b00;
outp <= 0;
end
3'b001: begin
state <= 2'b01;
outp <= 0;
end
3'b010: begin
state <= 2'b10;
outp <= 0;
end
3'b011: begin
state <= 2'b01;

## CARE GROUP OF INSTITUTIONS

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outp <= 0;
end
3'b100: begin
state <= 2'b00;
outp <= 0;
end
3'b101: begin
state <= 2'b11;
outp <= 0;
end
3'b110: begin
state <= 2'b10;
outp <= 0;
end
3'b111: begin
state <= 2'b01;
outp <= 1;
end

endcase
end
end

endmodule

RESULT:
The Sequential circuits were designed and, HDL codes were written and verified
using Testbench circuits

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