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Chapter 15

Digital Signal Processing

The trend today in receiver design is toward First, you could demodulate the IF sig-
digital signal processing. This powerful tech- nal and do the signal processing at audio. In
nique frees the receiver of drift problems in- that way, a simple, low-cost ADC is used
volving temperature and power supply (indeed, maybe even your computer’s
voltage excursions. Today, the small size of sound card). A digital-to-analog converter
large-scale integration digital integrated cir- (DAC) is used to convert the signal back to
cuits makes it possible to deliver receivers that audio. About the only thing that can be
could be only dreamed of a generation ago. done after the demodulator is filtering and
Although the goal is to get the analog- audio AGC.
to-digital converter (ADC) as close to the an- Second, the processing takes place at the
tenna as possible, most receivers today fit the IF frequency. The ADC must be considerably
schema shown in Figure 15.1. From the IF better than in the audio case, but this permits
amplifier two paths can be taken by the digi- utilizing the digital circuitry to demodulate the
tal designer. IF signal. It also permits using I-Q quadrature

A/D DIGITAL D/A AUDIO


DEMODULATOR
CONVERTER PROCESSING CONVERTER OUTPUT

IF
AMPLIFIER

A/D DIGITAL D/A AUDIO


CONVERTER PROCESSING CONVERTER OUTPUT

Fig. 15.1 Digital signal processing schema.

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228 THE TECHNICIAN’S RADIO RECEIVER HANDBOOK

processing techniques. After the ADC, there


will be a digital processing stage and a DAC to +VMAX
reconvert the signal to audio.
3Q
It is worth noting that, in radar re-
2Q
ceivers, a significant increase in sensitivity is
available because we can integrate a number Q

of pulses (N). In coherent processing, the IF


is converted and the increase in sensitivity is -Q
N, but in noncoherent processing (after the -2Q
demodulator), it is N. -3Q
Another advantage of using the micro-
-VMAX
processor to control the receiver is that all
the tuning, bandwidth, gain, and control
functions can be implemented through the
microprocessor. The user’s decisions on
which of these to invoke are registered in the
microprocessor and relayed to the circuits ERROR
under control.

ADC NOISE
Fig. 15.2 Quantizing error of the signal.
All reception is a problem of signal-to-noise
ratio (SNR). The ADC must add minimally to
the noise produced in the receiver or the Table 15.1 Quantization Noise Voltage
design will fail. The sampling rate (number N Bit Decibels
of samples per second taken by the ADC) 6 −20
must be high enough to demodulate the 8 −41
bandwidth being handled. Nyquest’s theo-
10 −53
rem tells us that the data sampling rate must
be twice the nominal bandwidth being re- 12 −63
ceived, but because filters have no straight 16 −97
edges, the actual rate will be up to 2.5 times 20 −125
the bandwidth. The width of the sampling
pulse must be small compared to the period
of the highest frequency within the receiver comes too large, then there will be a hard
passband. clipping action taking place at ±NQ, and the
The ADC will add little inherent noise automatic gain control circuits must be bal-
of its own at the IF frequency, but as it gets anced to eliminate this problem. The root
closer to the antenna, with its smaller signal mean square value of the quantizing voltage
levels, the percentage of the total becomes is given in Table 15.1.
higher and higher. As a result, IF processing
probably will be the standard for some time
to come. RECEIVER ARCHITECTURES
Figure 15.2 shows the quantization er-
ror noise that will be encountered in the Figure 15.3 shows the layout of a simple
ADC. The top curve is an input/output single-conversion receiver based on digital
curve, whereas the bottom curve is a repre- techniques. The front end of the receiver
sentation of the error. Each step of the ADC consists of the bandpass filtering, RF ampli-
output is QV high. If the input signal be- fying, and mixing functions. It is driven by a
Digital Signal Processing 229

IF DIGITAL AUDIO
FRONT END AUDIO
AMPLIFIER RECEIVER OUTPUT

AGILE
FREQUENCY
SYNTHESIZER
MICROPROCESSOR

Fig. 15.3 Digital receiver block diagram.

number of signals. The RF signal from the uator, low-pass or bandpass filter, and a
antenna drives the input of the front-end mixer/local oscillator. In this case, the LO is a
circuitry. digital frequency synthesizer.
There will be control signals for select- At the output of the mixer are a band-
ing the bandpass filtering and automatic gain pass filter and a noise blanker. The noise
control for the RF amplifier. Sometimes, a blanker punches a hole in the signal at the
selectable attenuator will be in the circuit +10 dB amplifier whenever a noise impulse
as well. is received. The output of the bandpass filter
Finally, there is the local oscillator cir- feeds a +10 dB amplifier, and the output of
cuit. In this case, the LO is an agile digital that amplifier is mixed with a signal from a
frequency synthesizer controlled by the mi- local frequency standard (which also serves
croprocessor. the digital frequency synthesizer). This pro-
The microprocessor also controls the IF duces the second IF signal, which is the high
amplifier gain through an AGC function. The gain (50–90 dB) stage.
IF amplifier produces an output signal that Following the second IF is the ADC.
almost fills up the ADC in the digital receiver This stage outputs digitized signals to the
section when a strong signal is received at quadrature multiplier stage, which produces
the antenna. Finally, the digital receiver sec- the I and Q signals needed by the channel fil-
tion demodulates the signal and applies it to ter and demodulator stage. If the receiver is
the audio amplifiers for output to the loud- to be used digitally, then the I and Q signals
speaker or earphones. are available as data out lines, but if an audio
The microprocessor controls the front output is required, the signal is fed to a DAC
end, the local oscillator (agile frequency syn- to reform the audio.
thesizer), IF amplifier, and digital receiver Figure 15.5 shows a block diagram of a
section. User inputs on the front panel of the somewhat more complex single-sideband re-
receiver determine which function is to be ceiver. Again, for the sake of simplicity, I do
used. not show the microprocessor that controls
Figure 15.4 shows a block diagram of a the action of the receiver.
high-frequency, double-conversion digital re- The front end consists of the preselec-
ceiver. The microprocessor controls are not tor, mixer stage and a digital frequency syn-
shown here but nonetheless are present. The thesizer. The preselector consists of an RF
front end of the receiver consists of an atten- amplifier and the bandpass or low-pass filter-
230 THE TECHNICIAN’S RADIO RECEIVER HANDBOOK

ANTENNA

NOISE
BLANKER

BANDPASS
LOW-PASS +10 dB
ATTENUATOR MIXER FILTER MIXER
FILTER AMPLIFIER
(15 KHz)

DIGITAL
FREQUENCY
FREQUENCY
STANDARD
SYNTHESIZER

I I
IF CHANNEL Q DATA
A/D QUADRATURE OUT
AMPLIFIER FILTER &
CONVERTER MULTIPLIER
(50 dB) Q DEMODULATOR

D/A AUDIO
CONVERTER OUTPUT

Fig. 15.4 Block diagram of a high-frequency, double-conversion digital receiver.

ANTENNA

IF IF
A/D IF
PRESELECTOR MIXER AMPLIFIER MIXER AMPLIFIER
CONVERTER TRANSLATOR
No. 1 No. 2

DIGITAL FIXED
FREQUENCY FREQUENCY
SYNTHESIZER OSCILLATOR

I DIGITAL
DECIMATION
SSB MIXER MIXER
FILTER
FILTER

BEAT
ENVELOPE D/A AUDIO
DETECTOR
FREQUENCY S CONVERTER OUTPUT
OSCILLATOR

Q DIGITAL
DECIMATION
SSB MIXER MIXER
FILTER
FILTER

D/A AGC
CONVERTER SYSTEM

Fig. 15.5 Block diagram of a complex single-sideband receiver.


Digital Signal Processing 231

ing needed to protect the receiver and im- At the beginning of the digital receiver
prove the intermodulation distortion perfor- section is the ADC. The output of the ADC
mance. IF amplifier 1 is at the first IF is fed to an IF translator stage, which pro-
frequency, which in HF receivers typically is duces the I and Q output signals. Following
about 50 MHz. In VHF/UHF receivers, a first the IF translator, the I/Q signals are fed to
IF of 70, 30, or 10.7 MHz may be used. decimation filters and a digital SSB filter.
The second IF frequency is generated Following the digital SSB filters are a set of
by the mixer following the first IF amplifier mixers and an envelope detector, which de-
and the fixed frequency oscillator. This signal velops the AGC voltage in a DAC circuit.
usually is 10.7 MHz, 9 MHz, 8.83 MHz, or 455 Finally, the signal is mixed with a beat fre-
kHz, depending on the frequency of the re- quency, then combined to form the input to
ceiver and the design. The second IF ampli- the DAC. The output of the DAC is an audio
fier is the amplifier with the highest gain. output signal.