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Using the textio Package

Chapter 8 Using the textio Package

The 1987 VHDL syntax for a file declaration is:
file identifier : subtype_indication is [ mode ] file_logical_name ;

where file_logical_name must be a string expression.

interactivelyÿ adv, N¤ N’_ W0

STD_INPUT is a file_logical_name that refers to characters that are entered interactively from the keyboard, and STD_OUTPUT refers to text that is displayed on the screen. refer to : vt, cÐSÊÿ f—c In QuickHDL reading from the STD_INPUT file brings up a dialog box that allows you to enter text into the current buffer. The last line written to the STD_OUTPUT file appears as a prompt in this dialog box. Any text that is written to the STD_OUTPUT file is also echoed in the Transcript window. You can specify a full or relative path as the file_logical_name; for example:
file filename : TEXT is in “/usr/steve/myfile”;

The standard VHDL package textio contains the following file declarations:
file INPUT: TEXT is in “STD_INPUT”; file OUTPUT: TEXT is out “STD_OUTPUT”;

If a file is declared within an architecture, process, or package, the file is opened when you start the simulator and is closed when you exit from it. If a file is declared in a subprogram, the file is opened when the subprogram is called and closed when execution RETURNs from the subprogram.

QuickHDL User’s and Reference Manual, V8.5_4

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For example. `. i). 8-2 QuickHDL User’s and Reference Manual.textio.all. Writing Strings and Aggregates aggregateÿ n. WRITELINE (OUTPUT. WAIT. will cause the following error: ERROR: Subprogram “WRITE” is ambiguous. END simple_behavior. ARCHITECTURE simple_behavior OF simple_textio IS BEGIN PROCESS VARIABLE i: INTEGER:= 42. T+|ÊN n v„ . BEGIN WRITE (LLL.textio. VARIABLE LLL: LINE.all. LLL). ‹¡ÿ vtÿ `. ENTITY simple_textio IS END. include the following statement in your VHDL source code: USE std. “hello”). A simple example using the package textio is: USE std. the VHDL procedure: WRITE (L. V8.‹¡•¾ A common error in VHDL source code occurs when a call to a WRITE procedure does not specify whether the argument is of type STRING or BIT_VECTOR. ambiguousÿ _ •wkgNIv„j! hñN$Sïv„.Using the Package Using the textio Package Using the Package The textio package contains declarations of types and subprograms that support formatted ASCII I/O operations. END PROCESS.5_4 . To access the routines in textio.

The Issues Screening and Analysis Committee of the VHDL Analysis and Standardization Group (ISAC-VASG) has specified that the textio package reads and writes only decimal numbers. the WRITE procedure is overloaded for the types STRING and BIT_VECTOR. because the compiler could not determine. as in: WRITE_STRING (L. whether the argument “010101” should be interpreted as a string or a bit vector. WIDTH := 0). “hello”). refer to the WRITE_STRING procedure in the io_utils package. The WRITE_STRING procedure simply defines the value to be a STRING and calls the WRITE procedure. The error occurs because the argument “hello” could be interpreted as a string or a bit vector. VALUE: FIELD: VALUE: FIELD: in in in in BIT_VECTOR. but the compiler is not allowed to determine the argument type until it knows which function is being called. JUSTIFIED: in SIDE:= RIGHT. “010101”). even if allowed to. but it serves as a shell around the WRITE procedure that solves the overloading problem. This call is even more ambiguous. QuickHDL User’s and Reference Manual. string’(“hello”)). JUSTIFIED: in SIDE:= RIGHT. Reading and Writing Hexadecimal Numbers The reading and writing of hexadecimal numbers is not specified in standard VHDL. which is located in the file io_utils. WIDTH := 0). The following procedure call also generates an error: WRITE (L.5_4 8-3 . STRING. procedure WRITE(L: inout LINE.vhd. There are two possible solutions to this problem: • Use a qualified expression to specify the type. For further details. as in: WRITE (L. V8. These lines are reproduced here: procedure WRITE(L: inout LINE. • Call a procedure that is not overloaded.Using the textio Package Writing Strings and Aggregates In the textio package.

-. the simulator supplies hexadecimal routines in the package io_utils.5_4 . To use these routines. _ •w •ô Dangling pointers are easily incurred when using the textio package.Read and allocate buffer L2 := L1. Following are examples of good and bad VHDL coding styles: deallocateÿ vtÿ ‘Íe°R ‘M Bad VHDL (because L1 and L2 both point to the same buffer): READLINE (infile.Deallocate buffer Good VHDL (because L1 and L2 point to different buffers): READLINE (infile. L1). bÛ . L1).Copy pointers WRITELINE (outfile.-. . This is because access types must be passed as variables.all.Read and allocate buffer L2 := new string’(L1.all). -. -.io_utils.vhd.Deallocate buffer The ENDLINE Function invalidÿ adjÿ eàeHv„ÿ eàh9cnv„ The ENDLINE function described in the IEEE Standard VHDL Language Reference Manual. The ISAC-VASG has recommended that the ENDLINE function be removed and that the following test be substituted for it: (L = NULL) OR (L’LENGTH = 0) 8-4 QuickHDL User’s and Reference Manual. L1). which is located in the file $MGC_HOME/shared/examples io_utils. V8.-. use work. but functions only allow constant parameters. L1). Dangling Pointers incur: vt.Copy contents WRITELINE (outfile. IEEE Std 1076-1987 contains invalid VHDL syntax and cannot be implemented in VHDL.-. because WRITELINE deallocates the access type (pointer) that is passed to it. compile the io_utils package and then include the following use clauses in your VHDL source code: use std.Writing Strings and Aggregates Using the textio Package To expand this functionality.all.textio.

use std.all. as in the following example: FILE myinput : TEXT IS IN “pathname.all.testbench for 8-bit adder -.function ENDFILE (L: in TEXT) return BOOLEAN. The following VHDL testbench provides an example of how results can be generated by reading vectors from a file. N by To provide stimulus for simulation. This file is named stimulus. IEEE Std 1076-1987. Reading Vectors from a File entity testbench is end. Providing Stimulus batchÿ n.textio. V8.vhd and is provided in the examples subdirectory. use IEEE. Then include the identifier for this file (myinput in this example) in the READLINE or WRITELINE procedure call.std_logic_1164. architecture adder8 of testbench is QuickHDL User’s and Reference Manual. ---------------------------------------------------------.reads file “vectors” ----------------------------------------------------------library IEEE. This is because the ENDFILE function is implicitly declared.5_4 8-5 . this function is commented out of the standard textio package. you can create batch files containing FORCE commands. not just files of type TEXT.dat”.Using the textio Package Providing Stimulus The ENDFILE Function In the IEEE Standard VHDL Language Reference Manual. the ENDFILE function is listed as: -. just declare an input or output file of type TEXT. Using Files Other than Standard Input and Output You can use the textio package to read and write to your own files. so it can be used with files of any type. As you can see. To do this.

variable R : real. alias cout std_logic is ports(1). cin => cin. sum : out std_logic_vector(N downto 1). variable vector_time : time. begin 8-6 QuickHDL User’s and Reference Manual. variable L : line.provide stimulus and check the result test: process file vector_file : text is in “vectors”. port (a : in std_logic_vector(N downto 1). V8. end component.5_4 . cout : out std_logic). alias sum std_logic_vector(8 downto 1) is ports(9 downto 2). -. b => b. alias cin std_logic is ports(10).component alias a std_logic_vector(8 downto 1) is ports(26 downto 19). variable good_number : boolean. sum => sum.declare an alias for each port -.declare one large signal signal ports:std_logic_vector(26 downto 1):=(others=> ‘Z’). -.instantiate the component uut: adderN generic map(8) port map (a => a.Providing Stimulus Using the textio Package -----------------------------------. -. begin -. cout => cout).this makes it easier to connect the signals to the -. variable signo : integer. cin : in std_logic. b : in std_logic_vector(N downto 1). alias b std_logic_vector(8 downto 1) is ports(18 downto 11).component declaration for adderN ----------------------------------component adderN generic(N : integer).

5_4 8-7 .Skip white space next.Illegal character assert false report “Illegal char in vector file: “ & L(i).Test for 1 assert ports(signo) = ‘1’. L). end.Don’t care null. when ‘1’ => -. when others => -. exit. -. for i in L’range loop case L(i) is when ‘0’ => -. end loop. end process. assert false report “Test complete”. when ‘X’ => -. wait. when ‘ ‘ | HT => -. R. V8.wait until vector time wait for vector_time . signo := signo .Test for 0 assert ports(signo) = ‘0’. next when not good_number. end if.Drive 0 ports(signo) <= ‘0’.Drive 1 ports(signo) <= ‘1’. when ‘L’ => -.Using the textio Package Providing Stimulus while not endfile(vector_file) loop readline(vector_file.read the time from the beginning of the line -.skip the line if it doesn’t start with a number read(L. vector_time := R * 1 ns. end loop. -. end case.now. when ‘H’ => -.1.convert real number to time if (now < vector_time) then -. QuickHDL User’s and Reference Manual. GOOD => good_number). signo := 26.

Providing Stimulus Using the textio Package Vector File # Test vectors for 8-bit adder # 0 means force 0 # 1 means force 1 # L means expect 0 # H means expect 1 # X means don’t care # # a b sum #time 87654321 87654321 cin 87654321 cout 0 11111111 00000000 0 XXXXXXXX X 100 00000001 00000001 1 HHHHHHHH L 200 00000010 00000001 0 LLLLLLHH L 300 10000000 00000001 0 LLLLLLHH L 400 11110000 00001111 0 HLLLLLLH L 500 00001111 11110000 1 HHHHHHHH L 600 10101010 10101010 1 LLLLLLLL H 700 00000000 00000000 0 LHLHLHLH H 800 00000000 00000000 0 LLLLLLLL L 8-8 QuickHDL User’s and Reference Manual.5_4 . V8.