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Ce r tif ic at io ns CS302  Digital Logic & Design
Comme rc e
Comp u te r Sc ie nc e
E nglis h BCD binary numbers represent Decimal digits 0 to 9. A 4bit BCD code is used to
represent the ten numbers 0 to 9. Since the 4bit Code allows 16 possibilities, therefore the 1. AN OVERVIEW & NUMBER SYSTEMS
Formal Sc ie nc e s
first 10 4bit combinations are considered to be valid BCD combinations. The latter six
He a lth Sci e nc e s
2. Binary to Decimal to Binary conversion, Binary Arithmetic, 1’s & 2’s complement
combinations are invalid and do not occur.
Manage me nt 3. Range of Numbers and Overflow, FloatingPoint, Hexadecimal Numbers
BCD Code has applications in Decimal Number display Systems such as Counters and
Mar ke ting 4. Octal Numbers, Octal to Binary Decimal to Octal Conversion
Digital Clocks. BCD Numbers can be added together using BCD Addition. BCD Addition is
Mas s Comm
similar to normal Binary Addition except for the case when sum of two BCD digits exceeds 9 or 5. LOGIC GATES: AND Gate, OR Gate, NOT Gate, NAND Gate
Natu ral Sc ie nc e s a Carry is generated. When the Sum of two BCD numbers exceeds 9 or a Carry is generated
a 6 is added to convert the invalid number into a valid number. The carry generated by adding
6. AND OR NAND XOR XNOR Gate Implementation and Applications
Politic al Sc ie nc e
S oc ial Sc ie nc e s
a 6 to the invalid BDC digit is passed on to the next BCD digit. 7. DC Supply Voltage, TTL Logic Levels, Noise Margin, Power Dissipation

Addition of two BCD digits requires two 4bit Parallel Adder Circuits. One 4bit Parallel
8. Boolean Addition, Multiplication, Commutative Law, Associative Law, Distributive Law, Demorg
S ite Map Adder adds the two BCD digits. A BCD Adder uses a circuit which checks the result at the 9. Simplification of Boolean Expression, Standard POS form, Minterms and Maxterms
Links output of the first adder circuit to determine if the result has exceeded 9 or a Carry has been
generated. If the circuit determines any of the two error conditions the circuit adds a 6 to the
10. KARNAUGH MAP, Mapping a nonstandard SOP Expression
original result using the second Adder circuit. The output of the second Adder gives the correct 11. Converting between POS and SOP using the Kmap
BCD output. If the circuit finds the result of the first Adder circuit to be a valid BCD number
(between 0 and 9 and no Carry has been generated), the circuit adds a zero to the valid BCD 12. COMPARATOR: QuineMcCluskey Simplification Method
result using the second Adder. The output of the second Adder gives the same result. Figure 13. ODDPRIME NUMBER DETECTOR, Combinational Circuit Implementation
15.1
14. IMPLEMENTATION OF AN ODDPARITY GENERATOR CIRCUIT
15. BCD ADDER: 2digit BCD Adder, A 4bit Adder Subtracter Unit
16. 16BIT ALU, MSI 4bit Comparator, Decoders
17. BCD to 7Segment Decoder, DecimaltoBCD Encoder
18. 2INPUT 4BIT MULTIPLEXER, 8, 16Input Multiplexer, Logic Function Generator
19. Applications of Demultiplexer, PROM, PLA, PAL, GAL
20. OLMC Combinational Mode, TriState Buffers, The GAL16V8, Introduction to ABEL
21. OLMC for GAL16V8, Tristate Buffer and OLMC output pin
22. Implementation of Quad MUX, Latches and FlipFlops
23. APPLICATION OF SR LATCH, EdgeTriggered D FlipFlop, JK Flipflop
24. Data Storage using Dflipflop, Synchronizing Asynchronous inputs using D flipflop
25. Dual PositiveEdge triggered D flipflop, JK flipflop, MasterSlave FlipFlops
26. THE 555 TIMER: Race Conditions, Asynchronous, Ripple Counters
27. Down Counter with truncated sequence, 4bit Synchronous Decade Counter
28. Modn Synchronous Counter, Cascading Counters, UpDown Counter
Figure 15.1 4Bit BCD Adder
29. Integrated Circuit Up Down Decade Counter Design and Applications
30. DIGITAL CLOCK: Clocked Synchronous State Machines
31. NEXTSTATE TABLE: Flipflop Transition Table, Karnaugh Maps
32. D FLIPFLOP BASED IMPLEMENTATION
141
33. Moore Machine State Diagram, Mealy Machine State Diagram, Karnaugh Maps
34. SHIFT REGISTERS: Serial In/Shift Left,Right/Serial Out Operation
35. APPLICATIONS OF SHIFT REGISTERS: SerialtoParallel Converter
36. Elevator Control System: Elevator State Diagram, State Table, Input and Output Signals, Input La
37. Traffic Signal Control System: Switching of Traffic Lights, Inputs and Outputs, State Machine
CS302  Digital Logic & Design 38. Traffic Signal Control System: EQUATION DEFINITION
39. Memory Organization, Capacity, Density, Signals and Basic Operations, Read, Write, Address, da
40. Memory Read, Write Cycle, Synchronous Burst SRAM, Dynamic RAM
The circuit that checks if the output of the first Adder has exceeded 9 is a simple
combinational circuit with the function table specified. Table 15.1 41. Burst, Distributed Refresh, Types of DRAMs, ROM ReadOnly Memory, Mask ROM
42. First InFirst Out (FIFO) Memory
Input Output Input Output
S3 S2 S1 S0 F S3 S2 S1 S0 F 43. LAST INFIRST OUT (LIFO) MEMORY
0 0 0 0 0 1 0 0 0 0
44. THE LOGIC BLOCK: Analogue to Digital Conversion, Logic Element, LookUp Table
0 0 0 1 0 1 0 0 1 0
0 0 1 0 0 1 0 1 0 1 45. SUCCESSIVE –APPROXIMATION ANALOGUE TO DIGITAL CONVERTER
0 0 1 1 0 1 0 1 1 1
0 1 0 0 0 1 1 0 0 1
0 1 0 1 0 1 1 0 1 1
0 1 1 0 0 1 1 1 0 1
0 1 1 1 0 1 1 1 1 1
S3S2\S1S0 00 01 11 10
00 0 0 0 0
01 0 0 0 0
11 1 1 1 1
10 0 0 1 1
142
Cin4 Cin= 0
1st MSD 4bit Adder 1st LSD 4bit Adder
Cout8 Cout4
S47 0 0
S03 0
Cin4=0 0
Cin= 0
Cout8 2nd MSD 4bit Adder Cout4 2nd LSD 4bit Adder
Cout
S47 S03
Consider two examples. In the first example, 2digit BCD number 99 is added with
another 2digit BCD number 99. The answer should be 198 a 3digit BCD number. Table 15.2.
In the second example, 2digit BCD number 99 is added with another 2digit BCD number 66.
The answer should be 165. Table 15.3
143
The 2's complement of any number is obtained by taking the 1's complement of a
number and then adding a 1 to the 1's complement. The two step process to represent a
negative number in its 2's complement form is shown
144
1001 1010
A (03) B (03)
Sum (03)
The Adder circuit adds the number 9 (1001), 1's complement of 5 (1010) and the Carry
In which is set to 1.
B3 B2 B1 B0
Add = 0
Subtract = 1
U C U C U C U C
A3 A2 A1 A0
CIn
COut
4bit Parallel Adder
S3 S2 S1 S0
145
The AND gate and OR gate implementation connected at the B input of the 4bit Adder
is used to allow Complemented or UnComplemented B input to be connected to the Adder
input. Adding of two 4bit numbers A and B can be performed by selecting the Add/Subtract =
0. The AND gates marked U (uncomplemented) are enabled allowing B03 to be passed on to
the OR gates and the B input of the Adder. Subtraction is performed by selecting the
Add/Subtract = 1. The AND gates marked C (complemented) are enabled allowing
complemented B03 to be passed on to the OR gates and the B input of the Adder. The Carry
In is also set to 1 when Add/Subtract is set to 1.
The 8bit Adder/Subtracter Circuit is similar to the 4bit Adder/Subtracter Circuit. Two
sets of ANDOR based circuit that allows complemented and uncomplemented B input to be
applied at the B inputs of the two 4bit Adders. The Add/Subtract function select input are tied
together. The Carry In of the 1st 4bit Adder circuit is connected to the Add/Subtract function
select input. The Carry Out of the 1st 4bit Adder circuit is connected to the Carry In of the 2nd
4bit Adder circuit.
B7 B6 B5 B4 B3 B2 B1 B0
Add = 0
Subtract = 1
U C U C U C U C U C U C U C U C
A7 A6 A5 A4 A3 A2 A1 A0
CIn CIn
2 nd 4bit Parallel Adder 1st 4bit Parallel Adder
COut
S7 S6 S5 S4 S3 S2 S1 S0
Consider two number A=103 and B=67 which are first added and then subtracted using the 8
bit Adder/Subtracter Circuit. Table 15.4 and Table 15.5
146
There are different MSI ALUs available that have two 4bit inputs a 4bit output and
three to five function select inputs that allows up to 32 different functions to be performed.
Three commercially available 4bit ALUS are
· 74XX181: The 4bit ALU has five function select inputs allowing it to perform 32 different
Arithmetic and Logic operations.
· 74XX381: The 4bit ALU only has three function select inputs allowing only 8 different
arithmetic and logic functions. Table 15.6
· 74XX382: The 4bit ALU is similar to the 74XX381, the only difference is that 74XX 381
provides groupcarry lookahead outputs and 74XX382 provides ripple carry and overflow
outputs
Input
S2 S1 S0 Function
0 0 0 F=0000
0 0 1 F=BA1+Cin
0 1 0 F=AB1+Cin
0 1 1 F=A+B+Cin
1 0 0 F = A ⊕B
1 0 1 F=A+B
1 1 0 F=A.B
1 1 1 F=1111
147
GroupCarry LookAhead
The LookAhead Carry Generator discussed earlier and used by the 74LS283 Adder
provides Carry's C1, C2, C3 and C4 simultaneously after a gate delay of two. Carry's C1, C2 and
C3 are used internally, where as C4 provides the Cout from the 74LS283. Referring to the Look
Ahead Carry Generator Circuit the C1, C2, C3 and C4 terms are generated on the basis of P0,
P1, P2 and P3 the four Carry Propagate terms and G0, G1, G2 and G3 the four Carry Generate
terms. Figure 15.9
Figure 15.9 LookAhead Carry Generator
These terms are used to generate GroupCarry LookAhead outputs that can be used
to cascade together multiple units eliminating the problem of rippling carry. The G and P
output pins of the 74XX381 provide the groupcarry lookahead outputs that allow multiple
ALUs to be cascaded together. The activelow outputs G and P are represented by the
Boolean expressions. Figure 15.10
148
S0
S0 G
S1
S1 P
74X381
S2
S2
Cin
A4 F4
A0 F0
B4 F5
B0 F1
A5 F6
A1 F2
B5 F7
B1 F3
A6
A2
B6
B2
A7
A3
B7
B3
149