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Floating Gate Devices:

Operation and Compact Modeling

Paolo Pavan(1), Luca Larcher(1)


and Andrea MarmirolI(2)

(1) Università di Modena e Reggio Emilia, Via Fogliani, 1 –


42100 Reggio Emilia (Italy) - pavan.paolo@unimo.it
(2) STMicroelectronics, Central R&D, Via C. Olivetti, 2,
20010 Agrate Brianza (MI), Italy – andrea.marmiroli@st.com
OUTLINE
z Motivation and Purposes
z Floating Gate (FG) Device model:
z FG voltage calculation (DC)
z Parameter extraction procedure
z Program/erase current modeling (TRANSIENT)
‰ Fowler-Nordheim tunnel current + a new self-consistent
model to calculate the electric field within the oxide
‰ Channel Hot Electron (CHE) and Channel Initiated
Secondary Electron (CHISEL) currents
z Reliability simulations
‰ Stress and Radiation Induced Leakage Current
z Advantages and Conclusions
MOTIVATIONS AND PURPOSES
z FG memory cells are usually replaced with standard MOS
in industry circuit simulations: Spice-like models demanded

z The standard method to calculate the FG potential uses


capacitive coupling coefficients, αi= Ci/CT

VFG = αCG VCG + αD VD + αSVS + αBVB

z Constant capacitive coupling coefficients ⇒ errors [1]


z The optimum model should be: Spice-like, compact,
accurate, reliable (both DC and transient)
[1] L. Larcher, et al., IEEE Trans. Elect. Devices, Sept. 2001
The new DC model

Control Gate
CPP
Floating Gate

VFG

Source Body Drain


P-substrate

CPP = interpoly dielectric capacitance


VFG = Floating Gate voltage
Elements of the DC model
z The new Spice-like model uses lumped circuit
elements:
z the capacitor, CPP, which takes into account the
inter-poly dielectric capacitance
z the MOS transistor: can be MOS Model 9 (Philips)
or BSIM3v3 (Berkeley), or …
z The voltage controlled voltage source, VFG:
z It implements the procedure to calculate the FG
voltage in a C code routine
z It is necessary to overcome problems in simulating a
capacitive net in DC conditions
VFG calculation
CG z VFG is calculated by
solving the charge
FG
neutrality equation at the
VFG FG node:

D S
B QMOS + QCPP = QW/E

z QCPP = CPP(VFG-VCG)
z QW/E = charge injected into the FG during the write/erase
(constant in DC conditions)
z QMOS = f(VFG,VS,VB,VD) calculated by means of the MOS
model charge equations ….
QMOS calculation
z MOS Model 9 (Philips) charge equations:

QMOS = −[QB + QD + Q S] + C GDO VGD + C GSOVGS + C GBOVGB

QB = f (C OX , VFB, VSB, VT1, VGB, K0 )

Q S = f (VDS2 , VGT3 , C OX , δ2 , FJ )

QD = f (VDS2 , VG T3 , C OX , δ2 , FJ )

z MOS Parameters: K0, COX, VFB


z MOS electrical internal variables: VT1, VGT3, VDS2, δ2, FJ
Solution of charge equation
z The charge neutrality equation is an implicit equation in
VFG:
F(VFG) = QMOS(VFG) + QCPP(VFG) – QW/E = 0
z It has no analytical solution, due to the complex expression
of QMOS
z ELDO (Spice-like simulator) solves it numerically through
suitable convergence algorithms
z Note that F is monotonic versus VFG for all the bias
combinations (VCG,VS,VB,VD) in the functionality range of
the device, thus guaranteeing the physical meaning of the
derived VFG solution
Parameters of the model
z Parameters of the equivalent MOS transistor (dummy cell):
z they can be extracted by applying the standard MOS
parameter procedure to the dummy cell.

z Only one additional parameter compared to a standard


MOS transistor: the Floating Gate to Control Gate
capacitance CPP
z derived from the cross section and layout of the cell

z No additional costs compared to the standard modeling


activity for MOS transistors
z The model is very easy and simple to use
The new transient model
z The DC model of FG memories can be extended to model
transient conditions by adding some voltage controlled
current sources to include program and erase currents
z Write currents of E2PROM and Flash are different: hence,
number and position of current sources may vary for
E2PROM and Flash
z Each voltage controlled current source models analytically
a specific kind of program/erase current: Fowler-Nordheim,
CHE, CHISEL
z One additional Eldo parameter allows the user to choose
the desired Floating Gate memory (Flash or E2PROM)
model
The new transient E2PROM model

Control Gate

CPP
Floating Gate

IW/E VFG
Source
Drain

P-substrate Body

z For E2PROM memories, IW/E models the program/erase


Fowler-Nordheim current flowing across the tunnel oxide
The new transient Flash model

Control Gate
CPP
Floating Gate
Iw1 Iw3
VFG
Iw2
Source Drain
Body P-substrate

z For Flash memories: IW1 and IW2 model the erase FN current;
IW3 the CHE+CHISEL program current
Fowler-Nordheim current source
z The voltage controlled current source (implemented in
ELDO) modeling Fowler/Nordheim currents allows to
reproduce program-erase and erase operations of
E2PROM and Flash memories, respectively.

 BFN 
IFN(Fox ) = ATA F ⋅ exp  −
2
FN ox 
 Fox 
‰ AT = area of the tunneling region
‰ AFN , BFN = Fowler-Nordheim coefficients depending
on the Si/SiO2 barrier
‰ FOX = electric field across the oxide, which has
been evaluated through ….
FOX calculation

FOX =
(V FG − VS,D ,B ) − VFB − ψS − ψ P
TOX
– VFB = flat-band voltage
– ψS = surface potential drop at Si/SiO2 interface

– ψP = surface potential drop at poly-Si/SiO2 interface

z To correctly evaluate ψS and ψP is necessary to take into


account poly depletion and charge quantization effects:
for this reason, a self consistent model has been used [2]
z The so calculated FOX has been incorporated in the FG
model through an analytical law, parameterized on the FG
and S,D,B dopings, which are additional parameters
[2] L. Larcher et al., “A new model of gate capacitance …”, IEEE Trans. Elect. Devices
CHE-CHISEL current source
z CHE-CHISEL gate currents have been modeled
analytically and included by means of a voltage controlled
current source
z This way, actual program operations of modern Flash
memories can be reproduced also by circuit simulations
z The CHE-CHISEL current model adopts a new approach to
model hot carrier phenomena, and particularly, to describe
the high energy distribution of carriers involved in impact
ionization phenomena
CHISEL current modeling
z The key point of CHISEL[3] current modeling is the accurate
calculation of energy distribution of tertiary electrons, that
are generated by four physical mechanisms (M)

Gate CHISEL
CHE

M4
e1 e1,2
Source e3 M2 M1 Drain
h2
Impact Ionization
M3
Body
h2,3
[3] L. Larcher, P.Pavan, “A New Analytical Model of Channel Hot Electron (CHE) and
CHannel Initiated Secondary ELectron (CHISEL) …,” MSM 2002, 2002, pp. 738-741.
Reliability Simulations
z Leakage currents across the gate oxide (SILC[4] - RILC[5])
are modeled analytically and included by means of some
voltage controlled current sources
z The model can simulate the reliability degradation of Flash
and E2PROM memories due to the aging of the gate oxide
induced by Program/Erase cycles and also by the exposure
to ionizing radiation: read/gate/drain disturb prediction
z Now, our work is focused to model leakage currents due to
Trap-Assisted Tunneling through n-traps including also the
phonon contribution (percolation path)

[4] L. Larcher et al. “A Model of the Stress Induced Leakage Current in Gate Oxides”, IEEE Trans.
Electr. Devices, Vol.48, N.2, 2001, pp.285-288.
[5] L. Larcher et al. “ A model of radiation induced leakage current (RILC) in ultra-thin gate oxides”,
IEEE Trans. Nuclear Science, Vol. 46 (6), pp. 1553-1561, 1999.
SILC - RILC modeling
z The Stress-Induced Leakage Current (SILC) and the
Radiation-Induced Leakage Current are modeled
assuming an inelastic Trap-Assisted Tunneling (TAT) as
conduction mechanism

cathode SiO2

Ep

xT
anode
tox
Simulation results
z Simulation results achieved by this model are excellent in
both DC and transient condition, for either Flash and
E2PROM memories, WITHOUT any free parameter to
improve the fitting quality
z We tested the simulation capability of this model on both
E2PROM and Flash memories, in DC and transient
conditions.
DC – E2PROM: IDS-VCG
10-5
VSB= 0V
10-6 CPP = 3 fF
W=0.3 µm
-7 L=0.75 µm
I DS (A)

10
VSB= 5V
10-8
simulation
10-9
VSB (exp) 0..5 step 1V
-10
10
0 1 2 3 4 5
VCG (V)
DC – E2PROM: IDS-VDS
140
simulation VG= 5V
120
VB= 0V
100 VG= 4V

80
I DS (µA)

VG= 3V
60
VG= 2V
40
20 VG= 1V

0
0 0.5 1 1.5 2 2.5 3 3.5 4
VDS (V)
DC – E2PROM: IDS-VCG
120
simulation VB= 0V
100 VD (exp) 0.8..3.8 step 1V

80
I DS (µA)

60 VD= 3.8V

40

20 VD= 0.8V

0
0 1 2 3 4 5
VCG (V)
DC – Flash: IDS-VCG
10-4
VSB (exp) 0..2 step 0.5V
10-5

10-6 VSB= 0V CPP = 0.8 fF


W=0.25 µm
10-7 L=0.375 µm
I DS (A)

10-8 VSB= 2V
10-9
VDS= 0.1V
10-10
simulation
-11
10
2 3 4 5 6 7
VCG (V)
DC – Flash: IDS-VDS
25
simulation VCG= 4 V

20 VB= 0 V
VCG= 3.75 V
15
I DS (µA)

VCG= 3.5 V
10
VCG= 3.25 V
5 VCG= 3 V

0
0 0.3 0.6 0.9 1.2 1.5 1.8
VDS (V)
DC – Flash: IDS-VCG
60
simulation CPP = 0.4 fF
50 W=0.16 µm
L=0.3 µm
VD (exp)
40
0.1 V
I D (µA)

0.7 V
30 1.3 V
1.9 V
20

10

0
2 2.5 3 3.5 4 4.5 5 5.5 6
VCG (V)
DC – Flash: IDS-VDS
25
VCG= 3.4 V
simulation
20 VB= 0 V
VCG= 3.2 V
CPP = 0.4 fF
15 W=0.22 µm
VCG= 3 V
I DS (µA)

L=0.3 µm

10 VCG= 2.8 V

5
VCG= 2.6
0
0 0.3 0.6 0.9 1.2 1.5 1.8
VDS (V)
DC – Flash: IDS-VDS
30
simulation
25
VD (exp)
20 0.4 V
I D (µA)

0.8 V
15 1.2 V
1.6 V
10

0
1.5 2.0 2.5 3.0 3.5
VCG (V)
Transient – Flash: VT - time
7
VG0(exp) -2.7..-4.7 step 1V
6 Erase bias:
D float
5
VG0= -4.7 V VS=VB=8 V
4
V T (V)

VCG

3 VG,MAX
VG0= -2.7 V
2
VG0
1 Time
simulation VB= VS= 8 V
0
0 0.1 0.2 0.3 0.4
Time (s)
Transient – Flash: VT - time
7
dV/dt (exp)= 12.5,20,25,30,35,50,60 V/s
6 simulation
5

4
V T (V)

dV/dt= 12.5V/s
3
2

1
dV/dt= 60 V/s
0
0 0.1 0.2 0.3 0.4
Time (s)
Erase E2PROM: VT - time
4
Lines: simulations
3 Symbols: measures

1
VT (V)

0.3 0.4 0.5 0.6


0 TRISE(ms 12V VCG-ramp
)
-1

-2 VD=VB=0V
TRIS VS=0V
E
-3
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time (ms)
Program E2PROM: VT - time
3
12V VD-ramp

2
VCG=VB=0V
TRIS VS floating
1
VT (V)

TRISE(ms
0 0.6 0.7
)
0.3 0.4
-1
Lines: simulations
Symbols: measures
-2
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time (ms)
Program E2PROM: VFG and VS
6
Dotted lines: VFG
5 Solid lines: VS

3 TRISE(ms
) 0.6
2 0.3 12V VD-ramp

0
TRIS
-1 E

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1


Time (ms)
Erase E2PROM: Tunnel Current
60
Lines: simulations VD-ramp

50 Symbols: measures Nominal

40 Rea
ITUN (pA)

TRIS l
30 E

20

10 dVT
ITUN,MEAS = −C CG
dt
0
0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
Time (ms)
Simulation results: Flash program
9
8 VDS = 4.2V
8
4
7 VCG pulse (V)
0 No free
6 0 1 2 3 4
parameter
VT (V)

time (µs)
5 to improve
VSB (exp) the fitting
4 0V quality!!
0.6 V
3 1.2 V
(A) 1.5 V
2
0 1 2 3 4
time (µs)
E2PROM retention simulations

NC
4.7
10 - 1 - fresh
4.2 2
10
VT(V)

3.7
3
10
4
3.2 10

NC= 105
2.7
0 1 2 3 4 5 6 7 8 9 10
Years
E2PROM read path schematic
VPSENSE
Current bias Sense
out
for sense VISENSE Amplifier
amp

VBOOST

COL<0> COL<i> COL<n>

CG bias VCG CG voltage


voltage transfer
generator block

COL<i> BL
WL

Mini array of
virgin cells CELLS
CG<i>
E2PROM read path signals
6
VW L
5

4
V (V)

3 VSENSEOUT

2 VCG
VCELL
1 VREF
VB L
0
0 100 200 300 400 500
Time (nsec)
E2PROM read path signals /2
3.0 3.0
VSENSE OUT VSENSE OUT
2.5 2.5
VCELL
2.0 VCELL 2.0
V (V)

V (V)
1.5 1.5 VREF
VREF
1.0 1.0 VB L
VB L

0.5 0.5

0 0

310 330 350 370 390 410 320 340 360 380 400 420
Time (nsec) Time (nsec)
Advantages
z This model features many advantages compared to
others proposed in the literature:
‰ The parameter extraction procedure is the same of a
standard MOS transistors
‰ The simulation time is comparable to that of a simple
MOS transistor
‰ VFG calculation procedure does NOT use capacitive
coupling coefficients:
z this means a more accurate VFG calculation
(considering the capacitive coupling coefficients
as constants introduces errors)
Coupling coefficients: αCG - Flash
VB=-1V αCG
VS=0V 0.72

0.70

0.68

0.66

0.64
0
22.
11.13 0
33.38
55.63
44.5 1
9 8 66.75 2
3
4
VCG 5
VD
VFG = αCG VCG + αD VD + αSVS + αBVB
Coupling coefficients: αD - Flash
αD
VFG = αCG VCG + αD VD + αSVS + αBVB 0.15

0.13

0.11

0.07

0 0
0.05
10 9
20 2
30 3
40 4
50 5
60
7
8 VD
9
VCG VB=-1V
VS=0V
Advantages /2
‰ This is the first compact DC and transient model of a FG
memory cell: it can be used for both single device
simulations and circuit simulations

‰ Fitting results are excellent WITHOUT any free parameter


to improve the fitting quality

‰ This model is easily scalable: scaling rules are taken into


account in the MOS model itself, and they do not affect
the VFG calculation

‰ This model is easily upgradeable: voltage controlled


current sources can be replaced independently on other
elements of the model
Conclusions
z We developed a new compact Spice-like DC and
transient model of the FG memory cell
z It overcomes the fixed coupling coefficients approach,
thus improving the FG memory cell modeling
z It is easily scalable and upgradeable
z Its simulation time is not critical
z Parameters can be extracted applying the same
procedure used for MOS transistor
z Simulation results are excellent without any free
parameter to improve the fitting quality
z It can be used for statistical analysis (effects of statistical
fluctuation of critical parameters)
References
z Paolo Pavan, Luca Larcher, Andrea Marmiroli,
Floating Gate devices: Operation and
Compact Modeling, Kluwer Academic
Publishers, 2004, 140 pp., ISBN 1-4020-7731-9