Datorarkitektur I

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Let’s Have a Look into the CPU


I/O 1

I/O 2

I/O n

System Bus 1. Why is a Control Unit Needed inside the CPU? CPU 2. Microoperations and Control Signals 3. The Control Unit - Basic Tasks System Bus 4. Hardwired Control 5. Microprogrammed Control ALU CPU Registers Main Memory

Control Unit Internal CPU Bus


Petru Eles, IDA, LiTH

Petru Eles, IDA, LiTH

Datorarkitektur I

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Datorarkitektur I

Address Bus
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Control Bus Fetch instruction Execute instruction

Instruction Execution
Let’s Have a Look into the CPU (cont’d) • • The CPU executes a sequence of instructions. The execution of an instruction is organized as an instruction cycle: it is performed as a succession of several steps;

The question that has to be answered: • How are the elements inside the CPU and the interface to the external datapath controlled in order to work properly?

To perform this control, that’s the task of the Control Unit •

Each step is executed as a set of several microoperations. The task performed by any microoperation falls in one of the following categories: - Transfer data from one register to another; - Transfer data from a register to an external interface (system bus); - Transfer data from an external interface to a register; - Perform an arithmetic or logic operation, using registers for input and output.

Petru Eles, IDA, LiTH

Petru Eles, IDA, LiTH

Data Bus

Read • The CPU executes an instruction as a sequence of control steps. Clear Y. IRin indirect addressing R3out.(R3) R1 ← R1 + [R3] Comments: • The first (three) control steps are identical for each instruction. IRin R1out. R1in b) signals for adding content of Y to that of R0 (result in Z): R0out. Read. End Petru Eles. R1in. IDA. Zin Zout. PCin MBRout. In each control step one or several microoperations are executed. address in R3: R3out. The following steps depend on the actual instruction (stored in the IR). Carry-in. one or several control signals have to be issued. One clock pulse triggers the activities corresponding to one control step ⇒ for each clock pulse the control unit generates the control signals corresponding to the microoperations to be executed in the respective control step. Clear Y.see lect. they allow the corresponding data transfer and/or computation to be performed. MARin. Add. PCin MBRout. MARin. Zin c) signals for reading a memory location. PCin MBRout. MARin.8 Microoperations and Control Signals (cont’d) Microoperations and Control Signals (cont’d) instruction: ADD R1. End unconditional branch (with relative addressing . PC←PC+1 1 2 3 4 5 6 PCout. MARin. the value will be available in the MBR after one additional step. Zin Zout. they perform instruction fetch and increment the PC. PCin. Zin Zout. Clear Y. Read R1out. Add.7 Datorarkitektur I Fö 11. • If a control step issues a read. Carry-in. Zin Zout.Datorarkitektur I Fö 11. Add. PC PCout MARin Status&Cond. MARin. Examples: a) signals for transferring content of register R0 to R1: R0out. only one of them is allowed to output on the bus) control steps and control signals: fetch ins. Yin MBRout. Zin Zout. Add. Yin R3out. LiTH Petru Eles. Carry-in. PC←PC+1 1 2 3 4 5 6 7 PCout. IDA. Zin Zout. LiTH Petru Eles. PC←PC+1 1 2 3 4 5 6 PCout. R1in.R3 R1 ← R1 + R3 instruction: BR target control steps and control signals: fetch ins. Read. End instruction: ADD R1. IRin PCout. IDA.5 Datorarkitektur I Fö 11. • Several microoperations can be performed in the same control step if they don’t conflict (for example. Add. Read. 5) control steps and control signals: fetch ins.6 Instruction Execution (cont’d) PCin Microoperations and Control Signals Control signals In order to allow the execution of a microoperation. Add. IDA. Flags Control unit IRin System bus MAR MBRin Clock IR IRout MBR MBRout Yin R0in R0 R0out Clear Y Y Yout Add XOR Zin • ALU Rn-1in Carry-in Rn-1 Z Zout Rn-1out Petru Eles. LiTH . Add. LiTH Datorarkitektur I Fö 11. Yin (displacement-field)IRout.

the control unit is a combinatorial circuit. IDA.g. IDA. LiTH Petru Eles. . Hardwired control 2.external signals received on the system bus (e.step 6 of ADD with register-indirect addressing . IR Control signals internal to the CPU Control unit Control signals on system bus Signals from system bus • The control unit is driven by the processor clock. interrupt signals). flags. IDA. Flags Generation of signal Zin: . . IR Instruction decoder I1 I2 I3 In Status&Cond. LiTH Datorarkitektur I Fö 11. LiTH Petru Eles. Flags The basic task of the control unit: . it gets a set of inputs (from IR. .step 7 of ADD with register-indirect addressing .in each control step the control unit issues a set of signals which cause the corresponding microoperations to be executed. Reset Step counter and decoder T1 T2 Encoder block (combinatorial signal generator) Clock Tn Generation of signal End: .first step of all instructions (fetch instruction) .the condition and status flags of the processor. Microprogrammed control Petru Eles.Datorarkitektur I Fö 11.the actual instruction executed. Clock • Techniques for implementation of the control unit: 1.10 Control Unit Control Unit (cont’d) Status&Cond. From system bus End Control signals Petru Eles.step 6 of ADD with register addressing .for each instruction the control unit causes the CPU to go through a sequence of control steps.step 5 of BR . LiTH . system bus) and transforms them into a set of control signals.------------------Zin = T1 + T5 ⋅ (ADDreg + BR) + T6 ⋅ ADDreg_ind + .step 5 of ADD with register addressing . . .11 Datorarkitektur I Fö 11. .the actual step to be executed.9 Datorarkitektur I Fö 11. .step 6 of BR . The signals to be generated at a certain moment depend on: . clock.12 Hardwired Control Hardwired Control (cont’d) • In this case. . IDA.------------------End = T6 ⋅ (ADDreg + BR) + T7 ⋅ ADDreg_ind + .

Microprogrammed Control Unit Status&Cond. Flags • • IR Address generator (AG) µPC INCR Control store (CS) gen. In order to allow execution of register-to-register operations in a single clock cycle.15 Datorarkitektur I ALU Fö 11. each bit in a CW corresponds to one control signal. Each control step during execution of an instruction defines a certain CW.basic idea: • All microroutines corresponding to the machine instructions are stored in the control store. end-fetch branch Clock Sequencer The control unit is implemented just like another very simple CPU. LiTH Petru Eles. RISCs (and other modern processors) use three-bus CPU structures (see following slide). IDA. LiTH . IDA.16 Microprogrammed Control • Control word (CW): a sequence of Nsig bits. Clock RISCs are implemented with hardwired control. LiTH Datorarkitektur I Fö 11. Microroutine: a sequence of CWs corresponding to the control sequence of a machine instruction.13 Datorarkitektur I Fö 11. where Nsig is the total number of control signals. Signals from system bus Control signals IAB: Internal Address Bus Petru Eles.14 Control signals Hardwired Control (cont’d) Control unit • • • Hardwired control provides highest speed. IAB Control buffer/ decoder (CB/D) end. it represents a combination of 1s and 0s corresponding to the active and nonactive control signals. An individual CW in a microroutine is called a microinstruction. In this case microprogrammed control units are used. • The control unit generates the sequence of control signals for a certain machine instruction by reading from the control store the CWs of the microroutine corresponding to the respective instruction. LiTH Petru Eles. IDA. addr Microprogrammed control . IR PC R0 Status&Cond.Datorarkitektur I Fö 11. inside the CPU. Flags • Rn-1 MBR MAR System bus Petru Eles. IDA. executing microroutines stored in the control store. If the instruction set becomes very complex (CISCs) implementing hardwired control is very difficult.

18 Control Store Organization Microroutine Executed for Conditional Branch Addr-fetch Control store ----------------------------------------end-fetch ----------------------------------------branch addr-fetch ----------------------------------------end ----------------------------------------end Fetch instruction Interrupt routine Execute instr. The microroutines contain. IDA. code n • • • The control store contains the microprogram (sometimes called firmware). LiTH . Control units can be implemented hardwired or microprogrammed. Each instruction of the microprogram practically represents the set of signals which the control unit has to issue in the respective control step. Petru Eles. LiTH Petru Eles. The sequencer is controlling the right execution sequence of microinstructions. hardwired controllers become too complicated. IDA. code 1 A_fetch +1 +2 +3 A_CB +1 +2 +3 +4 +5 PCout. Clear Y. Read. IRin end-fetch this produces the jump to A_CB -------------branch to A_CB+2 if N set end PCout. also branches which have to be interpreted by the microprogrammed controller. beside CWs. LiTH Datorarkitektur I Fö 11. Zin Zout. MARin. A microprogrammed control unit is implemented like another CPU inside the CPU. It executes microprogrammes stored in the control store. IDA. Add. Add. The sequencer is a small control unit of the control unit. Addr-instr0 Addr-instr1 Addr-instrn ----------------------------------------end Execute instr. They are used in all RISCs. Therefore CISCs are implemented with microprogrammed controllers. It is doing this by issuing in each clock cycle the appropriate control signals. A hardwired control unit is a combinatorial circuit which gets a set of inputs and transforms them into a set of control signals. Yin (displacement-field)IRout. PCin MBRout.19 Summary • • • • • • • • The control unit is in charge of coordinating the activities inside the CPU and the interaction with the outside. Petru Eles. PCin end Addr-interr.17 Datorarkitektur I Fö 11. A set of control signals activates the microoperations which have to be executed in a given control step. Hardwired controllers are faster then microprogrammed ones.Datorarkitektur I Fö 11. Zin Zout. If the instruction set is complex. Carry-in. code 0 Execute instr.

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