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PCB Design Rule Check:

 Major Rules:
o Integrity of point to point signal.
o Timing relationship between signals.
o Coupling of traces.
o Noiseless power supply.
o Electromagnetic radiation.
 Keep the high-rise time signals separate. As they may induce crosstalk or electromagnetic
radiation of the harmonics of the base signal. Radiation pattern observed in a spectrum analyzer
shows frequencies that are multiples or harmonic of clock oscillators.
 Sudden change in voltage causes electric field coupling (dv/dt) also called capacitive coupling.
 Sudden change in current causes magnetic field coupling (di/dt) also called inductive coupling.
 Signal typically takes 150ps to travel 1inch.
 Crystals are major sources of electromagnetic field radiation as they usually have high-rise time.
 If the width of the trace is fixed, the distance from the ground and power plane is fixed, then the
characteristic impedance is fixed. It doesn’t vary.
 If there is a via, connector, layer change, change in trace thickness and addition of test points
along the trace lead to change in the characteristic impedance of the trace. This also increases
reflections. Capacitive discontinuity – via, thicker trace. Inductive discontinuity – connector,
thinner trace.
 Low AC impedance between power and ground pins of all the IC’s at all frequencies ensures that
the noise on AC rail is shorted to GND.
 Big bulk capacitors between power and GND plane reduces low frequency noise.
 Small decoupling caps with low parasitic inductance placed near the IC’s creates low impedance
AC path between power and GND planes.
 Use a 2D field solver to find the trace length and impedance.
 The characteristic impedance of a microstrip is close to 50Ω if w=2*h.
 The stack-up should be designed such that it provides a proper return path for the high-speed
signals.
 If there are more than one power islands in the power layer, they should be connected by
stitching capacitors to provide a continuous return path for the signals. Place the stitching
capacitors at the junction of the power planes.

 Differential signal rules:


o Definite width of the trace.
o Definite separation between positive and negative trace.
o Definite separation between trace and power and GND planes.
o Keep the lengths of positive and negative trace matched, typically within 50 mils.
 Via’s and traces for power and GND should be thick.
 Keep power and GND traces close to each other.
 Portion of the signal gets reflected at the junction where the impedance of the trace changes,
this causes the signal to distort at the receiving end.
 PCB signals over 1GHz have significant trace loss as it propagates, if the length exceeds 10
inches, the loss can be significant.
 Knee frequency is the estimate of the highest frequency content of the signal. It depends upon
the rise time of the signal.
o fknee – 0.35/τ
o fknee – highest frequency content of the signal
o τ – 10% - 90% rise time of the signal

 A periodic waveform consists of one low frequency component and multiples of the low
frequency component. The lowest frequency component is called fundamental and the
multiples of the lowest frequency component is called harmonics.
 In order to preserve higher rising edge and signal we will have to preserve more harmonics of
the signal as it propagates.

 The electric signals are electromagnetic wave and their speed of propagation depends upon the
dielectric constant of the material surrounding it.

 A serpentine routing to add intentional delay. Note that the traces are too close. If the adjacent
traces in the serpentine delay are very close, there is coupling between traces, a good AC return
path, so signal travels faster. If the trace is far off, the signal speed is close to that of straight
line.

 Clocks to PCI devices are usually generated from a clock multiplier. In motherboard designs,
there is additional clock delay on PCI add on card to keep the trace length matched. It is usually
2.5” on the PCI add-on card, so motherboard trace length is less than 2.5’.
 ISI (Inter Symbol Interference): If the transitions are in quick successions, the amplitudes are
smaller. When the transition pattern is like 1010101, the signal in not able to rise to its full
value. The signal may also not rise to its full amplitude, if the signal passes though capacitive
loads. The signal starts to rise slowly and before it could rise to full amplitude, the signal starts
to fall. This keeps happening if the signal switches fast in 101010 like pattern.

 Resistance of a conductor:

 In standard mounting conditions, resistors act as tiny inductors. Inductance is larger if the loop
area between the upper metalized layer and the ground plane is large. To minimize loop area,
sometimes RF engineers mount the resistors upside down. Further, on normal mounting
position, forms small capacitance between upper metallic and GND plane. Larger pad size,
smaller top layer to GND layer separation increases parasitic capacitance. This can be ignored
for most devices under 1GHz.
 If W is the amount of work done in moving the charge q, then the potential difference V is given
by: V=W/q
 Capacitance between high speed signal path, distort the signal. This can be formed by a via, a
thick trace at card edge connector, SMD pad, BGA pad or via.
 Real capacitor:

 At high frequencies we cannot say capacitor is a short, really 2πfL dominates than 1/(2πfC), such
that at high frequency the low impedance AC path to GND plane no more applies. So choose
capacitors with low parasitic inductance.
 Capacitance of a unit length coaxial cable:

 The capacitance per unit length of the microstrip increases with increase in trace width,
decrease with increase in distance between trace and GND plane, increase with the dielectric
constant of the material between the trace and the GND plane.
 Usually microstrip on the top layer is covered with solder mask, so the effective dielectric
constant increases, so capacitance increases.
 Fringe effect extends the area of the overlap, so the effective capacitance in parallel plate
capacitor is typically higher than calculated. If we join 2 parallel plate capacitors, so that their
area of overlap doubles, the resulting capacitance is less than twice due to the fringe effect.
 If 2 structures are joined, their resulting capacitance with respect to GND is less than the sum
of the capacitances of the individual structures with respect to GND.
 In high speed signals, via’s act as capacitance and degrades the signal performance. The extent
of degradation will depend upon the rise time of the signal.
 Via pad diameter is usually 10mil larger than the via hole. Capacitance of the via increases with
the increase in via pad size, with increase in drill size, also increases with number of power and
GND planes internal, by stripping off the inner layer pads. A typical PCB via has a capacitance of
0.30 pF.
 Via’s used to route power signals can have bigger pad size and drill holes, which provides
additional capacitance.
 Every wire carrying current produces magnetic field around it. Magnetic field generates a total
magnetic flux, it is defined as the total sum of the magnetic field and the surface area. Magnetic
field lines are closer near to the wire and sparse when away from the wire. The number of
magnetic field lines will depend upon the current being carried in the wire.
 Inductance is defined as the number of magnetic line loops per unit of current flowing in the
wire. L=N/I (Weber/Ampere).
 If we want to reduce inductance, increasing radius is not best way, reducing length is the best
way.

 If there are M magnetic line of loop encircled in the first wire due to the current I flowing in the
second wire, the mutual inductance is LM=M/I.
 Faraday’s law of electromagnetic induction: If the number of magnetic lines of loops across an
inductor changes, it induces a voltage across it.
 Number of magnetic lines of loop changes by ∆N in a time period ∆t, the voltage induced across
the inductor is; L=∆N/∆t.
 Lenz’s Law: The direction of voltage is such that, it opposes the change in current.

 Magnetic lines of loop around a wire due to carrying current, there is also magnetic lines of loop
due to the return path. The direction of these 2 loops are in the opposite direction. So the closer
they are, the smaller, magnetic lines of loop. The smaller the net change in the magnetic lines of
loop means smaller induced voltage.
 Keep the high speed signals close to the power and GND planes, keeps the electromagnetic
signals tightly coupled, so less cross talk. Striplining high speed signals, reduces cross talk and
shields any potential radiation.
 In 6 layer board, stack up: SIG 1/GND/SIG 2/SIG 3/POW/SIG 4. Route SIG 2 and SIG 3 in
orthogonal manner to avoid potential cross talk. To have a good coupling between PWR and
GND planes, to have a low AC path for the high frequency noise and signals, we can try to keep
it close together, stack up: SIG 1/SIG 2/GND/PWR/SIG 3/SIG 4. Problem: SIG 1 & 4 cannot have
direct access to the power planes, so no way to have controlled impedance.
 Flooding planes provides good capacitance, in turn reduces power supply noises.
 A typical 8 layer board addresses most of the SI issues, stack up: SIG 1/GND/SIG
2/POW/GND/SIG 3/POW/SIG 4, but there isn’t enough POW to GND capacitance, so can try
stack up: SIG 1/GND/POW/SIG 2/SIG 3/GND/POW/SIG 4, by keeping the spacing between SIG 2
& SIG 3 layer large, we can avoid cross talk.
 We should try to keep the stack-up symmetrical, if the second layer from the top is GND, then
the second layer from bottom should be GND as well, this is for mechanical requirements, to
avoid warping.
 Voltage drop across the trace is given by: R= (6.787*10-7)/WT (ohms/inch)
o W – width of the trace in inches
o T – thickness of the trace in inches
o Simplicity temperature dependency is removed, assuming 20C.
 Minimizing voltage drop:
o Keep the trace wider.
o Length of the trace should be as small as possible.
o Thickness of the trace should be as large as possible.
 If the current taken by the load varies, and the wire that connects the load with the source (V)
has some inductance L. The change in current dI/dt, because of the current taken by the load
causes some drop in voltage L*(dI/dt) across the inductor. So the voltage at the load is: V1 = V-
L*(dI/dt).
 If we have a de-coupling capacitor, it provides a low AC path to GND, thereby reducing the
noise/fluctuations in voltage. Z = 1/2πfC. So higher the capacitor lower the impedance.
Capacitor value can be chosen by:
o Estimating the maximum change in load current.
o Calculate the maximum allowable ripple in the supply.
o Calculate the required impedance by dV/dI.
o Find the value of the capacitor with lower impedance than the above value.
 Calculation steps:
o Find the inductance of the trace: ZL - 2πfL.
o What is the ripple voltage that is acceptable?
o Find the maximum impedance that can be tolerated: Zx – dV/dI.
o Then we can calculate the frequency below which we don’t need de-coupling caps: 2πfL
= dV/dI. Thereby finding the frequency.
o We know Zx, so we can always find capacitor with impedance less than that, Zc – 1/2πfC.
 Inductance of a power supply wire: L – 10.16 X ln (2H/D), where:
o X – Length of wire in inches,
o H – average separation between the wires,
o D – wire diameter,
o L – inductance in nH
 dI can also be calculated by: dI – N*C*V/T, where,
o N – number of gates
o C – capacitance
o V – voltage
o T – time
 How low should the impedance be? It depends on the maximum swing in current.
 In case the frequency of the noise is low, the drop across the power supply wiring inductor is so
low that we do not need to worry about it at all.
 When the frequency of the noise element increases, the effective AC impedance of the
capacitor taking into account, its series inductance increases. The capacitor is no more able to
shunt the AC noise to ground. To overcome this problem, we use a number of small capacitors.
The equivalent inductance of the n capacitors is 1/nth the inductance of one capacitors.
 The capacitors are placed really close to the power supply pins of IC’s to keep the inductance of
the trace from capacitor to the IC pin very low.
 With the equivalent capacitance, equivalent ESR and equivalent inductance, we can find the
impedance of each capacitor by: Z = R2+(2πfL-(1/2πfC))2
 If the power and GND planes are routed adjacent to each other, they act as a parallel plate
capacitance. Since there is no lead, they do not suffer from effective series inductance as in
normal capacitors.
 The capacitnce of a parallel plate capacitor is given by: C=ε0εrA/d. Where,
o ε0 – 8.87*10-12 Nm2/C2
o εr – relative permeability of the dielectric
o A – area formed by the power and GND plane
o d – separation between power and GND planes
 The above formula can be represented in inches by: C = 0.225εrA/d

 The impedance of a capacitor is given by Xc= 1/ 2*pi*fc Where,


o XC = Impedance in Ohms,
o f = frequency,
o C = Capacitance in Farad
 Now XC is very low if the frequency f is high and/or C is high. As an example, if C = 0.1µF and f =
100 MHz, then Xc= 1/(2*pi*100*10e6*0.1*10e-6) XC = 0.016 Ohms
This is indeed very low impedance. It will essentially mean that if 100 MHz noise is present at
power rail it should get shorted to ground by the low impedance path.
 If there are n inductors, each of inductance L are connected in parallel, their equivalent
inductance Leq is given by: Leq = L/n. Capacitors are connected in parallel Ceq is given by: Ceq =
n*C.
Z = 1/nR2+(2πfL-(1/2πfC))2