You are on page 1of 76

8 7 6 5 4 3 2 1

CK ENG
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD APPD
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. REV ZONE ECN DESCRIPTION OF CHANGE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ. DATE DATE

K36C MLB SCHEMATIC 02 691395 ENGINEERING RELEASED 04/09/09 ?

D APR/10/2009 D

(.csa) Date
(.csa) Date

Page Contents Page


TABLE_TABLEOFCONTENTS_HEAD
Contents
45 08/17/2008
TABLE_TABLEOFCONTENTS_HEAD

1
1
Table of Contents K36BH_MLB
08/22/2007
TABLE_TABLEOFCONTENTS_ITEM
38 SATA Connectors K36B_MLB
46 08/17/2008
TABLE_TABLEOFCONTENTS_ITEM

2
2
System Block Diagram K36B_MLB
08/17/2008
TABLE_TABLEOFCONTENTS_ITEM
39 External USB Connectors K36B_MLB
48 07/17/2008
TABLE_TABLEOFCONTENTS_ITEM

3
3
Power Block Diagram K36B_MLB
08/17/2008
TABLE_TABLEOFCONTENTS_ITEM
40 Front Flex Support K36B_MLB
49 08/17/2008
TABLE_TABLEOFCONTENTS_ITEM

4
4
CONFIGURATION OPTIONS K36B_MLB
08/17/2008
TABLE_TABLEOFCONTENTS_ITEM
41 SMC K36B_MLB
50 08/17/2008
TABLE_TABLEOFCONTENTS_ITEM

5
5
Revision History K36B_MLB TABLE_TABLEOFCONTENTS_ITEM
42 SMC Support K36B_MLB
51 08/17/2008
TABLE_TABLEOFCONTENTS_ITEM

6
6
JTAG Scan Chain K36B_MLB
08/17//2008
TABLE_TABLEOFCONTENTS_ITEM
43 LPC+SPI Debug Connector K36B_MLB
52 08/17/2008
TABLE_TABLEOFCONTENTS_ITEM

7
7
FUNC TEST K36B_MLB
08/17/2008
TABLE_TABLEOFCONTENTS_ITEM
44 SMBUS CONNECTIONS K36B_MLB
53 08/17/2008
TABLE_TABLEOFCONTENTS_ITEM

8
8
Power Aliases K36B_MLB TABLE_TABLEOFCONTENTS_ITEM
45 VOLTAGE SENSING K36B_MLB
54 08/17/2008
TABLE_TABLEOFCONTENTS_ITEM

9
9
SIGNAL ALIAS K36B_MLB TABLE_TABLEOFCONTENTS_ITEM
46 Current Sensing K36B_MLB
55 08/17/2008
TABLE_TABLEOFCONTENTS_ITEM

10
10
CPU FSB K36B_MLB
08/18/2008
TABLE_TABLEOFCONTENTS_ITEM
47 Thermal Sensors K36B_MLB
56 08/17/2008
TABLE_TABLEOFCONTENTS_ITEM

11
11
CPU Power & Ground K36B_MLB
08/17/2008
TABLE_TABLEOFCONTENTS_ITEM
48 Fan K36B_MLB
58 08/17/2008
TABLE_TABLEOFCONTENTS_ITEM

12
12
CPU Decoupling K36B_MLB
08/17/2008
TABLE_TABLEOFCONTENTS_ITEM
49 GEYSER K36B_MLB
59 08/17/2008

C
TABLE_TABLEOFCONTENTS_ITEM

13
13
eXtended Debug Port(MiniXDP) M99_MLB
01/08/2008
TABLE_TABLEOFCONTENTS_ITEM
50
61
SMS K36B_MLB
081/17/2008
C
TABLE_TABLEOFCONTENTS_ITEM

14
14
MCP CPU Interface K36B_MLB
08/17/2008
TABLE_TABLEOFCONTENTS_ITEM
51 SPI ROM K36B_MLB
62 08/29/2008
TABLE_TABLEOFCONTENTS_ITEM

15
15
MCP Memory Interface K36B_MLB
08/17/2008
TABLE_TABLEOFCONTENTS_ITEM
52 AUDIO: CODEC K36A_MLB
66 08/29/2008
TABLE_TABLEOFCONTENTS_ITEM

16
16
MCP Memory Misc K36B_MLB
08/17/2008
TABLE_TABLEOFCONTENTS_ITEM
53 AUDI0: SPEAKER AMP K36A_MLB
67 08/29/2008
TABLE_TABLEOFCONTENTS_ITEM

17
17
MCP PCIe Interfaces K36B_MLB
08/17/2008
TABLE_TABLEOFCONTENTS_ITEM
54 AUDIO: JACK K36A_MLB
68 08/29/2008
TABLE_TABLEOFCONTENTS_ITEM

18
18
MCP Ethernet & Graphics K36B_MLB
08/17/2008
TABLE_TABLEOFCONTENTS_ITEM
55 AUDIO: JACK TRANSLATORS K36A_MLB
69 08/17/2008
TABLE_TABLEOFCONTENTS_ITEM

19
19
MCP PCI & LPC K36B_MLB
08/17/2008
TABLE_TABLEOFCONTENTS_ITEM
56 DC-In & Battery Connectors RAYMOND
70 08/17/2008
TABLE_TABLEOFCONTENTS_ITEM

20
20
MCP SATA & USB K36B_MLB
08/17/2008
TABLE_TABLEOFCONTENTS_ITEM
57 PBUS Supply/Battery Charger K36B_MLB
72 08/17/2008
TABLE_TABLEOFCONTENTS_ITEM

21
21
MCP HDA & MISC K36B_MLB
08/17/2008
TABLE_TABLEOFCONTENTS_ITEM
58 5V/3.3V SUPPLY K36B_MLB
73 08/17/2008
TABLE_TABLEOFCONTENTS_ITEM

22
22
MCP Power & Ground K36B_MLB
08/17/2008
TABLE_TABLEOFCONTENTS_ITEM
59 1.8V/0.9V DDR2 SUPPLY K36B_MLB
74 08/17/2008
TABLE_TABLEOFCONTENTS_ITEM

23
24
MCP79 A01 Silicon Support K36B_MLB
08/17/2008
TABLE_TABLEOFCONTENTS_ITEM
60 IMVP6 CPU VCore Regulator K36B_MLB
75 08/17/2008
TABLE_TABLEOFCONTENTS_ITEM

24
25
MCP Standard Decoupling K36B_MLB
08/17/2008
TABLE_TABLEOFCONTENTS_ITEM
61 MCP VCORE REGULATOR K36B_MLB
76 08/17/2008
TABLE_TABLEOFCONTENTS_ITEM

25
26
MCP Graphics Support K36B_MLB
08/17/2008
TABLE_TABLEOFCONTENTS_ITEM
62 CPU VTT(1.05V) SUPPLY K36B_MLB
77 08/17/2008
TABLE_TABLEOFCONTENTS_ITEM

26
28
SB Misc K36B_MLB
08/17/2008
TABLE_TABLEOFCONTENTS_ITEM
63 MISC POWER SUPPLIES K36B_MLB
78 08/17/2008
TABLE_TABLEOFCONTENTS_ITEM

27
29
FSB/DDR2 VREF MARGINING K36B_MLB
08/17/2008
TABLE_TABLEOFCONTENTS_ITEM
64 POWER SEQUENCING K36B_MLB
79 08/17/2008
TABLE_TABLEOFCONTENTS_ITEM

28
31
DDR2 SO-DIMM Connector A K36B_MLB
08/17/2008
TABLE_TABLEOFCONTENTS_ITEM
65 POWER FETS K36B_MLB
90 08/17/2008
TABLE_TABLEOFCONTENTS_ITEM

29
32
DDR2 SO-DIMM Connector B K36B_MLB
08/17/2008
TABLE_TABLEOFCONTENTS_ITEM
66 INVERTER,LVDS K36B_MLB
93 08/17/2008
TABLE_TABLEOFCONTENTS_ITEM

30
33
Memory Active Termination
08/17/2008
67 TMDS ALIASES K36B_MLB

B TABLE_TABLEOFCONTENTS_ITEM

31
34
Right Clutch Connector
K36B_MLB

K36B_MLB
08/17/2008
TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM
68
94
MINI-DVI CONNECTOR K36B_MLB
08/17/2008
B
100 08/17/2008
TABLE_TABLEOFCONTENTS_ITEM

32
37
Ethernet PHY (RTL8211CL) SUMA
03/20/2008
TABLE_TABLEOFCONTENTS_ITEM
69 CPU/FSB Constraints K36B_MLB
101 08/17/2008
TABLE_TABLEOFCONTENTS_ITEM

33
38
Ethernet & AirPort Support SUMA
04/04/2008
TABLE_TABLEOFCONTENTS_ITEM
70 Memory Constraints K36B_MLB
102 08/17/2008
TABLE_TABLEOFCONTENTS_ITEM

34
39
ETHERNET CONNECTOR SUMA
04/04/2008
TABLE_TABLEOFCONTENTS_ITEM
71 MCP Constraints 1 K36B_MLB
103 08/17/2008
TABLE_TABLEOFCONTENTS_ITEM

35
41
FireWire LLC/PHY(FW643E) K36B_MLB
08/17/2008
TABLE_TABLEOFCONTENTS_ITEM
72 MCP Constraints 2 K36B_MLB
104 08/17/2008
TABLE_TABLEOFCONTENTS_ITEM

36
42
FireWire Port Power K36B_MLB
08/17/2008
TABLE_TABLEOFCONTENTS_ITEM
73 Ethernet Constraints K36B_MLB
105 08/17/2008
TABLE_TABLEOFCONTENTS_ITEM

37
43
FireWire Ports K36B_MLB
(MASTER)
TABLE_TABLEOFCONTENTS_ITEM
74 FireWire Constraints K36B_MLB
106 08/17/2008
TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM
75 SMC Constraints K36B_MLB
109 08/17/2008

TABLE_TABLEOFCONTENTS_ITEM
76 K36B RULE DEFINITIONS K36B_MLB

DIMENSIONS ARE IN MILLIMETERS

METRIC APPLE INC.


XX

A X.XX
DRAFTER DESIGN CK NOTICE OF PROPRIETARY PROPERTY A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
X.XXX PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
ENG APPD MFG APPD
Schematic / PCB #’s ANGLES
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
QA APPD DESIGNER TITLE
DO NOT SCALE DRAWING
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
051-8089 1 SCHEM,MLB,K36C SCH CRITICAL
RELEASE SCALE
NONE
SCHEM,MLB,K36C
820-2496 1 PCBF,MLB,K36B PCB CRITICAL
SIZE DRAWING NUMBER REV.
MATERIAL/FINISH
051-8089 02
THIRD ANGLE PROJECTION
NOTED AS
APPLICABLE
D SHT 1 OF 109

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U1000

J1300

INTEL CPU
XDP CONN
2.X OR 3.X GHZ
PG 12

PENRYN

PG 9

FSB

D 64-Bit
J6950
D
800/1067/1333 MHz

DC/BATT POWER SUPPLY


PG 13

J3100,3200 PG 60

MAIN
GPIOs FSB INTERFACE
MEMORY 2 UDIMMs
DDR2-800MHZ DIMM
PG 14 J5520

PG 25,26

TEMP SENSOR

PG 41
Misc
CLK
PG 24
U6100
SYNTH POWER SENSE
PG 45
SPI
J4501 Boot ROM J5601

SATA SPI FAN CONN AND CONTROL


PG 52 PG 48,49
Conn 3GHZ. PG 20

PG 38
HD
J4500 NVIDIA U4900
B,0 BSB ADC Fan Ser
SATA J5100

Conn 3GHZ. SATA MCP79 SMC Prt


LPC Conn
PG 38 PG 19 LPC Port80,serial
C ODD
PG 18
PG 41
PG 43 C
U1400

J9001

LVDS PWR

CONN LVDS OUT CTRL

PG 71
RGB OUT

J4810 J5800 J4501 J9001 J4600,4601

DP OUT TRACKPAD/ EXTERNAL


J9401
Bluetooth IR CAMERA
KEYBOARD USB
HDMI OUT Connectors
PG 40 PG 40 PG 40 PG 40
MINI DVI PG 39

CONN DVI OUT

(UP TO 12 DEVICES)

9
8
TMDS OUT
PG 71

7
USB
PG 19
PG 17

6
5
4
3
2
UP TO 20 LANES3

1
0
PCI-E
PG 16

B B
SMB
PG 20 SMB
CONN
RGMII PCI HDA PG 44
(UP TO FOUR PORTS) DIMM’s
PG 17
PG 18 PG 20

U6200

U4100 Audio

PCI-E Codec
FIREWIRE PG 53
FW643E
PG 35

J4300
U3700
U6801 U6801 U6610,6620,6630 System Block Diagram
A FW PORT GB
E-NET
HEADPHONE Line Out Speaker
SYNC_MASTER=K36B_MLB

NOTICE OF PROPRIETARY PROPERTY


SYNC_DATE=08/17/2008
A
Conn Amp Amp Amps
88E1116
PG 37 PG 55 PG 56 PG 57 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PG 31 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
J3400 J3900 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
MINI PCI-E J6800,6801,6802,6803
E-NET
AirPort Audio SIZE DRAWING NUMBER REV.
Conn
PG 28
PG 33
Conns D 051-8089 02

PG 59
APPLE INC. SCALE SHT OF
NONE 2 109

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

K36B POWER SYSTEM ARCHITECTURE D6905


02
PPVIN_G3H_P3V42G3H SHDN*
3.425V G3HOT PP3V42_G3H_REG
03 SMC PWRGD 04
D6905 PBUS_VSENSE VIN LT3470 VOUT RN5VD30A-F SMC_RESET_L
U6990 U5000
7A FUSE V Q5315
D 01 PPVBAT_G3H_CHGR_REG PPBUS_G3H D
02 22
VIN
CPUVTTS0_EN PPCPUVTT_S0_REG
EN_PSV VOUT
CHGR_EN (S0) (8A MAX CURRENT)
(S5)
CPUVTT 09-1
(1.05V) R7955 PWRBTN*
6A FUSE ENABLES PP1V05_S0_FET
AC DCIN(16.5V) TPS51117 MCP79
ADAPTER
IN
A VIN
VOUT
U5403 U7600
LPC_RESET0* LPC_RESET_L
29-1
SMC_BATT_ISENSE PGOOD
RSMRST*
PBUS SUPPLY/
SMC_DCIN_ISENSE
BATTERY CHARGER A CPUVTTS0_PGOOD
CPUPWRGD
30
CPU_PWRGD
ISL6258A SMC_CPU_VSENSE
U7000 01 02 CPU VCORE
V MCP_PS_PWRGD PS_PWRGD
29
J6950 VIN
VOUT A SMC_CPU_ISENSE
PPVCORE_S0_CPU_REG
(44A MAX CURRENT)
26
U2850
CPU_RESET#
U1400
ISL9504B
IMVP_VR_ON VR_ON
3S2P Q7050
BATT_POS_F PPVBAT_G3H_CHGR_OUT PGOOD VR_PWRGOOD_DELAY 28
(9 TO 12.6V) 25 U7400
C CPU C
CHGR_BGATE PPBUS_G3H 4.6V AUDIO PWRGOOD
IN MAX8902A PP4V6_AUDIO_ANALOG
1.05V (S5) U6201
EN OVT RESET*
EN
TPS62510
07 PP1V05_S5_REG U1000
MCP79 11 11-1
PVIN U7750
VOUT
08 32
P3V3S3_EN RC P1V05_S5_EN PG
PM_SLP_S4_L DELAY
02 P1V05_S5_PGOOD
09
SMC P16

SLP_S3# 15 U4900 04-1 Q7800 ENTRIP1


VIN
5V PP5VRT_S0_REG PP5VLT_S3_REG
11-3
EN1
(RT)
VOUT1
(4A MAX CURRENT)
17
U1400 RC DDRREG_EN P60
SMC_PM_G2_EN
(S5) PP3V3_S5_REG PP3V3_S5
DELAY
ENTRIP2 VOUT2
(4A MAX CURRENT)
06
RC EN2 3.3V
PCI_RESET0# DELAY Q7910
TPS51125
05 PP3V3_S3_FET
31
U7200 13
RC 11-2 P5VLTS3_EN PGOOD VREG3
11-1
DELAY
P3V3S3_EN
P5V3V3_PGOOD

Q7930 SMC 10
18 24 PM_RSMRST_L
B PP3V3_S0_FET ALL_SYS_PWRGD
RSMRST_OUT(P15)
PWRGD(P12) 99ms DLY
B
IMVP_VR_ON
15 09-1
RSMRST_PWRGD
IMVP_VR_ON(P16) 25
RSMRST_IN(P13)
Q3805 P3V3S0_EN
PM_SLP_S3_L 1.5V (S0) SMC_LRESET_L
SMC_ONOFF_L
PVIN Q3810 PWR_BUTTON(P90)
PM_WLAN_EN_L
16 16-3 TPS62510
PP1V5_S0_FET
19-1
P3V3_ENET_FET P17(BTN_OUT) PM_PWRBTN_L
P1V5S0_EN EN U7740 VOUT
RST* SMC_RESET_L
P1V5_S0_PGOOD
P3V3ENET_EN_L
P5V3V3_PGOOD SLP_S5_L
Q3805 SLP_S5_L(P95)
MCPCORES0_PGOOD SLP_S4_L
AP_PWR_EN P1V5_S0_PGOOD SLP_S4_L(P94)
PP1V8_S0_FET
1.8V S0 PP1V8_S0_REG
21 CPUVTTS0_PGOOD SLP_S3_L
SMC_ADAPTER_EN FL7700 P5V_LT_S3_PGOOD
SLP_S3_L(P93)
04-1
02 S3 TO S0
S0PGOOD_PWROK U4900
FETS PP1V5_S0_FET R5490 PP1V5_S0
21

=DDRREG_EN
VIN
1.8V PP1V8_S3_REG
14 (Q7901 & Q7971)
S5 VOUT1
(12A MAX CURRENT) RST*
PM_SLP_S3_L =DDRVTT_EN
S3 0.9V VOUT2 PP3V3_S0 SEL
PP0V9_S0_REG
(1A MAX CURRENT) PP1V8_S0 ADJ1 Power Block Diagram
RC P1V5S0_EN 16-2 TPS51116 PP1V05_S0
16-3 ADJ2 LTC2909 SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008
A DELAY P1V05S0_EN
(S0)
U7300 A
MCPDDR_EN PPVCORE_S0_MCP_REG_R R5490 20 U7870 NOTICE OF PROPRIETARY PROPERTY
RC 16-2 MCP_CORE PPVCORE_S0_MCP THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
DELAY 16-2 P3V3S0_EN MCPCORES0_EN VOUT2 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
EN2 (23A MAX CURRENT) AGREES TO THE FOLLOWING
(S0) I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

CPUVTTS0_EN PP5VLT_S3 12 II NOT TO REPRODUCE OR COPY IT


RC
DELAY 16-3 PBUSVSENS_EN 16-2 11-2 P5VLTS3_EN EN1
5V (LT)
VOUT1
PP5VLT_S3_REG
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

(S0) (4.5A MAX CURRENT) SIZE DRAWING NUMBER REV.


PGOOD1 PP5V_LT_S3_PGOOD
RC MCPCORES0_EN P5VRTS0_EN_L 16-1 VIN
SN0802043 D 051-8089 02

DELAY 16-4 (S0) U7500 MCPCORES0_PGOOD APPLE INC.


02 PGOOD2
SCALE
NONE
SHT
3
OF
109

8 7 6 5 4 3 2 1
PAGE_BORDER=TRUE

8 7 6 5 4 3 2 1
Page Notes
Power aliases required by this page:
(NONE)
Signal aliases required by this page:
(NONE)
BOM options provided by this page:
(NONE)

D D

BOM OPTION ALTERNATES OPTION


TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION TABLE_ALT_HEAD

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:


TABLE_5_ITEM

PART NUMBER
341S2420 1 IC,SMC,HS8/2117,9X9MM,TLP,HF,BLANK U4900 CRITICAL SMC_PROG TABLE_ALT_ITEM

TABLE_5_ITEM

128S0093 128S0218 ALL ALTERNATE PER CYNDI


341S2418 1 IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP U6100 CRITICAL BOOTROM_PROG TABLE_ALT_ITEM

TABLE_5_ITEM

152S0694 152S0138 ALL ALTERNATE PER CYNDI


341S2093 1 IC, CYPRESS, CY7C63833 U4800 CRITICAL TABLE_ALT_ITEM

TABLE_5_ITEM

152S0847 152S0586 ALL ALTERNATE PER CYNDI


338S0654 1 IC,FW643E,1394B PHY/OHCI LINK/PCI-E,127 U4100 CRITICAL TABLE_ALT_ITEM

152S0874 152S0516 ALL ALTERNATE PER CYNDI


TABLE_ALT_ITEM

152S0796 152S0685 ALL ALTERNATE PER CYNDI


TABLE_5_HEAD
TABLE_ALT_ITEM

C PART#

826-4393
QTY

1
DESCRIPTION

LBL,P/N LABEL,PCB,28MMX6MM
REFERENCE DESIGNATOR(S)

[EEE:3TN]
CRITICAL

CRITICAL
BOM OPTION
TABLE_5_ITEM
152S0778

157S0058
152S0693

157S0055
ALL

ALL
ALTERNATE PER CYNDI

ALTERNATE PER CYNDI


TABLE_ALT_ITEM
C

TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION


TABLE_5_ITEM

TABLE_5_HEAD

337S3769 1 PDC,SLGVT,2.26,25W,1066,R0,3M,BGA,P7750 U1000 CRITICAL PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
TABLE_5_ITEM

514-0665 1 CONN,RCPT,MINI-DVI,32P,R/A J9401 CRITICAL


TABLE_5_ITEM

TABLE_5_HEAD 514-0666 1 CONN,RCPT,3.5MM AUDIO IN,R/A J6750 CRITICAL


PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION TABLE_5_ITEM

TABLE_5_ITEM
514-0667 1 CONN,RCPT,3.5MM AUDIO OUT,R/A J6700 CRITICAL
338S0702 1 IC,GMCP,MCP79,35X35MM,BGA1437,B03 U1400 CRITICAL TABLE_5_ITEM

514-0668 1 CONN,RCPT,RJ45,NO FILTER,8P J3900 CRITICAL


TABLE_5_ITEM

514-0669 1 CONN,RCPT,USB,4P,MIDPLANE J4600 CRITICAL


TABLE_5_HEAD
TABLE_5_ITEM

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION 514-0669 1 CONN,RCPT,USB,4P,MIDPLANE J4601 CRITICAL
TABLE_5_ITEM

338S0694 1 IC,RTL8251CA-VB-GR,GIGE TRANSCEIVER,48P U3700 CRITICAL

B B
BOARD STACK-UP AND CONSTRUCTION
Top SIGNAL
2 GROUND
3 SIGNAL(High Speed)
4 SIGNAL(High Speed)
5 GROUND
6 POWER
7 POWER
8 GROUND CONFIGURATION OPTIONS
A 9 SIGNAL(High Speed) SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008
NOTICE OF PROPRIETARY PROPERTY
A
10 SIGNAL(High Speed) THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

11 GROUND I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
BOTTOM SIGNAL SIZE DRAWING NUMBER REV.

D 051-8089 02

APPLE INC. SCALE SHT OF


NONE 4 109

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Revision History
*****2008/08/21*****
PAGE 61:
- U7500 PIN V5DRV1 LINK TO PP5V_S0_MCPREG_VCC. *****2008/08/25***** *****2008/10/31*****
- U7500 PIN TONSEL LINK TO GND DIRECTLY. CHANGE CSA BASE ON WILL’S SUGGESTION. PAGE 41:
PAGE 9: - U4100 CHANGE FROM 338S0523 TO 338S0654
PAGE 64:
- ADD GMUX_JTAG_TMS AND GMUX_JTAG_TDI IN MISC NC MCP79 ALIASES.
- R7859 CHANGE TO 100 OHM.
PAGE 18: *****2008/11/01*****
- R7879 CHANGE TO 100K OHM. - NETNAME ENET_INTR_L CHANGE TO TP_ENET_INTR_L.
PAGE 65: PAGE 4:
- ENET_PWRDWN_L CHANGE TO TP_ENET_PWRDWN_L - BOM change U1400 CHANGE FROM 338S0678 TO 338S0702
- DELETE 1.05V S0 FET CIRCUIT. PAGE 19:
PAGE 57: *****2008/11/05*****
D - R7011 CHANGE TO 9.31K OHM, 1%
- DELETE R1987,R1988,R1995,R1970,R1971,R1972,R1973,R1996,R1997,R1998,R1999,R1978,R1979
(FOLLOW M97 DESIGN).
PAGE 62:
- C6210 CHANGE FROM 127S0062 TO 127S0108
D
*****2008/08/22***** - NET DPMUX_LOWPWR_L SYNC M97 NETNAME AUD_IPHS_SWITCH_EN PAGE 68:
PAGE 7: - NET LVDSMUX_SEL_IG_L SYNC M97 NETNAME - C6832, C6833 CHANGE FROM 127S0062 TO 127S0108
- ADD SMC_EXCARD_PWR_EN TEST_POINT PAGE 45:
- NET DPMUX_SEL_IG_L SYNC M97 NETNAME - DELETE L4502, NET SATA_HDD_D2R_UF_P / SATA_HDD_D2R_UF_N
PAGE 8: PAGE 28:
- L4501 / Fl4520 / FL4525 CHANGE FROM 155S0303 TO 155S0371
- ADD =PP3V42_G3H_RTC_D LINK TO =PP3V42_G3H_REG - REMOVE NET DIMM_OVERTEMPA_L PAGE 102:
PAGE 14: PAGE 29: - DELETE PHYSICAL/SPACING SETTING OF SATA_HDD_D2R_UF_P / SATA_HDD_D2R_UF_N
- R1410 CHANGE TO 49.9 OHM - REMOVE NET DIMM_OVERTEMPA_L
- CHANGE R1440 TO 150_5% AND NO STUFF PAGE 42: *****2008/11/06*****
- ADD SMC_EXCARD_PWR_EN TO TP_SMC_EXCARD_PWR_EN - U5413 CHANGE FROM 353S1432 TO 353S2220
PAGE 26:
- ADD SMC_RSTGATE_L TO TP_SMC_RSTGATE_L - R7417 CHANGE FROM 5.36K(114S0289) TO 4.42K(114S0280)
- R2872 CHANGE TO 0OHM
- RTC FOLLOW M97 DESIGN AND USE SUPERCAP SOLUTION - ADD ALS_GAIN TO NC_ALS_GAIN *****2008/11/12*****
- ADD ESTARLDO_EN TO NC_ESTARLDO_EN - U1000 CHANGE FROM 373S3646 TO 373S3702
- MCP S0 PWRGD FOLLOW M97 DESIGN
PAGE 29: - ADD SMC_ANALOG_ID TO NC_SMC_ANALOG_ID
- ADD SMC_SYS_KBDLED TO NC_SMC_SYS_KBDLED *****2008/11/19*****
- PULL R3240 DOWN TO GND. PULL R3241 HIGH - J6950 CHANGE FROM 516S0620 TO 516S0735
PAGE 32,33,34 - ADD R5054 10KOHM LINK SMC_GPU_ISENSE PULL DOWN TO GND. - J9401 CHANGE FROM 514-0517 TO 514-0665
- FOLLOW M97 DESIGN - ADD R5055 10KOHM LINK SMC_NB_MISC_ISENSE PULL DOWN TO GND. - J6750 CHANGE FROM 514-0519 TO 514-0666
PAGE 39: PAGE 43:
- J6700 CHANGE FROM 514-0521 TO 514-0667
- R5142 CHANGE TO NO STUFF.
- D4600/D4601/PIN-6 CONNECT TO USB VBUS (FOLLOW M97D) - J3900 CHANGE FROM 514-0523 TO 514-0668
PAGE 46:
PAGE 44: - R5416 CHANGE TO 4.53K AND DELETE BOM OPTION. - J4600, J4601 CHANGE FROM 514-0527 TO 514-0669
- R5270/R5271 = 1K (FOLLOW M97D) - R5417 CHANGE TO 4.53K AND DELETE BOM OPTION. - U3700 CHANGE FROM 338S0570 TO 338S0694
- R5280/R5281 = 1K (FOLLOW M97D) - R5418 CHANGE TO 4.53K AND DELETE BOM OPTION. *****2008/11/26*****
PAGE 68: PAGE 57: - PAGE 61 NOTE : CORRECT REFERENCE TO R5164 AND R5144
- CHANGE C9411, C9412 TO 220PF - NETNAME FROM CHGR LOWCURRENT REF CHANGE TO CHGR_LOWCURRENT_REF
- J3400 CHANGE TO 516S0729
- NETNAME FROM CHGR LOWCURRENT GATE CHANGE TO CHGR_LOWCURRENT_GATE
- CHANGE R9462, R9463 TO 2.7KOHM PAGE :
- ADD C9480 0.1UF_16V_0402 FROM GND_CHASSIS_TMDS_DOWN TO GND - REMOVE R7884 AND C7884 *****2008/12/12*****
- R5144 and R5164 changed to 10K 5% 0402 (116S0090)
C - CHANGE R9460,R9461 TO 0OHM,
- CHANG C9442 AND C9443 TO 47PF
PAGE 66:
- REMOVE J9001 PIN 20 AND PIN21 NET. *****2008/12/17*****
C
- U4900 symbol update
*****2008/08/23***** *****2008/09/02*****
MODIFY ALL NOSTUFF TO NO STUFF. PAGE 45: *****2008/12/20*****
- CHANGE ODD CONNECTOR FROM 516S0720 TO 516S0719 - R5156, R5157, R5158 change from 0 to 33 ohm, 5%, 0402(116s0030)
PAGE 6:
- REMOVE ETHERNET CIRCUIT. *****2008/09/27*****
PAGE 8: PAGE 9:
- ADD =PP3V3_S5_P3V3ENETFET LINK TO PP3V3_S5 - ADD STANDOFF 860-0964 X 4
- ADD =PP1V05_ENET_PHY LINK TO PP1V2R1V05_ENET. - ADD STANDOFF 860-0723 X 1
PAGE 9: - ADD STANDOFF 860-0749 X 1
- ADD =RTL8211_ENSWRE LINK TO GND. PAGE 29:
- ADD =PP3V3_ENET_PHY_VDDREG LINK TO TP_PP3V3_ENET_PHY_VDDREG.
- REMOVE BOMOPTION TABLE OF R2903/R2905/R2909/R2911
- ADD =RTL8211_REGOUT LINK TO NC_RTL8211_REGOUT. PAGE 66:
- =P3V3ENET_EN_L LINK TO PM_SLP_RMGT_L
- C6601/C6603 CHANGE TO APN 128S0135, and REMOVE BOMOPTION OMIT
- =P1V05ENET_EN LINK TO PM_SLP_RMGT_L
- C6605 CHANGE TO APN 128s0148, HF APN 128s0221, and REMOVE BOMOPTION OMIT
PAGE 10: PAGE 68:
- CHANGE XDP_TDO_CONN TO XDP_TDO - C6830/C6831 CHANGE TO APN 128S0220, and REMOVE BOMOPTION OMIT
PAGE 13: PAGE 72:
- XDP FOLLOW M98 DESIGN. CONNECTOR FROM 516S0625 CHANGE TO 998-1571. - R7272 CHANGE FROM 57.6K 1%(114s0389) TO 75K 1%(114s0399)
PLAGE 23:
- DELETE R2400~R2413 FOR MCP A01 VERSION. *****2008/10/20*****
PAGE 31: PAGE 29:
- REMOVE R3400, R3401 - ADD R2903/R2905 BOMOTION AND CHANGE VALUE TO 200 OHM
- L3401 FROM NO STUFF CHANGE TO STUFF. PAGE 50:
PAGE 39 - REMOVE ALT TABLE
- DELETE R4699. PAGE 74:
- R4690 FROM NO STUFF CHANGE TO STUFF. - REMOVE ALT TABLE
PAGE 94:
PAGE 41:
- REMOVE K36 BOM OPTION TABLE AND ALT TABLE
- SMC_NB_DDR_ISENSE CHANGE TO SMC_MCP_DDR_ISENSE
- SMC_NB_CORE_ISENSE CHANGE TO SMC_MCP_CORE_ISENSE *****2008/10/22*****
PAGE 46: PAGE 12:
- SMC_NB_DDR_ISENSE CHANGE TO SMC_MCP_DDR_ISENSE
- C1200 ~ C1219 CHANGE TO 138S0580
B - SMC_NB_CORE_ISENSE CHANGE TO SMC_MCP_CORE_ISENSE
- R5417 ADD BOM OPTION FOR NO STUFF
- R5416 ADD BOM OPTION FOR NO STUFF
PAGE 28:
- C2870 CHANGE TO 138S0614 B
PAGE 37:
PAGE 50: - ADD R3731 (116s0026 22 ohm 5% 0402) FOR EMI 125MHZ NOISE
- ADD C5926 (10UF,20%.0603) TO =PP3V3_S3_SMS - TP_RTL8211_CLK125 CHANGE TO RTL8211_CLK125
PAGE 63: PAGE 48:
- REMOVE USB_PWR_EN_S3 - C4803 CHANGE TO 138S0614
PAGE 66: PAGE 66:
- REMOVE R9010, R9011 - C6605 CHANGE TO HF APN 128S0221
PAGE 70:
*****2008/08/24*****
- C7040/C7041/C7047 CHANGE TO 138S0614
PAGE 6: PAGE 90:
- R0602 BOMOPTION FROM JTAG_1DEV CHANGE TO NO STUFF. - L9002 CHANGE TO 116S0004(0ohm,5%,0402)
PAGE 13: - C9003 CHANGE TO 116S0004(0ohm,5%,0402)
- XDP FOLLOW M97 DESIGN. CONNECTOR FROM 998-1571 CHANGE TO 516S0625.
PAGE 18: *****2008/10/24*****
- R1860 AND R1861 CHANGE TO PAGE 68.
PAGE 19:
PAGE 25: - R1950/R1951/R1952/1953 CHANGE TO 116s0004 (0 OHM,5%,0402)
- C2504-C2507 FROM 138S0578(402) CHANGE TO 138S0614(402-1) PAGE 28:
- C2516-C2517 FROM 138S0578(402) CHANGE TO 138S0614(402-1) - R2825/R2826 CHANGE TO 116s0004 (0 OHM,5%,0402)
PAG3 35: PAGE 34:
- J3400 516S0635 CHANGE TO HF APN 516S0729
- R4150 FROM 118S0343 (0201) CHANGE TO 116S0056(0402) PAGE 52:
PAGE 58: - ADD C5250/C5251/C5270/C5271/C5260/C5261/C5280/C5281 131S1104 (22pF,5%,0402) NO STUFF
- C7281, C7241, C7272 FROM 138S0555(603) CHANGE TO 138S0615(603-1) - TEXT "ALS" CHANGE TO "MINI-PCIE"
- C7280, C7240 FROM 128S0092(POLY) CHANGE TO 128S0128(POLY-TANT)
- I2C_ALS_SCL CHANGE TO I2C_MINI_PCIE_SCL
- C7291, C7292, C7252, C7251 FROM 128S0115(POLY,CASE-B2) CHANGE TO
128S0222(POLY,CASE-B2-SM) - I2C_ALS_SDA CHANGE TO I2C_MINI_PCIE_SDA
- Q7260, Q7261 FROM 376S0512 CHANGE TO 376S0652 (H-F) PAGE 67:
PAGE 59: - J6700 514-0604 CHANGE TO HF APN 514-0521
- Q7320 FROM 376S0512 CHANGE TO 376S0652 (H-F) - J6750 514-0603 CHANGE TO HF APN 514-0519
- Q7321 FROM 376S0511 CHANGE TO 376S0651 (H-F) PAGE 69:
02
- C7321 FROM 128S0111(POLY) CHANGE TO 128S0218 (POLY,CASE-D2E-SM) - J6950 516S0620 CHANGE TO HF APN 516S0735
A - C7343 FROM 128S0073 CHANGE TO 128S0233.
PAGE 60: *****2008/10/25*****
SYNC_MASTER=K36B_MLB

NOTICE OF PROPRIETARY PROPERTY


A
- XW7400 ADD BOMOPTION OMIT. PAGE 52:
- Q7400, Q7402 FROM 376S0472 CHANGE TO 376S0617. - STUFF C5250/C5251/C5270/C5271/C5260/C5261/C5280/C5281
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PAGE 61: PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
*****2008/10/28***** AGREES TO THE FOLLOWING
- L7500 FROM 152S0869 CHANGE TO 152S0685.
PAGE 34: I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
- Q7500 FROM 376S0512 CHANGE TO 376S0652.
- J3400 516S0729 CHANGE TO 516S0635
- C7560 FROM 128S0092 CHANGE TO 128S0218. II NOT TO REPRODUCE OR COPY IT
PAGE 62: *****2008/10/30***** III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
- Q7620 FROM 376S0512 CHANGE TO 376S0652. PAGE 69:
- C7601 FROM 138S0578 CHANGE TO 138S0614. - J6950 516S0735 CHANGE TO 516S0620 SIZE DRAWING NUMBER REV.

D 051-8089 02

APPLE INC. SCALE SHT OF


NONE 5 109
NOTE: All page numbers are .csa, not PDF. See page 1 for .csa -> PDF mapping.
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D
1.05V TO 3.3V LEVEL TRANSLATOR (K36B: ON ICT FIXTURE)

=PP3V3_S0_XDP
13 8

13 12 11 10 8
=PP1V05_S0_CPU To XDP connector
From XDP connector U1000 and/or level translator
JTAG_ALLDEV JTAG_ALLDEV
XDP_TCK
CPU
1 C0601 1 C0602 69 13 10 7 6 IN
XDP_TDI XDP
0.1UF 0.1UF 69 13 10 7 IN
20% 20% 69 13 10 7 6 IN XDP_TMS R0603
2 10V
CERM 2 10V
CERM 0
402 402 69 13 10 7 6 IN XDP_TRST_L 69 10 XDP_TDO 1 2 XDP_TDO_CONN OUT 7 13

5%
1/16W
MF-LF
402 XDP connector
JTAG_ALLDEV
R06011
10K
5%
1/16W
MF-LF
402 2

11
1
From XDP connector
VCCA VCCB
U0600 or via level translator U1400
C 69 13 10 7 6 XDP_TCK 2
NLSV4T244
A1
UQFN
B1 10 JTAG_MCP_TCK MAKE_BASE=TRUE 7 13 21
MCP XDP
C
NO STUFF 3 A2 B2 9 JTAG_MCP_TDI MAKE_BASE=TRUE 7 13 21

R06021 69 13 10 7 6 XDP_TMS 4 A3 B3 8 JTAG_MCP_TMS MAKE_BASE=TRUE 7 13 21


R0604
JTAG_ALLDEV 0
0 69 13 10 7 6 XDP_TRST_L 5 A4 B4 7 JTAG_MCP_TRST_L 7 13 21 21 JTAG_MCP_TDO 1 2 JTAG_MCP_TDO_CONN OUT 7 13
5% MAKE_BASE=TRUE
1/16W 5%
MF-LF
402 2 JTAG_LVL_TRANS_EN_L 12 OE*
1/16W
MF-LF
402
XDP connector
GND
6

B B

JTAG Scan Chain


A SYNC_MASTER=K36B_MLB

NOTICE OF PROPRIETARY PROPERTY


SYNC_DATE=08/17//2008
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-8089 02

APPLE INC. SCALE SHT OF


NONE 6 109

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

Functional Test Points

#J5601 Fan Connectors # J4501 SATA HD System LED and IR #J1300 XDP # J5100 LPC+SPI Connector
TRUE PP3V42_G3H
D I12
I15
TRUE
TRUE
PP5VRT_S0
FAN_RT_PWM
7 8

48
I284

I283
TRUE
TRUE
SATA_HDD_R2D_P
SATA_HDD_R2D_N
38

38
71

71
I199

I198
TRUE
TRUE
XDP_BPM_L<5>
XDP_BPM_L<4>
10 13 69

10 13 69
I227

I228 TRUE PP5VRT_S0


7 8

7 8
D
TRUE FAN_RT_TACH 48 I282 TRUE SATA_HDD_D2R_C_N 38 71 TRUE XDP_BPM_L<3> 10 13 69 I226 TRUE LPC_AD<0> 19 41 43 72
I16 I196
TRUE GND I281 TRUE SATA_HDD_D2R_C_P 38 71
I197 TRUE XDP_BPM_L<2> 10 13 69 I225 TRUE LPC_AD<1> 19 41 43 72
I157
PP5V_S0_HDD_FLT Need 4 TP TRUE SPI_ALT_MOSI
I280 TRUE 38 TRUE XDP_BPM_L<1> 10 13 69 I224 43
#J6950 Battery/Lid Connector TRUE SYS_LED_ANODE_L 38
I195
TRUE XDP_BPM_L<0> 10 13 69 I223 TRUE SPI_ALT_MISO 43
I279 I193
TRUE LPC_FRAME_L
I285 TRUE SMC_BS_ALRT_L_F 56 I278 TRUE IR_RX_OUT 38 40
I194 TRUE TP_XDP_OBSFN_B0 13
I222
PM_CLKRUN_L
19 41 43 72

TRUE SMBUS_BATT_SCL_F 56 I277 TRUE PP5V_S3_IR_CONN 38 TRUE TP_XDP_OBSFN_B1 13 I221 TRUE 19 41 43


I286 I192
TRUE SMC_TMS
I288 TRUE SMBUS_BATT_SDA_F 56 I276 TRUE GND Need 4 TP
I191 TRUE TP_XDP_OBSDATA_B0 13 I219
DEBUG_RESET_L
41 42 43

TRUE PPVBAT_G3H_CONN_F 56 TRUE TP_XDP_OBSDATA_B1 13 I220 TRUE 26 43


I287 I190
TRUE SMC_LID_F #J3400 Airport TP_XDP_OBSDATA_B2 TRUE SMC_TDO 41 42 43
I289 56
I188 TRUE 13 I217
TRUE SMC_TRST_L
I291 TRUE GND_SMC_LID_F 56 I274 TRUE PCIE_WAKE_L 17 31
I189 TRUE TP_XDP_OBSDATA_B3 13 I218 41 43

TRUE SMC_MD1
I290 TRUE PP3V42_G3H_LIDSWITCH_F 56 I275 TRUE MINI_CLKREQ_L 17 31
I186 TRUE XDP_PWRGD 13 I216
SMC_TX_L
41 43

TRUE GND Need 6 TP I273 TRUE PCIE_CLK100M_MINI_N 17 31 71 TRUE XDP_OBS20 13 I215 TRUE 39 41 42 43
I292 I187
TRUE PCIE_CLK100M_MINI_P PM_LATRIGGER_L TRUE LPC_CLK33M_LPCPLUS 26 43 72
I272 17 31 71
TRUE 13 19 I214
#J6900 MagSafe DC Power Jack I271 TRUE PCIE_MINI_D2R_N 17 31 71
I185
TRUE JTAG_MCP_TCK 6 13 21 I213 TRUE LPC_AD<2> 19 41 43 72
I183
PCIE_MINI_D2R_P TRUE LPC_AD<3>
I294 TRUE PP18V5_DCIN_FUSE Need 2 TP 56 I269 TRUE 17 31 71
I184 TRUE SMBUS_MCP_0_DATA 13 21 44 72 I212 19 41 43 72

ADAPTER_SENSE TRUE PCIE_MINI_R2D_N TRUE SPIROM_USE_MLB 43


I293 TRUE 56 I270 31 71
I182 TRUE SMBUS_MCP_0_CLK 13 21 44 72 I211

TRUE PCIE_MINI_R2D_P XDP_TCK TRUE SPI_ALT_CLK


I295 TRUE GND Need 2 TP I267 31 71
I181 TRUE 6 10 13 69 I209 43

TRUE SPI_ALT_CS_L
I268 TRUE PP3V3_WLAN Need 4 TP 31 I180 TRUE PPCPUVTT_S0 7 8 I210 43

#J9000 INVERTER Connector I266 TRUE PP1V5_S0_R Need 3 TP 7 8 I178 TRUE PP3V3_S0 7 8 I207 TRUE LPC_SERIRQ 19 41 43

MINI_RESET JTAG_MCP_TDO_CONN TRUE LPC_PWRDWN_L


I297 TRUE PPBUS_ALL_INV_CONN Need 2 TP 66 I264 TRUE 31
I179 TRUE 6 13 I208 19 41 43

PP3V3_S3_AIRPORT_CONN TRUE SMC_TDI


I296 TRUE INV_GND 66 I265 TRUE 31 I177 TRUE JTAG_MCP_TRST_L 6 13 21 I206 41 42 43

TRUE I2C_MINI_PCIE_SCL TRUE MCP_DEBUG<0> TRUE SMC_TCK


I298 TRUE PP5V_INV_F 66 I263 31 44 I175 13 19 72 I203 41 42 43

TRUE I2C_MINI_PCIE_SDA MCP_DEBUG<1> TRUE SMC_RESET_L


I299 TRUE INV_BKLIGHT_PWM_L Need 4 TP 66 I262 31 44
I176 TRUE 13 19 72 I204 41 42 43

TRUE USB2_AIRPORT_N 31 72 TRUE MCP_DEBUG<2> 13 19 72 I205 TRUE SMC_NMI 41 43


I261 I173
#J9001 LCD + CAMERA CONNECTOR I259 TRUE USB2_AIRPORT_P 31 72 TRUE MCP_DEBUG<3> 13 19 72 I202 TRUE SMC_RX_L 39 41 42 43

C I300 TRUE PP3V3_LCDVDD_SW_F 66 I260 TRUE GND Need 6 TP


I174

I172 TRUE JTAG_MCP_TDI


JTAG_MCP_TMS
6 13 21 I201 TRUE
TRUE
LPCPLUS_GPIO
GND Need 2 TP
18 43 C
I301 TRUE PP3V3_S0_LCD_F 66 I171 TRUE 6 13 21 I200

TRUE LVDS_IG_DDC_CLK 18 66
# Other Func Test Points TRUE MCP_DEBUG<4> 13 19 72
I303 I170

I302 TRUE LVDS_IG_DDC_DATA 18 66 I258 TRUE ALL_SYS_PWRGD 26 41 64 I169 TRUE MCP_DEBUG<5> 13 19 72

TRUE LVDS_IG_A_DATA_N<0> 18 66 71 I256 TRUE PPVCORE_S0_CPU 8 I168 TRUE MCP_DEBUG<6> 13 19 72


I305
TRUE LVDS_IG_A_DATA_P<0> 18 66 71 I257 TRUE PPCPUVTT_S0 7 8 I167 TRUE MCP_DEBUG<7> 13 19 72
I304

I306 TRUE LVDS_IG_A_DATA_N<1> 18 66 71 I255 TRUE PPVCORE_S0_MCP_R 8 I165 TRUE FSB_CLK_ITP_P 13 14 69

I307 TRUE LVDS_IG_A_DATA_P<1> 18 66 71 I254 TRUE PPVCORE_S0_MCP 8 I166 TRUE FSB_CLK_ITP_N 13 14 69

LVDS_IG_A_DATA_N<2> TRUE PP0V9_S0 TRUE XDP_CPURST_L


I308 TRUE 18 66 71 I253 8 I163 13 69

I309 TRUE LVDS_IG_A_DATA_P<2> 18 66 71 I252 TRUE PP1V05_S0 7 8 I164 TRUE XDP_DBRESET_L 10 13 26

I310 TRUE LVDS_IG_A_CLK_F_N 66 I251 TRUE PP1V5_S0_R 7 8 I162 TRUE XDP_TDO_CONN 6 13

TRUE LVDS_IG_A_CLK_F_P 66 I250 TRUE PP1V8_S0 8 I161 TRUE XDP_TRST_L 6 10 13 69


I311

I313 TRUE USB2_CAMERA_CONN_P 66 72 I248 TRUE PP1V8_S0_R 8 I160 TRUE XDP_TDI 6 10 13 69

I312 TRUE USB2_CAMERA_CONN_N 66 72 I249 TRUE PP1V05_S0_MCP_PEX_AVDD 8 24


I159 TRUE XDP_TMS 6 10 13 69

I315 TRUE PP5V_S3_CAMERA_F 66 I246 TRUE PP1V05_S0 7 8


I158 TRUE GND Need 8 TP
I314 TRUE GND I247 TRUE PP1V05_S0_MCP_SATA_AVDD 8 24

I245 TRUE PP1V05_S0 7 8

# J6701 MIC CONNECTOR I244 TRUE PP5VRT_S0 7 8

I316 TRUE MIC_LO_CONN 54 I243 TRUE PP3V3_S0 7 8

I317 TRUE MIC_HI_CONN 54 I242 TRUE PP1V0_FW 8

I318 TRUE MIC_SHLD_CONN 54 55 I240 TRUE PP1V8_S3 8

I241 TRUE PP3V3_S3 8


#J6702 Left SPEAKER CONNECTOR I238 TRUE PP5VLT_S3 8

TRUE SPKRCONN_L_P_OUT 53 54 I239 TRUE PPVTT_S3_DDR_BUF 8


I319
TRUE SPKRCONN_L_N_OUT 53 54 I237 TRUE PP1V05_S5_REG 8
I320
I235 TRUE PP3V3_S5 8
#J6703 Right SUB SPEAKER CONNECTOR TRUE PP3V42_G3H
B I321 TRUE SPKRCONN_SUB_P_OUT 53 54
I236

I234 TRUE PP18V5_G3H


7 8

8
B
I322 TRUE SPKRCONN_SUB_N_OUT 53 54 I233 TRUE PPBUS_G3H 8

TRUE SPKRCONN_R_P_OUT 53 54 I232 TRUE PPBUS_G3H_CPU_ISNS 8


I323
SPKRCONN_R_N_OUT TRUE PP3V3_ENET_PHY
I324 TRUE 53 54 I230 8

I231 TRUE PP1V2R1V05_ENET 8


# J5800 GEYSER AND DIMM0 REMOTE TEMP SENSORS I229 TRUE PPVP_FW 8

I326 TRUE TPAD_GND_F 49

I325 TRUE CONN_TPAD_ONOFF_FLTR_L 49

I328 TRUE CONN_TPAD_USB_P 49 72

I327 TRUE CONN_TPAD_USB_N 49 72

I329 TRUE SMC_LID_LC 49

I330 TRUE PP5V_S3_TPAD_F 49

#J5520 CPU/MCP Thermal Sensor


I331 TRUE CPUTHMSNS_D2_P 47

I332 TRUE CPUTHMSNS_D2_N 47

I334 TRUE MCPTHMSNS_D2_P 47

I333 TRUE MCPTHMSNS_D2_N 47

#J4810 BLUETOOTH
I335 TRUE PP3V3_S3_BT_F_CONN 40

I336 TRUE USB2_BT_F_N_CONN 40 72

I337 TRUE USB2_BT_F_P_CONN 40 72

I338 TRUE GND_BT_F_CONN 40 FUNC TEST


A TRUE
#J4500 SATA ODD
SATA_ODD_R2D_UF_P 38 71 NOTICE OF PROPRIETARY PROPERTY
A
I340
I339 TRUE SATA_ODD_R2D_UF_N 38 71
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
I342 TRUE SATA_ODD_D2R_C_N 38 71 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I341 TRUE SATA_ODD_D2R_C_P 38 71
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
TRUE PP3V3_S0 Need 4 TP 7 8
I343 II NOT TO REPRODUCE OR COPY IT
I345 TRUE SMC_ODD_DETECT 38 41
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I344 TRUE GND Need 6 TP
SIZE DRAWING NUMBER REV.

D 051-8089 02

APPLE INC. SCALE SHT OF


NONE 7 109

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

"S0,S0M" RAILS "S3" RAILS 56 =PP3V42_G3H_REG


"G3H" RAILSPP3V42_G3H 7
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=3.42V
58 =PP5VRT_S0_REG PP5VRT_S0 7 59 =PP1V8_S3_REG PP1V8_S3 7 MAKE_BASE=TRUE
60 =PPVCORE_S0_CPU_REG PPVCORE_S0_CPU 7 MIN_LINE_WIDTH=0.30 MM MIN_LINE_WIDTH=1.5 mm
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.20 MM MIN_NECK_WIDTH=0.25 mm =PPVIN_S5_SMCVREF 42
(CPU VCORE PWR) MIN_NECK_WIDTH=0.3 MM VOLTAGE=5V VOLTAGE=1.8V
=PP3V42_G3H_SMBUS_SMC_BSA
VOLTAGE=0.9V MAKE_BASE=TRUE MAKE_BASE=TRUE 44
MAKE_BASE=TRUE
=PP5V_S0_HDD 38 =PP3V42_G3H_PWRCTL 64
=PPVCORE_S0_CPU 11 12
=PP5V_S0_LPCPLUS 43 =PP1V8_S3_P1V8S0FET 65 =PP3V42_G3H_CHGR 57
=PPVCORE_S0_CPU_VSENSE 45

D
=PP5V_S0_FAN_RT
=PP5V_S0_CPU_IMVP
48

60
=PP1V8_S3_MEM 28 29
=PP3V42_G3H_SMCUSBMUX
=PP3V42_G3H_LIDSWITCH
39

56
D
=PP5V_S0_ODD 38 =PP3V42_G3H_BMON_ISNS 46
65 21 =PP3V3_S3_FET PP3V3_S3 7
65 62 =PPCPUVTT_S0_REG PPCPUVTT_S0 7 =PP5V_S0_TMDS 68 MIN_LINE_WIDTH=0.6 mm =PP3V3_S5_SMC 41 42 50
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 MM =PP5V_S0_LCD 66 VOLTAGE=3.3V =PP3V3_S5_LPCPLUS 43
VOLTAGE=1.05V MAKE_BASE=TRUE
MAKE_BASE=TRUE =PP5V_S0_CPUVTTS0 62 =PP3V42_G3H_RTC_D 26
=PP3V3_S3_SMBUS_SMC_A_S3 44
=PP1V05_S0_CPU 6 10 11 12 13 =PP5V_S0_AUDIO 52 55
=PP3V3_S3_PDCISENS 59
=PP1V05_S0_MCP_FSB 14 22 24 =PP5V_S0_AUDIO_AMP 53
=PP3V3_S3_SMBUS_SMC_MGMT 44
=PP1V05_S0_SMC_LS 42 56 =PP18V5_DCIN_CONN PP18V5_G3H 7
=PP3V3_S3_VREFMRGN 27 MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.3 MM
=PP3V3_S3_WLAN 31 VOLTAGE=18.5V
MAKE_BASE=TRUE
=PP3V3_S3_AIRPORT_AUX 31
=PP18V5_G3H_CHGR 57
=PP3V3_S3_BT 40

=PP3V3_S3_SMS 50
57 =PPBUS_G3H PPBUS_G3H 7
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=12.6V
MAKE_BASE=TRUE
61 =PPMCPCORE_S0_REG PPVCORE_S0_MCP_R 7
MIN_LINE_WIDTH=0.6 MM
46 =PPVCORE_S0_MCP_REG_R MIN_NECK_WIDTH=0.2 MM =PPVIN_S0_MCPCORES0
VOLTAGE=1.05V 61
(MCP VCORE REG. OUTPUT) MAKE_BASE=TRUE =PPVIN_S0_MCPREG_VIN 61
=PPVCORE_S0_MCP_VSENSE 45
=PPVIN_S5_1V8S3_0V9S0 59

=PPVIN_S5_3V3S5 58

65 63 =PP3V3_S0_FET PP3V3_S0 7 =PPVIN_S0_5VRTS0 58


MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM =PPVIN_S3_5VLTS3 61
VOLTAGE=3.3V =PPBUS_G3HRS5
24 22 =PPVCORE_S0_MCP PPVCORE_S0_MCP 7 MAKE_BASE=TRUE 45
61 46 MIN_LINE_WIDTH=0.6 MM 61 =PP5VLT_S3_REG PP5VLT_S3 7
(MCP VCORE AFTER SENSE RES) MIN_NECK_WIDTH=0.2 MM =PP3V3_S0_XDP 6 13 MIN_LINE_WIDTH=0.6 MM =PPBUS_S5_INV 66
VOLTAGE=1.05V MIN_NECK_WIDTH=0.2 MM
MAKE_BASE=TRUE =PP3V3_S0_MCP 21 22 24 VOLTAGE=5V =PPBUS_S5_FWPWRSW 36
MAKE_BASE=TRUE
=PP3V3_S0_MCP_DAC_UF 25 =PPBUS_G3H_CPU_ISNS_R 46

C 59 =PP0V9_S0_REG PP0V9_S0 7
=PP3V3_S0_MCP_VPLL_UF
=PP3V3_S0_ODD
25

38
=PP5V_S3_EXTUSB 39
C
MIN_LINE_WIDTH=0.4 mm =PP5V_S3_IR 38 40
MIN_NECK_WIDTH=0.2 mm =PP3V3_S0_LPCPLUS
VOLTAGE=0.9V =PP5V_S3_CAMERA 66
MAKE_BASE=TRUE =PP3V3_S0_SMBUS_SMC_0_S0 44
=PP5V_S3_VTTCLAMP 65 46 =PPBUS_G3H_CPU_ISNS PPBUS_G3H_CPU_ISNS 7
=PPVTT_S0_VTTCLAMP 65 =PP3V3_S0_SMBUS_SMC_B_S0 44 MIN_LINE_WIDTH=0.6MM
=PP5V_S3_MCPDDRFET 65 MIN_NECK_WIDTH=0.3MM
=PP3V3_S0_SMBUS_MCP_0 44 VOLTAGE=12.6V
=PP0V9_S3M_MEM_TERM 30 =PP5V_S3_SYSLED 42 MAKE_BASE=TRUE
=PP3V3_S0_FAN_RT 48
=PPVIN_S0_CPUVTTS0
=PP5V_S3_TPAD 49 62
=PP3V3_S0_AUDIO 52 54 55
=PP5V_S3_1V8S3_0V9S0 59 =PPVIN_S5_CPU_IMVP 60
=PP3V3_S0_IMVP 60
=PP5V_S3_AUDIO
65 =PP1V05_S0_FET PP1V05_S0 7 =PP3V3_S0_TMDS 68
MIN_LINE_WIDTH=0.6 MM =PP5V_S3_AUDIO_AMP
MIN_NECK_WIDTH=0.2 MM =PP3V3_S0_LCD 66
VOLTAGE=1.05V
MAKE_BASE=TRUE
=PP1V05_S0_MCP_PEX_DVDD 8 24
=PP3V3_S0_MCP_GPIO
=PP3V3_S0_HDCPROM
18 19 21

25
"ENET" RAILS
=PP1V05_S0_MCP_AVDD_UF =PP3V3_S0_MCP_PLL_UF 24
24
33 =PP3V3_ENET_FET PP3V3_ENET_PHY 7
=PP1V05_S0_MCP_PLL_UF 24 =PP3V3R1V5_S0_MCP_HDA 21 24 MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
=PP1V05_S0_MCP_SATA_DVDD =PP3V3_S0_SMC VOLTAGE=3.3V
8 24 42 MAKE_BASE=TRUE
=PP1V05_S0_MCP_HDMI_VDD 18 25 =PP3V3_S0_MCPTHMSNS 47 =PP3V3_ENET_MCP_RMGT 18 24

=PP1V05_S0_VMON 64 =PP3V3_S0_CPUTHMSNS 47
59 27 =PPVTT_S3_DDR_BUF PPVTT_S3_DDR_BUF 7 =PP3V3_ENET_PHY 32
=PP5VR3V3_S0_MCPCOREISNS 46 MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
=PPSPD_S0_MEM 28 29 VOLTAGE=0.9V =PP1V05_ENET_FET PP1V2R1V05_ENET
63 =PP1V5_S0_FET PP1V5_S0_R 7
=PP3V3_S0_PWRCTL MAKE_BASE=TRUE 33 7
MIN_LINE_WIDTH=0.5 mm 64 MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.5V =PP3V3_S0_VMON 64 VOLTAGE=1.05V
MAKE_BASE=TRUE MAKE_BASE=TRUE
=PP3V3_S0_MCPDDRISNS
"S5" RAILS
46
=PP1V5_S0_CPU 11 12
=PP1V05_ENET_MCP_PLL_MAC 24
=PP3V3_S0_CPUVTTISNS 46
=PP1V5_S0_AIRPORT 31
=PP3V3_FW_P1V0FW =PP1V05_ENET_MCP_RMGT 18 24
63

=PP3V3_FW_PHY 37 =PP1V05_ENET_PHY 32
B 46 =PP1V8_S0
(DDR PWR AFTER SENSE RES.)
PP1V8_S0
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
7 =PP3V3_FW_FWPHY 35 37
63 =PP1V05_S5_REG PP1V05_S5_REG
MIN_LINE_WIDTH=0.6 MM
7 B
VOLTAGE=1.8V MIN_NECK_WIDTH=0.2 MM
MAKE_BASE=TRUE VOLTAGE=1.05V
MAKE_BASE=TRUE
=PP1V8R1V5_S0_MCP_MEM 16 24 36 =PPBUS_S5_FW_FET PPVP_FW 7
=PP1V05_S5_MCP_VDD_AUXC 22 24 VOLTAGE=12.6V MIN_NECK_WIDTH=0.2 MM
MAKE_BASE=TRUE MIN_LINK_WIDTH=0.4 MM
=PP1V05_ENET_P1V05ENETFET 33 =PPVP_FW_PHY_CPS_FET 37

65 =PP1V8_S0_FET PP1V8_S0_R 7
=PPVP_FW_PORT1 37
MIN_LINE_WIDTH=0.5MM
(DDR PWR REG. OUTPUT) MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.8V
MAKE_BASE=TRUE
=PP1V8_S0_VMON 64

=PP1V8_S0_FET_R 46 58 =PP3V3_S5_REG PP3V3_S5 7


MIN_LINE_WIDTH=1.5 mm
=PP3V3R1V8_S0_MCP_IFP_VDD 18 25 MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V
MAKE_BASE=TRUE
"FW" RAILS =PP3V3_S5_MCP_GPIO
=PP3V3_S5_ROM
18 20

43 51

=PP3V3_S5_LCD 66

63 =PP1V0_FW_REG PP1V0_FW 7 =PP3V3_S5_MCP 22 24


MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM =PP3V3_S5_MCPPWRGD 26
VOLTAGE=1.0V
MAKE_BASE=TRUE =PP3V3_S5_AIRPORT_AUX
PEX & SATA AVDD/DVDD aliases =PP1V0_FW_FWPHY 35 =PP3V3_S5_P3V3ENETFET
=PP3V3_S5_PWRCTL
33

64

=PP1V05_S0_MCP_PEX_AVDD0 17 =PP3V3_S5_P1V05ENETFET 33
206 mA (A01)
24 7 PP1V05_S0_MCP_PEX_AVDD =PP1V05_S0_MCP_PEX_AVDD1 17 =PP3V3_S5_P3V3S3FET 65
MAKE_BASE=TRUE
=PP3V3_S5_P3V3S0FET 65
206 mA (A01)
=PP1V05_S0_MCP_PEX_DVDD0 17
57 mA (A01)
=PP3V3_S5_P1V05S5 63 Power Aliases
24 8 =PP1V05_S0_MCP_PEX_DVDD =PP1V05_S0_MCP_PEX_DVDD1 17 =PP3V3_FW_LATEVG 36 37
SYNC_MASTER=K36B_MLB
A 206 mA (A01)
NOTICE OF PROPRIETARY PROPERTY
A
24 7 PP1V05_S0_MCP_SATA_AVDD =PP1V05_S0_MCP_SATA_AVDD0 20
MAKE_BASE=TRUE 127 mA (A01)
=PP1V05_S0_MCP_SATA_AVDD1 20 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
127 mA (A01) PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
24 8 =PP1V05_S0_MCP_SATA_DVDD =PP1V05_S0_MCP_SATA_DVDD0 20 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
43 mA (A01)
127 mA (A01) =PP1V05_S0_MCP_SATA_DVDD1 20 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-8089 02

APPLE INC. SCALE SHT OF


NONE 8 109

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU FSB FREQUENCY STRAPS
PCI-E ALIASES LVDS ALIASES UNUSED EXPRESS CARD LANE BSEL<2..0> FSB MHZ
UNUSED GPU LANES UNUSED LVDS SIGNALS
0 0 0 266
17 =PEG_D2R_N<15:0> NC_PEG_D2R_N<15:0> 71 18 LVDS_IG_A_DATA_P<3> NC_LVDS_IG_A_DATA_P3 0 0 1 133
NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE 71 17 PCIE_EXCARD_D2R_P TP_PCIE_EXCARD_D2RP 69 10 IN CPU_BSEL<0:2> =MCP_BSEL<0:2> OUT 14 0 1 0 200
MAKE_BASE=TRUE MAKE_BASE=TRUE 0 1 1 (166)
17 =PEG_D2R_P<15:0> NC_PEG_D2R_P<15:0> 71 18 LVDS_IG_A_DATA_N<3> NC_LVDS_IG_A_DATA_N3 71 17 PCIE_EXCARD_D2R_N TP_PCIE_EXCARD_D2RN 1 0 0 333
NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE
MAKE_BASE=TRUE
1 0 1 100
1 1 0 (400)
17 =PEG_R2D_C_N<15:0> NC_PEG_R2D_C_N<15:0> 71 18 LVDS_IG_B_CLK_P NC_LVDS_IG_B_CLKP 71 17 PCIE_EXCARD_R2D_C_P TP_PCIE_EXCARD_R2D_CP 1 1 1 (RSVD)
NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
17 =PEG_R2D_C_P<15:0> NC_PEG_R2D_C_P<15:0> 71 18 LVDS_IG_B_CLK_N NC_LVDS_IG_B_CLKN 71 17 PCIE_EXCARD_R2D_C_N TP_PCIE_EXCARD_R2D_CN
NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
17 PCIE_EXCARD_PRSNT_L TP_PCIE_EXCARD_PRSNT_L
17 PEG_PRSNT_L TP_PEG_PRSNT_L 71 18 LVDS_IG_B_DATA_P<3:0> NC_LVDS_IG_B_DATA_P<3:0> MAKE_BASE=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE EXCARD_CLKREQ_L TP_EXCARD_CLKREQ_L
D 17 PEG_CLKREQ_L TP_PEG_CLKREQ_L
MAKE_BASE=TRUE
71 18 LVDS_IG_B_DATA_N<3:0> NC_LVDS_IG_B_DATA_N<3:0>
NO_TEST=TRUE MAKE_BASE=TRUE
17

71 17 PCIE_CLK100M_EXCARD_P TP_PCIE_CLK100M_EXCARDP
MAKE_BASE=TRUE

MAKE_BASE=TRUE
D
PEG_CLK100M_P TP_PEG_CLK100MP 71 17 PCIE_CLK100M_EXCARD_N TP_PCIE_CLK100M_EXCARDN
71 17
MAKE_BASE=TRUE
MAKE_BASE=TRUE
HDA PULL-DOWN
71 17 PEG_CLK100M_N TP_PEG_CLK100MN
MAKE_BASE=TRUE MISC NC MCP79 ALIASES
17 EXTGPU_PWR_EN TP_EXTGPU_PWR_EN AUD_IPHS_SWITCH_EN
MAKE_BASE=TRUE 19

17 EXTGPU_RESET_L TP_EXTGPU_RESET_L 14 CPU_PECI_MCP TP_CPU_PECI_MCP USB ALIASES


MAKE_BASE=TRUE
19 GMUX_JTAG_TDI TP_GMUX_JTAG_TDI
MAKE_BASE=TRUE
UNUSED USB PORTS R0977
1
20K
MAKE_BASE=TRUE
GMUX_JTAG_TMS TP_GMUX_JTAG_TMS 72 20 USB_EXTC_P TP_USB_EXTCP 5%
19 MAKE_BASE=TRUE 1/16W
USB_EXTC_N TP_USB_EXTCN MF-LF
ETHERNET ALIASES 16 MCP_MEM_RESET_L TP_MCP_MEM_RESET_L
MAKE_BASE=TRUE

MAKE_BASE=TRUE
72 20

72 20 USB_EXTD_P TP_USB_EXTDP MAKE_BASE=TRUE 2 402


MAKE_BASE=TRUE
72 20 USB_EXTD_N TP_USB_EXTDN
33 =P3V3ENET_EN PM_SLP_RMGT_L 21
SO-DIMM ALIASES 72 20 USB_EXCARD_P TP_USB_EXCARDP MAKE_BASE=TRUE

MAKE_BASE=TRUE LAN ALIASES


MAKE_BASE=TRUE UNUSED ADDRESS PINS 72 20 USB_EXCARD_N TP_USB_EXCARDN
33 =P1V05ENET_EN MAKE_BASE=TRUE 18 MCP_MII_RXER
31 =USB_MINI_P USB_MINI_P 20 72
32 =PP3V3_ENET_PHY_VDDREG PP3V3_ENET_PHY_VDDREG 28 MEM_A_A<15> TP_MEM_A_A15 MAKE_BASE=TRUE 18 MCP_MII_COL 1
MAKE_BASE=TRUE 31 =USB_MINI_N USB_MINI_N 20 72 R0930
=RTL8211_REGOUT NC_RTL8211_REGOUT
MAKE_BASE=TRUE 29 MEM_B_A<15> TP_MEM_B_A15 MAKE_BASE=TRUE 18 MCP_MII_CRS
32
MAKE_BASE=TRUE MAKE_BASE=TRUE 1
47K
1 R0931 5%
32 =RTL8211_ENSWREG R0932 1/16W
47K MF-LF
47K 5% 2 402
5% 1/16W
1/16W MF-LF
MF-LF 2 402
2 402
TRACKPAD(WELLSPRING)
49 =USB2_TPAD_P USB_TPAD_P 20 72
MAKE_BASE=TRUE
49 =USB2_TPAD_N USB_TPAD_N 20 72
MAKE_BASE=TRUE

BLUETOOTH DP HOTPLUG PULL-DOWN


18 DP_HOTPLUG_DET
=USB2_BT_P USB_BT_P
C 40

40 =USB2_BT_N USB_BT_N
MAKE_BASE=TRUE

MAKE_BASE=TRUE
20 72

20 72 1
R0940 C
20K
5%
1/16W
MF-LF
2 402

CPU HEATSINK STANDOFF SCREW HOLE FW PULL-DOWN


Screw Holes Z0903
OMIT
Z0904
OMIT 17 PCIE_FW_PRSNT_L
STDOFF-4.2OD3.95H-5.52R3.37-6B STDOFF-4.2OD3.95H-5.52R3.37-7SQB 1
1 1 R0955
0
BATTERY,AUDIO,DIP DIMM CONNECTOR CHASSIS GND 5%
1/16W
MF-LF
Z0906 OMIT Z0903 USE SAME Z0913 NON SHAPE OF A HOOF SYMBOL 2 402

5R2P3-7SQBNP FOR LAYOUT PLACEMENT


1 BUT, NEED CHANGE TO HIGH STANDOFF SYMBOL

OMIT OMIT
=GND_BATT_CHGND Z0921 MCP_SAFE_MODE SIGNAL TO SUPPORT
SATA,LVDS CONNECTOR CHASSIS GND
56

=GND_CHASSIS_AUDIO_JACK
Z0905 STDOFF-4.5OD3.95H-1.1-3.2-TH
54
STDOFF-4.5OD3.95H-1.1-3.2-TH ROM FAILURE OVERRIDE
28 =GND_CHASSIS_DIPDIMM_LEFT 1
OMIT 1
R0920
Z0907 55 =GND_CHASSIS_AUDIO_MIC

66 =GND_CHASSIS_LVDS
0
6P5R2P6-7SQB 21 MCP_SPKR 1 2 SMC_MCP_SAFE_MODE IN 41
1 29 28 =GND_CHASSIS_DIPDIMM_CENTER 5%
1/16W
29 =GND_CHASSIS_DIPDIMM_RIGHT MF-LF
34 =GND_CHASSIS_RJ45
402
68 =GND_CHASSIS_TMDS_UPPER MCP_TV_DAC_RSET 18 71
DIP DIMM CONNECTOR CHASSIS GND 37 =GND_CHASSIS_FW_UPPER MCP_TV_DAC_VREF 18 71
OMIT 68 =GND_CHASSIS_TMDS_DOWN R09411
B Z0910
5R2P3-7SQB 37 =GND_CHASSIS_FW_DOWN
124
1%
1 C0940
0.01UF
B
OMIT OMIT 1/16W
10%
1
Z0901 Z0912
MF-LF
402
16V
2 CERM
5R2P3-7SQBNP 2
402
1 STDOFF-4.2OD2.15H-1.2-3.2-TH
DIP DIMM CONNECTOR CHASSIS GND 1

OMIT
Z0909
5R2P3-7SQB
1

55 54 53 52 =GND_AUDIO_CODEC GND_AUDIO_CODEC 1 2
MAKE_BASE=TRUE
DCIN CONNECTOR CHASSIS GND OMIT XW0901
OMIT OMIT Z0913 SM
Z0902 Z0911 STDOFF-4.2OD3.95H-5.52R3.37-6B 53 =GND_AUDIO_AMP GND_AUDIO_AMP 1 2
7X7R2P3-5B 5R2P3-7B MAKE_BASE=TRUE
1 1 1 XW0902
SM

I/O CONNECTOR CHASSIS GND


OMIT
Z0908
5P0R2P3-7BLB
1

(EMI PAD FOR INVERTER GONNECTOR) SIGNAL ALIAS


A TABLE_5_HEAD
SYNC_MASTER=K36B_MLB

NOTICE OF PROPRIETARY PROPERTY


A
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
INVT_CHGND 1 ZS0920
66 EMI-SPRING
TABLE_5_ITEM

CLIP-SM-M42 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


860-0964 4 THERMAL STANDOFF Z0903,Z0904,Z0905,Z0921 ? STANDOFF PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
TABLE_5_ITEM
AGREES TO THE FOLLOWING
860-0723 1 STANDOFF WIRELESS Z0912 ? STANDOFF I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
TABLE_5_ITEM

II NOT TO REPRODUCE OR COPY IT


860-0749 1 STANDOFF W/THRU HOLES,WIRELESS Z0913 ? STANDOFF
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-8089 02

APPLE INC. SCALE SHT OF


NONE 9 109

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT
69 14 BI FSB_A_L<3> J4 A3* U1000 ADS* H1 FSB_ADS_L BI 14 69

69 14 BI FSB_A_L<4> L5 A4* PENRYN BNR* E2 FSB_BNR_L BI 14 69

FSB_A_L<5> L4 FCBGA G5 FSB_BPRI_L


69 14 BI A5* BPRI* BI 14 69
1 OF 4 =PP1V05_S0_CPU 6 8 11 12 13
69 14 BI FSB_A_L<6> K5 A6*
69 14 BI FSB_A_L<7> M3 A7* DEFER* H5 FSB_DEFER_L BI 14 69

69 14 BI FSB_A_L<8> N2 A8* DRDY* F21 FSB_DRDY_L BI 14 69


1
69 14 FSB_A_L<9> J1 A9* DBSY* E1 FSB_DBSY_L 14 69
R1000
BI BI
54.9
69 14 BI FSB_A_L<10> N3 A10* 1%

ADDR GROUP0
1/16W
69 14 BI FSB_A_L<11> P5 A11* BR0* F1 FSB_BREQ0_L BI 14 69 MF-LF
402

CONTROL
FSB_A_L<12> P2 A12* 2
69 14 BI

D 69 14

69 14
BI
BI
FSB_A_L<13>
FSB_A_L<14>
L2

P4
A13*
A14*
IERR*
INIT*
D20

B3
69 CPU_IERR_L
CPU_INIT_L IN 14 69
D
69 14 BI FSB_A_L<15> P1 A15*
69 14 BI FSB_A_L<16> R1 A16* LOCK* H4 FSB_LOCK_L BI 14 69

69 14 BI FSB_ADSTB_L<0> M1 ADSTB0*

RESET* C1 FSB_CPURST_L IN 13 14 69

69 14 BI FSB_REQ_L<0> K3 REQ0* RS0* F3 FSB_RS_L<0> IN 14 69

69 14 BI FSB_REQ_L<1> H2 REQ1* RS1* F4 FSB_RS_L<1> IN 14 69

69 14 BI FSB_REQ_L<2> K2 REQ2* RS2* G3 FSB_RS_L<2> IN 14 69

69 14 BI FSB_REQ_L<3> J3 REQ3* TRDY* G2 FSB_TRDY_L IN 14 69

69 14 BI FSB_REQ_L<4> L1 REQ4*

HIT* G6 FSB_HIT_L BI 14 69

69 14 BI FSB_A_L<17> Y2 A17* HITM* E4 FSB_HITM_L BI 14 69 OMIT


FSB_A_L<18> U5 A18* FSB_D_L<0> E22 D0* D32* Y22 FSB_D_L<32>
69 14 BI 69 14 BI U1000 BI 14 69

69 14 BI FSB_A_L<19> R3 A19* BPM0* AD4 XDP_BPM_L<0> BI 7 13 69


1
69 14 BI FSB_D_L<1> F24 D1* PENRYN D33* AB24 FSB_D_L<33> BI 14 69

69 14 FSB_A_L<20> W6 A20* BPM1* AD3 XDP_BPM_L<1> 7 13 69


R1001 69 14 FSB_D_L<2> E26 D2* FCBGA D34* V24 FSB_D_L<34> 14 69
BI BI 54.9 BI BI

XDP/ITP SIGNALS
69 14 BI FSB_A_L<21> U4 A21* BPM2* AD1 XDP_BPM_L<2> BI 7 13 69 1% 69 14 BI FSB_D_L<3> G22 D3* 2 OF 4 D35* V26 FSB_D_L<35> BI 14 69

69 14 FSB_A_L<22> Y5 A22* ADDR GROUP1 BPM3* AC4 XDP_BPM_L<3> 7 13 69


1/16W
MF-LF 69 14 FSB_D_L<4> F23 D4* D36* V23 FSB_D_L<36> 14 69
BI BI BI BI
402
FSB_A_L<23> U1 A23* PRDY* AC2 XDP_BPM_L<4> 2 FSB_D_L<5> T22 FSB_D_L<37>
69 14 BI BI 7 13 69 69 14 BI G25 D5* D37* BI 14 69

69 14 BI FSB_A_L<24> R4 A24* PREQ* AC1 XDP_BPM_L<5> BI 7 13 69 69 14 BI FSB_D_L<6> E25 D6* D38* U25 FSB_D_L<38> BI 14 69

69 14 BI FSB_A_L<25> T5 A25* TCK AC5 XDP_TCK IN 6 7 10 13 69 69 14 BI FSB_D_L<7> E23 D7* D39* U23 FSB_D_L<39> BI 14 69

69 14 BI FSB_A_L<26> T3 A26* TDI AA6 XDP_TDI IN 6 7 10 13 69 69 14 BI FSB_D_L<8> K24 D8* D40* Y25 FSB_D_L<40> BI 14 69

69 14 BI FSB_A_L<27> W2 A27* TDO AB3 XDP_TDO OUT 6 10 69 69 14 BI FSB_D_L<9> G24 D9* D41* W22 FSB_D_L<41> BI 14 69

DATA GRP 0

DATA GRP 2
69 14 BI FSB_A_L<28> W5 A28* TMS AB5 XDP_TMS IN 6 7 10 13 69 69 14 BI FSB_D_L<10> J24 D10* D42* Y23 FSB_D_L<42> BI 14 69

69 14 BI FSB_A_L<29> Y4 A29* TRST* AB6 XDP_TRST_L IN 6 7 10 13 69 69 14 BI FSB_D_L<11> J23 D11* D43* W24 FSB_D_L<43> BI 14 69

69 14 BI FSB_A_L<30> U2 A30* DBR* C20 XDP_DBRESET_L OUT 7 13 26 69 14 BI FSB_D_L<12> H22 D12* D44* W25 FSB_D_L<44> BI 14 69

C 69 14

69 14
BI FSB_A_L<31>
FSB_A_L<32>
V4

W3
A31*
A32*
R1002 1
5%
68
69 14

69 14
BI FSB_D_L<13>
FSB_D_L<14>
F26
K22
D13*
D14*
D45*
D46*
AA23

AA24
FSB_D_L<45>
FSB_D_L<46>
BI 14 69

14 69
C
BI BI BI
1/16W
69 14 FSB_A_L<33> AA4 A33* THERMAL MF-LF 69 14 FSB_D_L<15> H23 D15* D47* AB25 FSB_D_L<47> 14 69
BI BI BI
402
FSB_A_L<34> AB2 2 FSB_DSTB_L_N<0> Y26 FSB_DSTB_L_N<2>
69 14 BI A34* 69 14 BI J26 DSTBN0* DSTBN2* BI 14 69

69 14 BI FSB_A_L<35> AA3 A35* PROCHOT* D21 CPU_PROCHOT_L OUT 14 42 60 69 69 14 BI FSB_DSTB_L_P<0> H26 DSTBP0* DSTBP2* AA26 FSB_DSTB_L_P<2> BI 14 69

69 14 BI FSB_ADSTB_L<1> V1 ADSTB1* THERMDA A24 CPU_THERMD_P OUT 47 69 14 BI FSB_DINV_L<0> H25 DINV0* DINV2* U22 FSB_DINV_L<2> BI 14 69

THERMDC B25 CPU_THERMD_N OUT 47

69 14 IN CPU_A20M_L A6 A20M*
OUT CPU_FERR_L PM_THRMTRIP_L FSB_D_L<16> FSB_D_L<48>
69 14 A5 FERR* THERMTRIP* C7 14 42 69 69 14 N22 D16* D48* AE24 14 69
OUT BI BI
IN CPU_IGNNE_L FSB_D_L<17> FSB_D_L<49>
69 14 C4 IGNNE* 69 14 K25 D17* D49* AD24 14 69
BI BI
ICH

69 14 BI FSB_D_L<18> P26 D18* D50* AA21 FSB_D_L<50> BI 14 69


H CLK
69 14 IN CPU_STPCLK_L D5 STPCLK* 69 14 BI FSB_D_L<19> R23 D19* D51* AB22 FSB_D_L<51> BI 14 69

69 14 IN CPU_INTR C6 LINT0 69 14 BI FSB_D_L<20> L23 D20* D52* AB21 FSB_D_L<52> BI 14 69

69 14 IN CPU_NMI B4 LINT1 BCLK0 A22 FSB_CLK_CPU_P IN 14 69 69 14 BI FSB_D_L<21> M24 D21* D53* AC26 FSB_D_L<53> BI 14 69

69 14 IN CPU_SMI_L A3 SMI* BCLK1 A21 FSB_CLK_CPU_N IN 14 69 69 14 BI FSB_D_L<22> L22 D22* D54* AD20 FSB_D_L<54> BI 14 69

69 14 BI FSB_D_L<23> M23 D23* D55* AE22 FSB_D_L<55> BI 14 69

DATA GRP 1

DATA GRP 3
TP_CPU_RSVD_M4 M4 RSVD0 69 14 BI FSB_D_L<24> P25 D24* D56* AF23 FSB_D_L<56> BI 14 69

TP_CPU_RSVD_N5 N5 RSVD1 69 14 BI FSB_D_L<25> P23 D25* D57* AC25 FSB_D_L<57> BI 14 69

TP_CPU_RSVD_T2 T2 RSVD2 69 14 BI FSB_D_L<26> P22 D26* D58* AE21 FSB_D_L<58> BI 14 69

TP_CPU_RSVD_V3 V3 RSVD3 69 14 BI FSB_D_L<27> T24 D27* D59* AD21 FSB_D_L<59> BI 14 69


RESERVED

TP_CPU_RSVD_B2 B2 RSVD4 69 14 BI FSB_D_L<28> R24 D28* D60* AC22 FSB_D_L<60> BI 14 69

TP_CPU_RSVD_F6 F6 RSVD5 69 14 BI FSB_D_L<29> L25 D29* D61* AD23 FSB_D_L<61> BI 14 69

TP_CPU_RSVD_D2 D2 RSVD6 69 14 BI FSB_D_L<30> T25 D30* D62* AF22 FSB_D_L<62> BI 14 69

TP_CPU_RSVD_D22 D22 RSVD7 1


69 14 BI FSB_D_L<31> N25 D31* D63* AC23 FSB_D_L<63> BI 14 69

TP_CPU_RSVD_D3 D3 RSVD8 R1005 69 14 BI FSB_DSTB_L_N<1> L26 DSTBN1* DSTBN3* AE25 FSB_DSTB_L_N<3> BI 14 69


1K
CPU JTAG Support 1%
1/16W
69 14 BI FSB_DSTB_L_P<1> M26 DSTBP1* DSTBP3* AF24 FSB_DSTB_L_P<3> BI 14 69

B R1090 2
MF-LF
402
69 14 BI FSB_DINV_L<1> N24 DINV1* DINV3* AC20 FSB_DINV_L<3> BI 14 69
B
54.9
69 13 10 7 6 XDP_TMS 1 2 CPU_GTLREF
69 27 AD26 GTLREF MISC COMP0 R26 69 CPU_COMP<0>
1% CPU_TEST1 C23 TEST1 COMP1 U26 69 CPU_COMP<1>
1/16W
R1091 1 CPU_TEST2 D25 TEST2 COMP2 AA1 CPU_COMP<2>
54.9
MF-LF
402 R1006 69

69 13 10 7 6 XDP_TDI 1 2 2.0K TP_CPU_TEST3 C24 TEST3 COMP3 Y1 69 CPU_COMP<3>


1%
1% 1/16W CPU_TEST4 AF26 TEST4
1/16W
MF-LF R1092 MF-LF
NO STUFF TP_CPU_TEST5 AF1 TEST5 DPRSTP* E5 CPU_DPRSTP_L R1023 1 R1021 1
2 402 IN 14 60 69
402 54.9
69 10 6 XDP_TDO 1 2 C1014 1 TP_CPU_TEST6 A26 TEST6 DPSLP* B5 CPU_DPSLP_L IN 14 69 54.9 54.9
1% 1%
PLACEMENT_NOTE=Place R1092 near ITP connector (if present) 1% NO STUFF 0.1uF TP_CPU_TEST7 C3 TEST7 DPWR* D24 FSB_DPWR_L 14 69 1/16W 1/16W
1/16W 10% IN
16V MF-LF MF-LF
OUT CPU_BSEL<0> CPU_PWRGD
MF-LF B22 BSEL0 PWRGOOD D6
402 R1010 X5R
402
2 69 9 IN 13 14 69 402
2
402
2
OUT CPU_BSEL<1> FSB_CPUSLP_L
0 69 9 B23 BSEL1 SLP* D7 14 69
1 2 IN
OUT CPU_BSEL<2> CPU_PSI_L
69 9 C21 BSEL2 PSI* AE6 60
OUT 1 1
NO STUFF 5% NO STUFF R1022 R1020
1/16W
R1093 R1011 1 MF-LF
402
1
R1012 27.4
1%
27.4
1%
54.9 1K 1K PLACEMENT_NOTE=Place C1014 within 12.7mm of CPU. 1/16W 1/16W
69 13 10 7 6 XDP_TCK 1 2 5% 5% MF-LF MF-LF
1/16W 1/16W PLACEMENT_NOTE=Place R1005 within 12.7mm of CPU. 2
402
2
402
1% MF-LF MF-LF
R1094 1/16W 402 2 2 402 PLACEMENT_NOTE=Place R1006 within 12.7mm of CPU.
MF-LF
649 402
69 13 10 7 6 XDP_TRST_L 1 2 PLACEMENT_NOTE (all 4 resistors):
1%
1/16W Place within 12.7mm of CPU
MF-LF
402

CPU FSB
A SYNC_MASTER=K36B_MLB

NOTICE OF PROPRIETARY PROPERTY


SYNC_DATE=08/18/2008
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

SYNC FROM T18 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT

CHANGE CPU FROM SOCKET TO BGA SYMBOL III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-8089 02

APPLE INC. SCALE SHT OF


NONE 10 109

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

A4 P6

(CPU CORE POWER) A8 P21


OMIT
A11 P24
=PPVCORE_S0_CPU 8 11 12
A14
U1000 R2

44 A (SV Design Target) A16


PENRYN R5
FCBGA
41 A (SV HFM) A19 R22

D A7 AB20 30.4 A (SV LFM) A23


4 OF 4
R25 D
A9 AB7 23 A (LV Design Target) AF2 T1
OMIT
A10 AC7 B6 T4
U1000
A12 AC9 B8 T23
PENRYN
A13 FCBGA AC12 B11 T26

A15 AC13 B13 U3


3 OF 4
A17 AC15 B16 U6

A18 AC17 B19 U21


A20 AC18 B21 U24

B7 AD7 B24 V2

B9 AD9 C5 V5
B10 AD10 C8 V22
B12 AD12 C11 V25

B14 AD14 C14 W1


B15 AD15 C16 W4
B17 AD17 C19 W23

B18 AD18 C2 W26


B20 AE9 C22 Y3
VCC
C9 AE10 C25 Y6
C10 AE12 D1 Y21

C12 AE13 D4 Y24

C13 AE15 D8 AA2


C15 AE17 D11 AA5

C17 AE18 D13 AA8

C18 AE20 D16 AA11


D9 AF9 D19 AA14

C D10

D12
AF10

AF12
D23

D26
AA16

AA19
C
D14 AF14 E3 AA22

D15 VCC AF15 E6 AA25

D17 AF17 E8 AB1

D18 AF18 E11 AB4


AF20
(CPU IO POWER 1.05V)
E7 E14 VSS VSS AB8
E9 =PP1V05_S0_CPU 6 8 10 12 13 E16 AB11

E10 G21 E19 AB13

E12 V6
4500 mA (before VCC stable)
E21 AB16
E13 J6
2500 mA (after VCC stable)
E24 AB19

E15 K6 F5 AB23

E17 M6 F8 AB26
E18 J21 F11 AC3

E20 K21 F13 AC6


F7 M21 F16 AC8
VCCP
F9 N21 F19 AC11
F10 N6 F2 AC14
F12 R21 F22 AC16
F14 R6 F25 AC19

F15 T21 G4 AC21


F17 T6 G1 AC24
F18 V21
NEED 1.5V POWER SOURCE G23 AD2
(CPU INTERNAL PLL POWER 1.5V)
F20 W21 G26 AD5

AA7 (BR1#) =PP1V5_S0_CPU 8 12 H3 AD8

AA9 B26 H6 AD11


AA10 VCCA C26
130 mA H21 AD13

B AA12 H24 AD16 B


AA13 VID0 AD6 CPU_VID<0> OUT 60 69 J2 AD19
AA15 VID1 AF5 CPU_VID<1> OUT 60 69 J5 AD22

AA17 VID2 AE5 CPU_VID<2> OUT 60 69 J22 AD25


=PPVCORE_S0_CPU 8 11 12
AA18 VID3 AF4 CPU_VID<3> OUT 60 69 J25 AE1
AA20 VID4 AE3 CPU_VID<4> OUT 60 69
1
K1 AE4
AB9 VID5 AF3 CPU_VID<5> 60 69
R1100 K4 AE8
OUT 100
AC10 VID6 AE2 CPU_VID<6> OUT 60 69 1% K23 AE11
1/16W
AB10 MF-LF K26 AE14
402
AB12 2 L3 AE16
AB14 VCCSENSE AF7 CPU_VCCSENSE_P OUT 60 69 L6 AE19
AB15 L21 AE23
PLACEMENT_NOTE=Place R1100 within 25.4mm of CPU, no stubs.
AB17 PLACEMENT_NOTE=Place R1101 within 25.4mm of CPU, no stubs. L24 AE26
AB18 VSSSENSE AE7 CPU_VCCSENSE_N OUT 60 69 M2 A2
M5 AF6
1 M22 AF8
R1101
100 M25 AF11
1%
1/16W N1 AF13
MF-LF
402 N4 AF16
2
N23 AF19
N26 AF21
P3 A25
B1 (Socket-P KEY) AF25

CPU Power & Ground


A SYNC_MASTER=K36B_MLB

NOTICE OF PROPRIETARY PROPERTY


SYNC_DATE=08/17/2008
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
SYNC FROM T18 AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

CHANGE CPU FROM SOCKET TO BGA SYMBOL II NOT TO REPRODUCE OR COPY IT


III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-8089 02

APPLE INC. SCALE SHT OF


11 109
NONE
Current numbers from Merom for Santa Rosa EMTS, doc #20905.

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

CPU VCore HF and Bulk Decoupling


6x 330uF. 32x 22uF 0805 (20 stuffed)

PLACEMENT_NOTE (C1200-C1219):
11 8 =PPVCORE_S0_CPU
Place inside socket cavity on secondary side.
D CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
D
1 1 1 1 1 1 1 1 1 1
C1200 C1201 C1202 C1203 C1204 C1205 C1206 C1207 C1208 C1209
22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
805 805 805 805 805 805 805 805 805 805

CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
1
C1210 1
C1211 1
C1212 1
C1213 1
C1214 1
C1215 1
C1216 1
C1217 1
C1218 1
C1219
22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
805 805 805 805 805 805 805 805 805 805

PLACEMENT_NOTE (C1240-C1243):

Place on secondary side.

CRITICAL CRITICAL CRITICAL CRITICAL


1 1 1 1
C1240 C1241 C1242 C1243
330UF 330UF 330UF 330UF
20% 20% 20% 20%
3 2 2.0V 3 2 2.0V 3 2 2.0V 3 2 2.0V
POLY-TANT POLY-TANT POLY-TANT POLY-TANT
D2T-SM2 D2T-SM2 D2T-SM2 D2T-SM2

C C

VCCA (CPU AVdd) DECOUPLING


1x 10uF, 1x 0.01uF
11 8 =PP1V5_S0_CPU
PLACEMENT_NOTE=PLACE C1250 C1251 NEAR CPU PIN B26.

C1250 1 1
C1251
10uF 0.01UF
20% 10%
6.3V 16V
X5R 2 2 CERM
603 402

B B
VCCP (CPU I/O) DECOUPLING
1x 330uF, 6x 0.1uF 0402
13 11 10 8 6 =PP1V05_S0_CPU
PLACEMENT_NOTE=PLACE C1260 BETWEEN CPU & MCP79.

CRITICAL
C1260 1 1 C1261 1 C1262 1 C1263 1 C1264 1 C1265 1 C1266
330UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 20% 20% 20%
2.0V 10V 10V 10V 10V 10V 10V
2 3 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
POLY-TANT
D2T-SM2 402 402 402 402 402 402

CPU Decoupling
A SYNC_MASTER=K36B_MLB

NOTICE OF PROPRIETARY PROPERTY


SYNC_DATE=08/17/2008
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
SYNC FROM T18 AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-8089 02

APPLE INC. SCALE SHT OF


NONE 12 109

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

Mini-XDP Connector
NOTE: This is not the standard XDP pinout.

D Use with 920-0620 adapter board to support CPU, MCP debugging.


D

MCP79-specific pinout

8 6 =PP3V3_S0_XDP
12 11 10 8 6 =PP1V05_S0_CPU XDP_CONN
J1300
6-1747769-0
XDP CRITICAL
F-ST-SM
R1315 1 64
54.9 62
1%
1/16W
MF-LF
402 2
1 2

69 10 7 XDP_BPM_L<5> OBSFN_A0 3 4 OBSFN_C0 JTAG_MCP_TDO_CONN 6 7


BI IN
69 10 7 XDP_BPM_L<4> OBSFN_A1 5 6 OBSFN_C1 JTAG_MCP_TRST_L 6 7 21
BI OUT
7 8

69 10 7 XDP_BPM_L<3> OBSDATA_A0 9 10 OBSDATA_C0 MCP_DEBUG<0> 7 19 72


BI BI
69 10 7 XDP_BPM_L<2> OBSDATA_A1 11 12 OBSDATA_C1 MCP_DEBUG<1> 7 19 72
IN BI
13 14

69 10 7 XDP_BPM_L<1> OBSDATA_A2 15 16 OBSDATA_C2 MCP_DEBUG<2> 7 19 72


IN BI
69 10 7 XDP_BPM_L<0> OBSDATA_A3 17 18 OBSDATA_C3 MCP_DEBUG<3> 7 19 72
IN BI
19 20
C 7 TP_XDP_OBSFN_B0 OBSFN_B0 21 22 OBSFN_D0 JTAG_MCP_TDI OUT 6 7 21
C
7 TP_XDP_OBSFN_B1 OBSFN_B1 23 24 OBSFN_D1 JTAG_MCP_TMS 6 7 21
OUT
25 26

7 TP_XDP_OBSDATA_B0 OBSDATA_B0 27 28 OBSDATA_D0 MCP_DEBUG<4> 7 19 72


BI
7 TP_XDP_OBSDATA_B1 OBSDATA_B1 29 30 OBSDATA_D1 MCP_DEBUG<5> 7 19 72
BI
31 32

7 TP_XDP_OBSDATA_B2 OBSDATA_B2 33 34 OBSDATA_D2 MCP_DEBUG<6> 7 19 72


BI
XDP 35 36
7 TP_XDP_OBSDATA_B3 OBSDATA_B3 OBSDATA_D3 MCP_DEBUG<7> BI 7 19 72
R1399 37 38
1K 39 40
69 14 10 IN CPU_PWRGD 1 2 7 XDP_PWRGD PWRGD/HOOK0 ITPCLK/HOOK4 FSB_CLK_ITP_P IN 7 14 69
41 42 XDP
5% 7 XDP_OBS20 HOOK1 ITPCLK#/HOOK5 FSB_CLK_ITP_N IN 7 14 69
1/16W
MF-LF VCC_OBS_AB 43 44 VCC_OBS_CD R1303
402
45 46 1K
19 7 IN PM_LATRIGGER_L HOOK2 RESET#/HOOK6 69 7 XDP_CPURST_L 1 2 FSB_CPURST_L IN 10 14 69

21 7 6 JTAG_MCP_TCK HOOK3 47 48 DBR#/HOOK7 XDP_DBRESET_L 7 10 26 5% PLACEMENT_NOTE=Place close to CPU to minimize stub.


OUT OUT 1/16W
49 50 NOTE: XDP_DBRESET_L must be pulled-up to 3.3V. MF-LF
402
72 44 21 7 SMBUS_MCP_0_DATA SDA 51 52 TDO XDP_TDO_CONN 6 7
BI IN
72 44 21 7 SMBUS_MCP_0_CLK SCL 53 54 TRSTn XDP_TRST_L 6 7 10 69
BI OUT
TCK1 55 56 TDI XDP_TDI
NC OUT 6 7 10 69

69 10 7 6 XDP_TCK TCK0 57 58 TMS XDP_TMS 6 7 10 69


OUT OUT
59 60 XDP_PRESENT#
XDP XDP
C1300 1
61
1
C1301
0.1uF 0.1uF
10% 63 10%
16V 16V
X5R 2 2 X5R
402 516S0625 402

B B

Direction of XDP module


Please avoid any obstructions
on even-numbered side of J1300

eXtended Debug Port(MiniXDP)

A SYNC_MASTER=M99_MLB

NOTICE OF PROPRIETARY PROPERTY


SYNC_DATE=01/08/2008
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-8089 02

APPLE INC. SCALE SHT OF


NONE 13 109

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT
U1400
MCP79-TOPO-B
BGA
(1 OF 11)

69 10 BI FSB_DSTB_L_P<0> T40 CPU_DSTBP0# CPU_D0# Y43 FSB_D_L<0> BI 10 69

69 10 BI FSB_DSTB_L_N<0> U40 CPU_DSTBN0# CPU_D1# W42 FSB_D_L<1> BI 10 69

69 10 BI FSB_DINV_L<0> V41 CPU_DBI0# CPU_D2# Y40 FSB_D_L<2> BI 10 69

CPU_D3# W41 FSB_D_L<3> BI 10 69


69 10 BI FSB_DSTB_L_P<1> W39 CPU_DSTBP1#
CPU_D4# Y39 FSB_D_L<4> BI 10 69
69 10 BI FSB_DSTB_L_N<1> W37 CPU_DSTBN1#
CPU_D5# V42 FSB_D_L<5> BI 10 69
69 10 BI FSB_DINV_L<1> V35 CPU_DBI1#
CPU_D6# Y41 FSB_D_L<6> BI 10 69

D 69 10

69 10
BI
BI
FSB_DSTB_L_P<2>
FSB_DSTB_L_N<2>
N37

L36
CPU_DSTBP2#
CPU_DSTBN2#
CPU_D7#
CPU_D8#
Y42
P42
FSB_D_L<7>
FSB_D_L<8>
BI
BI
10 69

10 69
D
69 10 BI FSB_DINV_L<2> N35 CPU_DBI2# CPU_D9# U41 FSB_D_L<9> BI 10 69

CPU_D10# R42 FSB_D_L<10> BI 10 69


69 10 BI FSB_DSTB_L_P<3> M39 CPU_DSTBP3#
CPU_D11# T39 FSB_D_L<11> BI 10 69
69 10 BI FSB_DSTB_L_N<3> M41 CPU_DSTBN3#
CPU_D12# T42 FSB_D_L<12> BI 10 69
69 10 BI FSB_DINV_L<3> J41 CPU_DBI3#
CPU_D13# T41 FSB_D_L<13> BI 10 69

CPU_D14# R41 FSB_D_L<14> BI 10 69


69 10 BI FSB_A_L<3> AC34 CPU_A3#
CPU_D15# T43 FSB_D_L<15> BI 10 69
69 10 BI FSB_A_L<4> AE38 CPU_A4#
CPU_D16# W35 FSB_D_L<16> BI 10 69
69 10 BI FSB_A_L<5> AE34 CPU_A5#
CPU_D17# AA37 FSB_D_L<17> BI 10 69
69 10 BI FSB_A_L<6> AC37 CPU_A6#
CPU_D18# W33 FSB_D_L<18> BI 10 69
69 10 BI FSB_A_L<7> AE37 CPU_A7#
CPU_D19# W34 FSB_D_L<19> BI 10 69
69 10 BI FSB_A_L<8> AE35 CPU_A8#
CPU_D20# AA36 FSB_D_L<20> BI 10 69
69 10 BI FSB_A_L<9> AB35 CPU_A9#
CPU_D21# AA34 FSB_D_L<21> BI 10 69
69 10 BI FSB_A_L<10> AF35 CPU_A10#
CPU_D22# AA38 FSB_D_L<22> BI 10 69
69 10 BI FSB_A_L<11> AG35 CPU_A11#
CPU_D23# AA35 FSB_D_L<23> BI 10 69
69 10 BI FSB_A_L<12> AG39 CPU_A12#
CPU_D24# U38 FSB_D_L<24> BI 10 69
69 10 BI FSB_A_L<13> AE33 CPU_A13#
CPU_D25# U36 FSB_D_L<25> BI 10 69
69 10 BI FSB_A_L<14> AG37 CPU_A14#
CPU_D26# U35 FSB_D_L<26> BI 10 69
69 10 BI FSB_A_L<15> AG38 CPU_A15#
CPU_D27# U33 FSB_D_L<27> BI 10 69
69 10 BI FSB_A_L<16> AG34 CPU_A16#
CPU_D28# U34 FSB_D_L<28> BI 10 69
69 10 BI FSB_A_L<17> AN38 CPU_A17#
CPU_D29# W38 FSB_D_L<29> BI 10 69
69 10 BI FSB_A_L<18> AL39 CPU_A18#
CPU_D30# R33 FSB_D_L<30> BI 10 69
69 10 BI FSB_A_L<19> AG33 CPU_A19#
CPU_D31# U37 FSB_D_L<31> BI 10 69
69 10 BI FSB_A_L<20> AL33 CPU_A20#
CPU_D32# N34 FSB_D_L<32> BI 10 69
69 10 BI FSB_A_L<21> AJ33 CPU_A21#
CPU_D33# N33 FSB_D_L<33> BI 10 69

C 69 10

69 10
BI
BI
FSB_A_L<22>
FSB_A_L<23>
AN36

AJ35
CPU_A22#
CPU_A23#
CPU_D34#
CPU_D35#
R34

R35
FSB_D_L<34>
FSB_D_L<35>
BI 10 69 C

FSB
BI 10 69
69 10 BI FSB_A_L<24> AJ37 CPU_A24#
CPU_D36# P35 FSB_D_L<36> BI 10 69
69 10 BI FSB_A_L<25> AJ36 CPU_A25#
CPU_D37# R39 FSB_D_L<37> BI 10 69
69 10 BI FSB_A_L<26> AJ38 CPU_A26#
CPU_D38# R37 FSB_D_L<38> BI 10 69
69 10 BI FSB_A_L<27> AL37 CPU_A27#
CPU_D39# R38 FSB_D_L<39> BI 10 69
69 10 BI FSB_A_L<28> AL34 CPU_A28#
CPU_D40# L37 FSB_D_L<40> BI 10 69
69 10 BI FSB_A_L<29> AN37 CPU_A29#
CPU_D41# L39 FSB_D_L<41> BI 10 69
69 10 BI FSB_A_L<30> AJ34 CPU_A30#
CPU_D42# L38 FSB_D_L<42> BI 10 69
69 10 BI FSB_A_L<31> AL38 CPU_A31#
CPU_D43# N36 FSB_D_L<43> BI 10 69
69 10 BI FSB_A_L<32> AL35 CPU_A32#
CPU_D44# N38 FSB_D_L<44> BI 10 69
69 10 BI FSB_A_L<33> AN34 CPU_A33#
CPU_D45# J39 FSB_D_L<45> BI 10 69
69 10 BI FSB_A_L<34> AR39 CPU_A34#
CPU_D46# J38 FSB_D_L<46> BI 10 69
69 10 BI FSB_A_L<35> AN35 CPU_A35#
CPU_D47# J37 FSB_D_L<47> BI 10 69

69 10 BI FSB_ADSTB_L<0> AE36 CPU_ADSTB0# CPU_D48# L42 FSB_D_L<48> BI 10 69

69 10 BI FSB_ADSTB_L<1> AK35 CPU_ADSTB1# CPU_D49# M42 FSB_D_L<49> BI 10 69

CPU_D50# P41 FSB_D_L<50> BI 10 69

69 10 BI FSB_REQ_L<0> AC38 CPU_REQ0# CPU_D51# N41 FSB_D_L<51> BI 10 69

69 10 BI FSB_REQ_L<1> AA33 CPU_REQ1# CPU_D52# N40 FSB_D_L<52> BI 10 69

69 10 BI FSB_REQ_L<2> AC39 CPU_REQ2# CPU_D53# M40 FSB_D_L<53> BI 10 69


24 22 14 8 =PP1V05_S0_MCP_FSB
69 10 BI FSB_REQ_L<3> AC33 CPU_REQ3# CPU_D54# H40 FSB_D_L<54> BI 10 69

69 10 BI FSB_REQ_L<4> AC35 CPU_REQ4# CPU_D55# K42 FSB_D_L<55> BI 10 69


R1410 1 R1415 1
1
R1416 CPU_D56# H41 FSB_D_L<56> 10 69
54.9 62 62 BI
1% 5% 5% 69 10 BI FSB_ADS_L AD42 CPU_ADS# CPU_D57# L41 FSB_D_L<57> BI 10 69
1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF 69 10 BI FSB_BNR_L AD43 CPU_BNR# CPU_D58# H43 FSB_D_L<58> BI 10 69
402 402 402
2 2 2 FSB_BREQ0_L AE40 CPU_D59# H42 FSB_D_L<59>
69 10 BI CPU_BR0# BI 10 69

B 69 42 10 IN PM_THRMTRIP_L 69 10 BI
69 FSB_BREQ1_L
FSB_DBSY_L
AL32

AD39
CPU_BR1#
CPU_DBSY#
CPU_D60#
CPU_D61#
K41

J40
FSB_D_L<60>
FSB_D_L<61>
BI
BI
10 69

10 69
B
69 10 IN CPU_FERR_L 69 10 BI FSB_DRDY_L AD41 CPU_DRDY# CPU_D62# H39 FSB_D_L<62> BI 10 69

69 10 BI FSB_HIT_L AB42 CPU_HIT# CPU_D63# M43 FSB_D_L<63> BI 10 69

69 10 BI FSB_HITM_L AD40 CPU_HITM#


69 10 IN FSB_LOCK_L AC43 CPU_LOCK# CPU_BPRI# AA41 FSB_BPRI_L OUT 10 69

69 10 OUT FSB_TRDY_L AE41 CPU_TRDY# CPU_DEFER# AA40 FSB_DEFER_L OUT 10 69

NO STUFF NO STUFF NO STUFF


1 1 1
9 OUT CPU_PECI_MCP E41 CPU_PECI
R1420 R1421 R1422 BCLK_OUT_CPU_P G42 FSB_CLK_CPU_P OUT 10 69
69 60 42 10 OUT CPU_PROCHOT_L AJ41 CPU_PROCHOT#
1K 1K 1K BCLK_OUT_CPU_N G41 FSB_CLK_CPU_N OUT 10 69
5% 5% 5% AG43 CPU_THERMTRIP#
1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF AH40 CPU_FERR# BCLK_OUT_ITP_P AL43 FSB_CLK_ITP_P OUT 7 13 69
402 402 402
2 2 2 BCLK_OUT_ITP_N AL42 FSB_CLK_ITP_N OUT 7 13 69

9 IN =MCP_BSEL<2> (MCP_BSEL<2>) F42 CPU_BSEL2


BCLK_OUT_NB_P AL41 69 FSB_CLK_MCP_P
9 IN =MCP_BSEL<1> (MCP_BSEL<1>) D42 CPU_BSEL1
BCLK_OUT_NB_N AK42 69 FSB_CLK_MCP_N
9 IN =MCP_BSEL<0> (MCP_BSEL<0>) F41 CPU_BSEL0
Loop-back clock for delay matching.
69 10 OUT FSB_RS_L<0> AC41 CPU_RS0# BCLK_IN_N AK41

69 10 OUT FSB_RS_L<1> AB41 CPU_RS1# BCLK_IN_P AJ40

69 10 OUT FSB_RS_L<2> AC42 CPU_RS2#

R1430
1 1
R1435 24 PP1V05_S0_MCP_PLL_FSB CPU_A20M# AF41 CPU_A20M_L OUT 10 69 =PP1V05_S0_MCP_FSB 8 14 22 24

49.9 49.9 270 mA (A01) 206 mA AG27 +V_DLL_DLCELL_AVDD CPU_IGNNE# AH39 CPU_IGNNE_L OUT 10 69 NO STUFF
1% 1%
AH27 CPU_INIT# AH42 CPU_INIT_L 1
1/16W 1/16W 20 mA +V_PLL_MCLK OUT 10 69 R1440
MF-LF MF-LF
29 mA AG28 +V_PLL_FSB CPU_INTR AF42 CPU_INTR 150
402
2 2
402

15 mA AH28 +V_PLL_CPU CPU_NMI AG41 CPU_NMI


OUT 10 69

10 69
5%
1/16W
MCP CPU Interface
OUT
MF-LF
CPU_SMI# AH41 CPU_SMI_L
A 69 MCP_BCLK_VML_COMP_VDD AM39 BCLK_VML_COMP_VDD
CPU_PWRGD AH43 CPU_PWRGD
OUT 10 69
2
402

10 13 69
SYNC_MASTER=K36B_MLB

NOTICE OF PROPRIETARY PROPERTY


SYNC_DATE=08/17/2008
A
MCP_BCLK_VML_COMP_GND AM40 OUT
69 BCLK_VML_COMP_GND
CPU_RESET# H38 FSB_CPURST_L OUT 10 13 69
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
69 MCP_CPU_COMP_VCC AM43 CPU_COMP_VCC CPU_SLP# AM33 FSB_CPUSLP_L OUT 10 69 AGREES TO THE FOLLOWING
69 MCP_CPU_COMP_GND AM42 CPU_COMP_GND CPU_DPSLP# AN33 CPU_DPSLP_L OUT 10 69 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
R1431 1
1
R1436 CPU_DPWR# AM32 FSB_DPWR_L OUT 10 69 II NOT TO REPRODUCE OR COPY IT
49.9 49.9
1% 1% CPU_STPCLK# AG42 CPU_STPCLK_L OUT 10 69 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
1/16W 1/16W
MF-LF MF-LF CPU_DPRSTP# AN32 CPU_DPRSTP_L OUT 10 60 69
402
2 2
402 SIZE DRAWING NUMBER REV.

D 051-8089 02

APPLE INC. SCALE SHT OF


14 109
NONE

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

OMIT OMIT
U1400 U1400
MCP79-TOPO-B MCP79-TOPO-B
BGA BGA
(2 OF 11) (3 OF 11)

70 28 BI MEM_A_DQ<63> AL8 MDQ0_63 MDQS0_7_P AL10 MEM_A_DQS_P<7> BI 28 70 70 29 BI MEM_B_DQ<63> AT4 MDQ1_63 MDQS1_7_P AT2 MEM_B_DQS_P<7> BI 29 70

70 28 BI MEM_A_DQ<62> AL9 MDQ0_62 MDQS0_7_N AL11 MEM_A_DQS_N<7> BI 28 70 70 29 BI MEM_B_DQ<62> AT3 MDQ1_62 MDQS1_7_N AT1 MEM_B_DQS_N<7> BI 29 70

70 28 BI MEM_A_DQ<61> AP9 MDQ0_61 MDQS0_6_P AR8 MEM_A_DQS_P<6> BI 28 70 70 29 BI MEM_B_DQ<61> AV2 MDQ1_61 MDQS1_6_P AY2 MEM_B_DQS_P<6> BI 29 70

70 28 BI MEM_A_DQ<60> AN9 MDQ0_60 MDQS0_6_N AR9 MEM_A_DQS_N<6> BI 28 70 70 29 BI MEM_B_DQ<60> AV3 MDQ1_60 MDQS1_6_N AY1 MEM_B_DQS_N<6> BI 29 70

D 70 28

70 28
BI
BI
MEM_A_DQ<59>
MEM_A_DQ<58>
AL6

AL7
MDQ0_59
MDQ0_58
MDQS0_5_P
MDQS0_5_N
AW7

AW8
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
BI
BI
28 70

28 70
70 29

70 29
BI
BI
MEM_B_DQ<59>
MEM_B_DQ<58>
AR4

AR3
MDQ1_59
MDQ1_58
MDQS1_5_P
MDQS1_5_N
BB6

BA6
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
BI
BI
29 70

29 70
D
70 28 BI MEM_A_DQ<57> AN6 MDQ0_57 MDQS0_4_P AP13 MEM_A_DQS_P<4> BI 28 70 70 29 BI MEM_B_DQ<57> AU2 MDQ1_57 MDQS1_4_P BA10 MEM_B_DQS_P<4> BI 29 70

70 28 BI MEM_A_DQ<56> AN7 MDQ0_56 MDQS0_4_N AR13 MEM_A_DQS_N<4> BI 28 70 70 29 BI MEM_B_DQ<56> AU3 MDQ1_56 MDQS1_4_N AY11 MEM_B_DQS_N<4> BI 29 70

70 28 BI MEM_A_DQ<55> AR6 MDQ0_55 MDQS0_3_P AV25 MEM_A_DQS_P<3> BI 28 70 70 29 BI MEM_B_DQ<55> AY4 MDQ1_55 MDQS1_3_P BB33 MEM_B_DQS_P<3> BI 29 70

70 28 BI MEM_A_DQ<54> AR7 MDQ0_54 MDQS0_3_N AW25 MEM_A_DQS_N<3> BI 28 70 70 29 BI MEM_B_DQ<54> AY3 MDQ1_54 MDQS1_3_N BA33 MEM_B_DQS_N<3> BI 29 70

70 28 BI MEM_A_DQ<53> AV6 MDQ0_53 MDQS0_2_P AU30 MEM_A_DQS_P<2> BI 28 70 70 29 BI MEM_B_DQ<53> BB3 MDQ1_53 MDQS1_2_P BB37 MEM_B_DQS_P<2> BI 29 70

70 28 BI MEM_A_DQ<52> AW5 MDQ0_52 MDQS0_2_N AU29 MEM_A_DQS_N<2> BI 28 70 70 29 BI MEM_B_DQ<52> BC3 MDQ1_52 MDQS1_2_N BA37 MEM_B_DQS_N<2> BI 29 70

70 28 BI MEM_A_DQ<51> AN10 MDQ0_51 MDQS0_1_P AT35 MEM_A_DQS_P<1> BI 28 70 70 29 BI MEM_B_DQ<51> AW4 MDQ1_51 MDQS1_1_P BA43 MEM_B_DQS_P<1> BI 29 70

70 28 BI MEM_A_DQ<50> AR5 MDQ0_50 MDQS0_1_N AU35 MEM_A_DQS_N<1> BI 28 70 70 29 BI MEM_B_DQ<50> AW3 MDQ1_50 MDQS1_1_N AY42 MEM_B_DQS_N<1> BI 29 70

70 28 BI MEM_A_DQ<49> AU6 MDQ0_49 MDQS0_0_P AU39 MEM_A_DQS_P<0> BI 28 70 70 29 BI MEM_B_DQ<49> BA3 MDQ1_49 MDQS1_0_P AT42 MEM_B_DQS_P<0> BI 29 70

70 28 BI MEM_A_DQ<48> AV5 MDQ0_48 MDQS0_0_N AT39 MEM_A_DQS_N<0> BI 28 70 70 29 BI MEM_B_DQ<48> BB2 MDQ1_48 MDQS1_0_N AT43 MEM_B_DQS_N<0> BI 29 70

70 28 BI MEM_A_DQ<47> AU7 MDQ0_47 70 29 BI MEM_B_DQ<47> BB5 MDQ1_47


70 28 BI MEM_A_DQ<46> AU8 MDQ0_46 70 29 BI MEM_B_DQ<46> BA5 MDQ1_46

MEMORY PARTITION 0

MEMORY PARTITION 1
70 28 BI MEM_A_DQ<45> AW9 MDQ0_45 70 29 BI MEM_B_DQ<45> BA8 MDQ1_45
70 28 BI MEM_A_DQ<44> AP11 MDQ0_44 70 29 BI MEM_B_DQ<44> BC8 MDQ1_44
70 28 BI MEM_A_DQ<43> AW6 MDQ0_43 70 29 BI MEM_B_DQ<43> BB4 MDQ1_43
70 28 BI MEM_A_DQ<42> AY5 MDQ0_42 MRAS0# AV17 MEM_A_RAS_L OUT 28 30 70 70 29 BI MEM_B_DQ<42> BC4 MDQ1_42 MRAS1# AW16 MEM_B_RAS_L OUT 29 30 70

70 28 BI MEM_A_DQ<41> AU9 MDQ0_41 MCAS0# AP17 MEM_A_CAS_L OUT 28 30 70 70 29 BI MEM_B_DQ<41> BA7 MDQ1_41 MCAS1# BA15 MEM_B_CAS_L OUT 29 30 70

70 28 BI MEM_A_DQ<40> AV9 MDQ0_40 MWE0# AR17 MEM_A_WE_L OUT 28 30 70 70 29 BI MEM_B_DQ<40> AY8 MDQ1_40 MWE1# BA16 MEM_B_WE_L OUT 29 30 70

70 28 BI MEM_A_DQ<39> AU11 MDQ0_39 70 29 BI MEM_B_DQ<39> BA9 MDQ1_39


70 28 BI MEM_A_DQ<38> AV11 MDQ0_38 70 29 BI MEM_B_DQ<38> BB10 MDQ1_38
70 28 BI MEM_A_DQ<37> AV13 MDQ0_37 70 29 BI MEM_B_DQ<37> BB12 MDQ1_37
70 28 BI MEM_A_DQ<36> AW13 MDQ0_36 70 29 BI MEM_B_DQ<36> AW12 MDQ1_36
70 28 BI MEM_A_DQ<35> AR11 MDQ0_35 70 29 BI MEM_B_DQ<35> BB8 MDQ1_35
70 28 BI MEM_A_DQ<34> AT11 MDQ0_34 MBA0_2 AP23 MEM_A_BA<2> OUT 28 30 70 70 29 BI MEM_B_DQ<34> BB9 MDQ1_34 MBA1_2 BB29 MEM_B_BA<2> OUT 29 30 70

70 28 BI MEM_A_DQ<33> AR14 MDQ0_33 MBA0_1 AP19 MEM_A_BA<1> OUT 28 30 70 70 29 BI MEM_B_DQ<33> AY12 MDQ1_33 MBA1_1 BB18 MEM_B_BA<1> OUT 29 30 70

C 70 28

70 28
BI MEM_A_DQ<32>
MEM_A_DQ<31>
AU13

AR26
MDQ0_32
MDQ0_31
MBA0_0 AW17 MEM_A_BA<0> OUT 28 30 70 70 29

70 29
BI MEM_B_DQ<32>
MEM_B_DQ<31>
BA12

BC32
MDQ1_32
MDQ1_31
MBA1_0 BB17 MEM_B_BA<0> OUT 29 30 70 C
BI BI
70 28 BI MEM_A_DQ<30> AU25 MDQ0_30 70 29 BI MEM_B_DQ<30> AW32 MDQ1_30
70 28 BI MEM_A_DQ<29> AT27 MDQ0_29 70 29 BI MEM_B_DQ<29> BA35 MDQ1_29
70 28 BI MEM_A_DQ<28> AU27 MDQ0_28 70 29 BI MEM_B_DQ<28> AY36 MDQ1_28
70 28 BI MEM_A_DQ<27> AP25 MDQ0_27 70 29 BI MEM_B_DQ<27> BA32 MDQ1_27
MA0_14 AR23 MEM_A_A<14> OUT 28 30 70 MA1_14 BA29 MEM_B_A<14> OUT 29 30 70
70 28 BI MEM_A_DQ<26> AR25 MDQ0_26 70 29 BI MEM_B_DQ<26> BB32 MDQ1_26
MA0_13 AU15 MEM_A_A<13> OUT 28 30 70 MA1_13 BA14 MEM_B_A<13> OUT 29 30 70
70 28 BI MEM_A_DQ<25> AP27 MDQ0_25 70 29 BI MEM_B_DQ<25> BA34 MDQ1_25
MA0_12 AN23 MEM_A_A<12> OUT 28 30 70 MA1_12 AW28 MEM_B_A<12> OUT 29 30 70
70 28 BI MEM_A_DQ<24> AR27 MDQ0_24 70 29 BI MEM_B_DQ<24> AY35 MDQ1_24
MA0_11 AW21 MEM_A_A<11> OUT 28 30 70 MA1_11 BC28 MEM_B_A<11> OUT 29 30 70
70 28 BI MEM_A_DQ<23> AP29 MDQ0_23 70 29 BI MEM_B_DQ<23> BC36 MDQ1_23
MA0_10 AN19 MEM_A_A<10> OUT 28 30 70 MA1_10 BA17 MEM_B_A<10> OUT 29 30 70
70 28 BI MEM_A_DQ<22> AR29 MDQ0_22 70 29 BI MEM_B_DQ<22> AW36 MDQ1_22
MA0_9 AV21 MEM_A_A<9> OUT 28 30 70 MA1_9 BB28 MEM_B_A<9> OUT 29 30 70
70 28 BI MEM_A_DQ<21> AP31 MDQ0_21 70 29 BI MEM_B_DQ<21> BA39 MDQ1_21
MA0_8 AR22 MEM_A_A<8> OUT 28 30 70 MA1_8 AY28 MEM_B_A<8> OUT 29 30 70
70 28 BI MEM_A_DQ<20> AR31 MDQ0_20 70 29 BI MEM_B_DQ<20> AY40 MDQ1_20
MA0_7 AU21 MEM_A_A<7> OUT 28 30 70 MA1_7 BA28 MEM_B_A<7> OUT 29 30 70
70 28 BI MEM_A_DQ<19> AV27 MDQ0_19 70 29 BI MEM_B_DQ<19> BA36 MDQ1_19
MA0_6 AP21 MEM_A_A<6> OUT 28 30 70 MA1_6 AY27 MEM_B_A<6> OUT 29 30 70
70 28 BI MEM_A_DQ<18> AN29 MDQ0_18 70 29 BI MEM_B_DQ<18> BB36 MDQ1_18
MA0_5 AR21 MEM_A_A<5> OUT 28 30 70 MA1_5 BA27 MEM_B_A<5> OUT 29 30 70
70 28 BI MEM_A_DQ<17> AV29 MDQ0_17 70 29 BI MEM_B_DQ<17> BA38 MDQ1_17
MA0_4 AN21 MEM_A_A<4> OUT 28 30 70 MA1_4 BA26 MEM_B_A<4> OUT 29 30 70
70 28 BI MEM_A_DQ<16> AN31 MDQ0_16 70 29 BI MEM_B_DQ<16> AY39 MDQ1_16
MA0_3 AV19 MEM_A_A<3> OUT 28 30 70 MA1_3 BB26 MEM_B_A<3> OUT 29 30 70
70 28 BI MEM_A_DQ<15> AU31 MDQ0_15 70 29 BI MEM_B_DQ<15> BB40 MDQ1_15
MA0_2 AU19 MEM_A_A<2> OUT 28 30 70 MA1_2 BA25 MEM_B_A<2> OUT 29 30 70
70 28 BI MEM_A_DQ<14> AR33 MDQ0_14 70 29 BI MEM_B_DQ<14> AW40 MDQ1_14
MA0_1 AT19 MEM_A_A<1> OUT 28 30 70 MA1_1 BB25 MEM_B_A<1> OUT 29 30 70
70 28 BI MEM_A_DQ<13> AV37 MDQ0_13 70 29 BI MEM_B_DQ<13> AV42 MDQ1_13
MA0_0 AR19 MEM_A_A<0> OUT 28 30 70 MA1_0 BA18 MEM_B_A<0> OUT 29 30 70
70 28 BI MEM_A_DQ<12> AW37 MDQ0_12 70 29 BI MEM_B_DQ<12> AV41 MDQ1_12
70 28 BI MEM_A_DQ<11> AT31 MDQ0_11 70 29 BI MEM_B_DQ<11> BA40 MDQ1_11
70 28 BI MEM_A_DQ<10> AV31 MDQ0_10 70 29 BI MEM_B_DQ<10> BC40 MDQ1_10
MEM_A_DQ<9> AT37
MEMORY MEM_B_DQ<9> AW42
MEMORY
70 28 BI MDQ0_9 70 29 BI MDQ1_9
MEM_A_DQ<8> AU37
CONTROL MEM_B_DQ<8> AW41
CONTROL
70 28 BI MDQ0_8 70 29 BI MDQ1_8
MEM_A_DQ<7> AW39
0A MEM_B_DQ<7> AT40
1A
70 28 BI MDQ0_7 70 29 BI MDQ1_7
MCLK0A_2_P AW33 TP_MEM_A_CLK2P MCLK1A_2_P BA42 TP_MEM_B_CLK2P
B 70 28

70 28
BI
BI
MEM_A_DQ<6>
MEM_A_DQ<5>
AV39
AR37
MDQ0_6
MDQ0_5
MCLK0A_2_N AV33 TP_MEM_A_CLK2N
70 29

70 29
BI
BI
MEM_B_DQ<6>
MEM_B_DQ<5>
AT41
AP41
MDQ1_6
MDQ1_5
MCLK1A_2_N BB42 TP_MEM_B_CLK2N B
70 28 BI MEM_A_DQ<4> AR38 MDQ0_4 MCLK0A_1_P BA24 MEM_A_CLK_P<1> OUT 28 70 70 29 BI MEM_B_DQ<4> AN40 MDQ1_4 MCLK1A_1_P BB22 MEM_B_CLK_P<1> OUT 29 70

70 28 BI MEM_A_DQ<3> AV38 MDQ0_3 MCLK0A_1_N AY24 MEM_A_CLK_N<1> OUT 28 70 70 29 BI MEM_B_DQ<3> AU40 MDQ1_3 MCLK1A_1_N BA22 MEM_B_CLK_N<1> OUT 29 70

70 28 BI MEM_A_DQ<2> AW38 MDQ0_2 70 29 BI MEM_B_DQ<2> AU41 MDQ1_2


MCLK0A_0_P BB20 MEM_A_CLK_P<0> OUT 28 70 MCLK1A_0_P BA19 MEM_B_CLK_P<0> OUT 29 70
70 28 BI MEM_A_DQ<1> AR35 MDQ0_1 70 29 BI MEM_B_DQ<1> AR41 MDQ1_1
MCLK0A_0_N BC20 MEM_A_CLK_N<0> OUT 28 70 MCLK1A_0_N AY19 MEM_B_CLK_N<0> OUT 29 70
70 28 BI MEM_A_DQ<0> AP35 MDQ0_0 70 29 BI MEM_B_DQ<0> AP42 MDQ1_0

70 28 OUT MEM_A_DM<7> AN5 MDQM0_7 MCS0A_1# AT15 MEM_A_CS_L<1> OUT 28 30 70 70 29 OUT MEM_B_DM<7> AT5 MDQM1_7 MCS1A_1# BB14 MEM_B_CS_L<1> OUT 29 30 70

70 28 OUT MEM_A_DM<6> AU5 MDQM0_6 MCS0A_0# AR18 MEM_A_CS_L<0> OUT 28 30 70 70 29 OUT MEM_B_DM<6> BA2 MDQM1_6 MCS1A_0# BB16 MEM_B_CS_L<0> OUT 29 30 70

70 28 OUT MEM_A_DM<5> AR10 MDQM0_5 70 29 OUT MEM_B_DM<5> AY7 MDQM1_5


70 28 OUT MEM_A_DM<4> AN13 MDQM0_4 MODT0A_1 AP15 MEM_A_ODT<1> OUT 28 30 70 70 29 OUT MEM_B_DM<4> BA11 MDQM1_4 MODT1A_1 BB13 MEM_B_ODT<1> OUT 29 30 70

70 28 OUT MEM_A_DM<3> AN27 MDQM0_3 MODT0A_0 AV15 MEM_A_ODT<0> OUT 28 30 70 70 29 OUT MEM_B_DM<3> BB34 MDQM1_3 MODT1A_0 AY15 MEM_B_ODT<0> OUT 29 30 70

70 28 OUT MEM_A_DM<2> AW29 MDQM0_2 70 29 OUT MEM_B_DM<2> BB38 MDQM1_2


70 28 OUT MEM_A_DM<1> AV35 MDQM0_1 MCKE0A_1 AU23 MEM_A_CKE<1> OUT 28 30 70 70 29 OUT MEM_B_DM<1> AY43 MDQM1_1 MCKE1A_1 AY31 MEM_B_CKE<1> OUT 29 30 70

70 28 OUT MEM_A_DM<0> AR34 MDQM0_0 MCKE0A_0 AT23 MEM_A_CKE<0> OUT 28 30 70 70 29 OUT MEM_B_DM<0> AR42 MDQM1_0 MCKE1A_0 BB30 MEM_B_CKE<0> OUT 29 30 70

MCP Memory Interface


A SYNC_MASTER=K36B_MLB

NOTICE OF PROPRIETARY PROPERTY


SYNC_DATE=08/17/2008
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-8089 02

APPLE INC. SCALE SHT OF


15 109
NONE

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

OMIT
U1400
MCP79-TOPO-B
BGA
(4 OF 11)

TP_MEM_A_CLK5P AU33 MCLK0B_2_P MCLK1B_2_P BA41 TP_MEM_B_CLK5P

MEMORY CONTROL 0B
MEMORY CONTROL 1B
TP_MEM_A_CLK5N AU34 MCLK0B_2_N MCLK1B_2_N BB41 TP_MEM_B_CLK5N
D TP_MEM_A_CLK4P BB24 MCLK0B_1_P MCLK1B_1_P AY23 TP_MEM_B_CLK4P
TP_MEM_A_CLK4N BC24 MCLK0B_1_N MCLK1B_1_N BA23 TP_MEM_B_CLK4N

TP_MEM_A_CLK3P BA21 MCLK0B_0_P MCLK1B_0_P BA20 TP_MEM_B_CLK3P


TP_MEM_A_CLK3N BB21 MCLK0B_0_N MCLK1B_0_N AY20 TP_MEM_B_CLK3N

TP_MEM_A_CS_L<2> AU17 MCS0B_0# MCS1B_0# BC16 TP_MEM_B_CS_L<2>


TP_MEM_A_CS_L<3> AR15 MCS0B_1# MCS1B_1# BA13 TP_MEM_B_CS_L<3>

TP_MEM_A_ODT<2> AN17 MODT0B_0 MODT1B_0 AY16 TP_MEM_B_ODT<2>


TP_MEM_A_ODT<3> AN15 MODT0B_1 MODT1B_1 BC13 TP_MEM_B_ODT<3>

TP_MEM_A_CKE<2> AV23 MCKE0B_0 MCKE1B_0 BA30 TP_MEM_B_CKE<2>


TP_MEM_A_CKE<3> AN25 MCKE0B_1 MCKE1B_1 BA31 TP_MEM_B_CKE<3>

24 PP1V05_S0_MCP_PLL_CORE
24 16 8 =PP1V8R1V5_S0_MCP_MEM
87 mA (A01) 17 mA T27 +V_PLL_XREF_XS
12 mA U28 +V_PLL_DP
R1610 1 19 mA U27 +V_PLL_CORE
40.2 MRESET0# AY32 MCP_MEM_RESET_L 9
1% 39 mA T28 +V_VPLL
1/16W TP or NC for DDR2.
MF-LF
402
2

70 MCP_MEM_COMP_VDD AN41 MEM_COMP_VDD


70 MCP_MEM_COMP_GND AM41 MEM_COMP_GND =PP1V8R1V5_S0_MCP_MEM 8 16 24

+VDD_MEM1 AM17 4771 MA (A01, DDR2)


R1611 1 +VDD_MEM2 AM19

C 40.2
1%
1/16W
MF-LF
AA22

AP12
GND1
GND2
+VDD_MEM3
+VDD_MEM4
AM21

AM23
C
402
2 G30 AM25
GND3 +VDD_MEM5
P10 GND4 +VDD_MEM6 AM27

T10 GND5 +VDD_MEM7 AM29

T6 GND6 +VDD_MEM8 AN16

V10 GND7 +VDD_MEM9 BC29

V34 GND8 +VDD_MEM10 AN20

W5 GND9 +VDD_MEM11 AN24

AA39 GND10 +VDD_MEM12 AT17

AB22 GND11 +VDD_MEM13 AP16


AB7 GND12 +VDD_MEM14 AN22

AD22 GND13 +VDD_MEM15 AP20

AE20 GND14 +VDD_MEM16 AP24


AF24 GND15 +VDD_MEM17 AV16

AG24 GND16 +VDD_MEM18 AR16


AH35 GND17 +VDD_MEM19 AR20

AK7 GND18 +VDD_MEM20 AR24

AM28 GND19 +VDD_MEM21 AW15


AT25 GND20 +VDD_MEM22 AP22

AP30 GND21 +VDD_MEM23 AP18

AR36 GND22 +VDD_MEM24 AU16


AU10 GND23 +VDD_MEM25 AN18

F28 GND24 +VDD_MEM26 AU24

BC21 GND25 +VDD_MEM27 AT21


AY9 GND26 +VDD_MEM28 AY29

B BC9

D34
GND27
GND28
+VDD_MEM29
+VDD_MEM30
AV24
AU20
B
F24 GND29 +VDD_MEM31 AU22

G32 GND30 +VDD_MEM32 AW27


H31 GND31 +VDD_MEM33 BC17

K7 GND32 +VDD_MEM34 AV20

M38 GND33 +VDD_MEM35 AY17


M5 GND34 +VDD_MEM36 AY18

M6 GND35 +VDD_MEM37 AM15

M7 GND36 +VDD_MEM38 AU18

M9 GND37 +VDD_MEM39 AY25

N39 GND38 +VDD_MEM40 AY26


N8 GND39 +VDD_MEM41 AW19

P33 GND40 +VDD_MEM42 AW24

P34 GND41 +VDD_MEM43 BC25


P37 GND42 +VDD_MEM44 AL30

P4 GND43 +VDD_MEM45 AM31

P40 GND44
P7 GND45 GND55 T33

R36 GND46 GND56 T34

R40 GND47 GND57 T35


R43 GND48 GND58 T37

R5 GND49 GND59 T38


T18 GND50 GND60 T7

T20 GND51 GND61 T9 MCP Memory Misc


AK11 GND52 GND62 U18

A T24

T26
GND53
GND54
GND63
GND64
U20

U22
SYNC_MASTER=K36B_MLB

NOTICE OF PROPRIETARY PROPERTY


SYNC_DATE=08/17/2008
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-8089 02

APPLE INC. SCALE SHT OF


NONE 16 109
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT
U1400
MCP79-TOPO-B
BGA
(5 OF 11)

9 IN =PEG_D2R_P<0> F7 PE0_RX0_P PE0_TX0_P C5 =PEG_R2D_C_P<0> OUT 9

9 IN =PEG_D2R_N<0> E7 PE0_RX0_N PE0_TX0_N D4 =PEG_R2D_C_N<0> OUT 9

9 IN =PEG_D2R_P<1> D7 PE0_RX1_P PE0_TX1_P C4 =PEG_R2D_C_P<1> OUT 9

9 IN =PEG_D2R_N<1> C7 PE0_RX1_N PE0_TX1_N B4 =PEG_R2D_C_N<1> OUT 9

9 IN =PEG_D2R_P<2> E6 PE0_RX2_P PE0_TX2_P A4 =PEG_R2D_C_P<2> OUT 9

9 IN =PEG_D2R_N<2> F6 PE0_RX2_N PE0_TX2_N A3 =PEG_R2D_C_N<2> OUT 9

9 =PEG_D2R_P<3> E5 PE0_RX3_P PE0_TX3_P B3 =PEG_R2D_C_P<3> 9

D 9
IN
IN =PEG_D2R_N<3> F5 PE0_RX3_N PE0_TX3_N B2 =PEG_R2D_C_N<3>
OUT
OUT 9 D
9 IN =PEG_D2R_P<4> E4 PE0_RX4_P PE0_TX4_P C1 =PEG_R2D_C_P<4> OUT 9

9 IN =PEG_D2R_N<4> E3 PE0_RX4_N PE0_TX4_N D1 =PEG_R2D_C_N<4> OUT 9

9 IN =PEG_D2R_P<5> C3 PE0_RX5_P PE0_TX5_P D2 =PEG_R2D_C_P<5> OUT 9

9 IN =PEG_D2R_N<5> D3 PE0_RX5_N PE0_TX5_N E1 =PEG_R2D_C_N<5> OUT 9

9 IN =PEG_D2R_P<6> G5 PE0_RX6_P PE0_TX6_P E2 =PEG_R2D_C_P<6> OUT 9

9 IN =PEG_D2R_N<6> H5 PE0_RX6_N PE0_TX6_N F2 =PEG_R2D_C_N<6> OUT 9

9 IN =PEG_D2R_P<7> J7 PE0_RX7_P PE0_TX7_P F3 =PEG_R2D_C_P<7> OUT 9

PCI EXPRESS
9 IN =PEG_D2R_N<7> J6 PE0_RX7_N PE0_TX7_N F4 =PEG_R2D_C_N<7> OUT 9

9 IN =PEG_D2R_P<8> J5 PE0_RX8_P PE0_TX8_P G3 =PEG_R2D_C_P<8> OUT 9

9 IN =PEG_D2R_N<8> J4 PE0_RX8_N PE0_TX8_N H4 =PEG_R2D_C_N<8> OUT 9

9 IN =PEG_D2R_P<9> L11 PE0_RX9_P PE0_TX9_P H3 =PEG_R2D_C_P<9> OUT 9

9 IN =PEG_D2R_N<9> L10 PE0_RX9_N PE0_TX9_N H2 =PEG_R2D_C_N<9> OUT 9

9 IN =PEG_D2R_P<10> L9 PE0_RX10_P PE0_TX10_P H1 =PEG_R2D_C_P<10> OUT 9

9 IN =PEG_D2R_N<10> L8 PE0_RX10_N PE0_TX10_N J1 =PEG_R2D_C_N<10> OUT 9

9 IN =PEG_D2R_P<11> L7 PE0_RX11_P PE0_TX11_P J2 =PEG_R2D_C_P<11> OUT 9

9 IN =PEG_D2R_N<11> L6 PE0_RX11_N PE0_TX11_N J3 =PEG_R2D_C_N<11> OUT 9

9 IN =PEG_D2R_P<12> N11 PE0_RX12_P PE0_TX12_P K2 =PEG_R2D_C_P<12> OUT 9

9 IN =PEG_D2R_N<12> N10 PE0_RX12_N PE0_TX12_N K3 =PEG_R2D_C_N<12> OUT 9

9 IN =PEG_D2R_P<13> N9 PE0_RX13_P PE0_TX13_P L4 =PEG_R2D_C_P<13> OUT 9

9 IN =PEG_D2R_N<13> P9 PE0_RX13_N PE0_TX13_N L3 =PEG_R2D_C_N<13> OUT 9

9 IN =PEG_D2R_P<14> N7 PE0_RX14_P PE0_TX14_P M4 =PEG_R2D_C_P<14> OUT 9

9 IN =PEG_D2R_N<14> N6 PE0_RX14_N PE0_TX14_N M3 =PEG_R2D_C_N<14> OUT 9

9 IN =PEG_D2R_P<15> N5 PE0_RX15_P PE0_TX15_P M2 =PEG_R2D_C_P<15> OUT 9

9 IN =PEG_D2R_N<15> N4 PE0_RX15_N PE0_TX15_N M1 =PEG_R2D_C_N<15> OUT 9

C 9 IN PEG_PRSNT_L C9
Int PU
PE0_PRSNT_16#
PE0_REFCLK_P
PE0_REFCLK_N
E11

D11
PEG_CLK100M_P
PEG_CLK100M_N
OUT
OUT
9 71

9 71
C
Int PU
31 7 IN MINI_CLKREQ_L D5 PEB_CLKREQ#/GPIO_49 PE1_REFCLK_P G11 PCIE_CLK100M_MINI_P OUT 7 31 71

31 IN PCIE_MINI_PRSNT_L D9 PEB_PRSNT# Int PU PE1_REFCLK_N F11 PCIE_CLK100M_MINI_N OUT 7 31 71

Int PU
35 IN FW_CLKREQ_L E8 PEC_CLKREQ#/GPIO_50 PE2_REFCLK_P J11 PCIE_CLK100M_FW_P OUT 35 71

9 IN PCIE_FW_PRSNT_L C10 PEC_PRSNT# Int PU PE2_REFCLK_N J10 PCIE_CLK100M_FW_N OUT 35 71

Int PU
9 IN EXCARD_CLKREQ_L M15 PED_CLKREQ#/GPIO_51 PE3_REFCLK_P G13 PCIE_CLK100M_EXCARD_P OUT 9 71

9 IN PCIE_EXCARD_PRSNT_L B10 PED_PRSNT# Int PU PE3_REFCLK_N F13 PCIE_CLK100M_EXCARD_N OUT 9 71

Int PU
TP_PE4_CLKREQ_L L16 PEE_CLKREQ#/GPIO_16 PE4_REFCLK_P J13 TP_PCIE_CLK100M_PE4P
TP_PE4_PRSNT_L L18 PEE_PRSNT#/GPIO_46 PE4_REFCLK_N H13 TP_PCIE_CLK100M_PE4N
Int PU
Int PU
TP_MCP_GPIO_17 M16 PEF_CLKREQ#/GPIO_17 PE5_REFCLK_P L14 TP_PCIE_CLK100M_PE5P
9 OUT EXTGPU_PWR_EN M18 PEF_PRSNT#/GPIO_47 PE5_REFCLK_N K14 TP_PCIE_CLK100M_PE5N
Int PU
Int PU
9 IN PEG_CLKREQ_L M17 PEG_CLKREQ#/GPIO_18 PE6_REFCLK_P N14 TP_PCIE_CLK100M_PE6P
9 OUT EXTGPU_RESET_L M19 PEG_PRSNT#/GPIO_48 PE6_REFCLK_N M14 TP_PCIE_CLK100M_PE6N
Int PU
31 7 IN PCIE_WAKE_L F17 PE_WAKE# Int PU (S5) PEX_RST0# K11 PCIE_RESET_L OUT 26

71 31 7 IN PCIE_MINI_D2R_P K9 PE1_RX0_P PE1_TX0_P D8 PCIE_MINI_R2D_C_P OUT 31 71

71 31 7 IN PCIE_MINI_D2R_N J9 PE1_RX0_N PE1_TX0_N C8 PCIE_MINI_R2D_C_N OUT 31 71

71 35 IN PCIE_FW_D2R_P H9 PE1_RX1_P PE1_TX1_P B8 PCIE_FW_R2D_C_P OUT 35 71

B 71 35 IN PCIE_FW_D2R_N G9 PE1_RX1_N PE1_TX1_N A8 PCIE_FW_R2D_C_N OUT 35 71


B
71 9 IN PCIE_EXCARD_D2R_P F9 PE1_RX2_P PE1_TX2_P A7 PCIE_EXCARD_R2D_C_P OUT 9 71

71 9 IN PCIE_EXCARD_D2R_N E9 PE1_RX2_N PE1_TX2_N B7 PCIE_EXCARD_R2D_C_N OUT 9 71

TP_PCIE_PE4_D2RP H7 PE1_RX3_P PE1_TX3_P B6 TP_PCIE_PE4_R2D_CP


TP_PCIE_PE4_D2RN G7 PE1_RX3_N PE1_TX3_N C6 TP_PCIE_PE4_R2D_CN

8 =PP1V05_S0_MCP_PEX_DVDD0
T17 +DVDD0_PEX1 +AVDD0_PEX1 Y12 =PP1V05_S0_MCP_PEX_AVDD0 8

W19 +DVDD0_PEX2 +AVDD0_PEX2 AA12

U17 +DVDD0_PEX3 +AVDD0_PEX3 AB12

V19 +DVDD0_PEX4 +AVDD0_PEX4 M12

W16 +DVDD0_PEX5 +AVDD0_PEX5 P12

W17 +DVDD0_PEX6 +AVDD0_PEX6 R12

W18 +DVDD0_PEX7 +AVDD0_PEX7 N12


U16 +DVDD0_PEX8 +AVDD0_PEX8 T12

+AVDD0_PEX9 U12

8 =PP1V05_S0_MCP_PEX_DVDD1 T19 +DVDD1_PEX1 +AVDD0_PEX10 AC12

U19 +DVDD1_PEX2 +AVDD0_PEX11 AD12

+AVDD0_PEX12 V12

+AVDD0_PEX13 W12

24 PP1V05_S0_MCP_PLL_PEX T16 +V_PLL_PEX


84 mA (A01) +AVDD1_PEX1 M13 =PP1V05_S0_MCP_PEX_AVDD1 8

+AVDD1_PEX2 N13

71 MCP_PEX_CLK_COMP A11 PEX_CLK_COMP +AVDD1_PEX3 P13 MCP PCIe Interfaces


NO STUFF
A 1
R1710
2.37K
SYNC_MASTER=K36B_MLB

NOTICE OF PROPRIETARY PROPERTY


SYNC_DATE=08/17/2008
A
1%
1/16W
MF-LF THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
2
402 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
PLACEMENT_NOTE=Place within 12.7mm of U1400 IF PE0 INTERFACE IS NOT USED, GROUND DVDD0_PEX AND AVDD0_PEX.
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
IF PE1 INTERFACE IS NOT USED, GROUND DVDD1_PEX AND AVDD1_PEX
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-8089 02

APPLE INC. SCALE SHT OF


17 109
NONE

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

OMIT
U1400
MCP79-TOPO-B
BGA
(6 OF 11) =PP3V3_ENET_MCP_RMGT 8 18 24

+3.3V_DUAL_RMGT1 J24 83 mA (A01)


+3.3V_DUAL_RMGT2 K24

LAN
D +V_DUAL_RMGT1 U23
=PP1V05_ENET_MCP_RMGT 8 24

131 mA (A01)
+V_DUAL_RMGT2 V23

32 IN ENET_RXD<0> C23 RGMII_RXD0 Network Interface Select


73 32 IN ENET_RXD<1> B23 RGMII_RXD1 MII_VREF E28 MCP_MII_VREF IN 24

73 32 IN ENET_RXD<2> E24 RGMII_RXD2


B24 ENET_TXD<0>
Interface ENET_TXD<0>
RGMII_TXD0 OUT 32 73
73 32 IN ENET_RXD<3> A24 RGMII_RXD3
RGMII_TXD1 C24 ENET_TXD<1> OUT 32 73

ENET_CLK125M_RXCLK A23 C25 ENET_TXD<2>


RGMII 1
73 32 IN RGMII_RXC/MII_RXCLK RGMII_TXD2 OUT 32 73

73 32 IN ENET_RX_CTRL C22 RGMII_RXCTL/MII_RXDV RGMII_TXD3 D25 ENET_TXD<3> OUT 32 73


MII 0
9 IN MCP_MII_RXER F23 MII_RXER/GPIO_36 RGMII_TXC/MII_TXCLK D24 ENET_CLK125M_TXCLK OUT 32 73

9 IN MCP_MII_COL B26 MII_COL/GPIO_20/MSMB_DATA RGMII_TXCTL/MII_TXEN C26 ENET_TX_CTRL OUT 32 73 NOTE: All Apple products set strap to
24 18 8 =PP3V3_ENET_MCP_RMGT
9 IN MCP_MII_CRS B22 MII_CRS/GPIO_21/MSMB_CLK MII, RGMII products will enable
RGMII_MDC D21 ENET_MDC OUT 32 73
feature via software. This
R1810 1 TP_ENET_INTR_L J22 RGMII_INTR/GPIO_35 RGMII_MDIO C21 ENET_MDIO BI 32 73
avoids a leakage issue since
49.9
1% RGMII_PWRDWN/GPIO_37 G23 TP_ENET_PWRDWN_L MCP79 requires a S5 pull-up.
1/16W
MF-LF 24 PP1V05_ENET_MCP_PLL_MAC T23 +V_DUAL_MACPLL
402
2 5 mA (A01) BUF_25MHZ E23 MCP_CLK25M_BUF0_R 33 73
OUT
73 MCP_MII_COMP_VDD C27 MII_COMP_VDD =PP3V3_S0_MCP_GPIO 8 19 21

73 MCP_MII_COMP_GND B27 MII_COMP_GND MII_RESET# J23 ENET_RESET_L OUT 32 73


R1860 R1861

1
1
PP3V3_S0_MCP_DAC 25 100K 100K
R1811 +V_RGB_DAC J32 103 mA 206 mA (A01) 5%
1/16W
5%
1/16W
49.9 MF-LF MF-LF
+V_TV_DAC K32 103 mA
1%
NO_TEST=TRUE NC_MCP_RGB_DAC_RSET 402 402

2
1/16W C39 RGB_DAC_RSET
MF-LF
402 TP_MCP_RGB_DAC_VREF B38 RGB_DAC_VREF
2
DDC_CLK0 B31 MCP_DDC_CLK0
DDC_DATA0 A31 MCP_DDC_DATA0

DACS
C RGB_DAC_RED B39 NC_MCP_RGB_RED NO_TEST=TRUE
C
RGB_DAC_GREEN A39 NC_MCP_RGB_GREEN NO_TEST=TRUE

RGB ONLY
71 9 OUT MCP_TV_DAC_RSET E36 TV_DAC_RSET
B40 NC_MCP_RGB_BLUE NO_TEST=TRUE
RGB_DAC_BLUE
OUT MCP_TV_DAC_VREF
71 9 A35 TV_DAC_VREF
RGB_DAC_HSYNC A40 NC_MCP_RGB_HSYNC NO_TEST=TRUE
RGB_DAC_VSYNC A41 NC_MCP_RGB_VSYNC NO_TEST=TRUE
TV / Component
C / Pr TV_DAC_RED A36 CRT_IG_R_C_PR OUT 68 71
20 8 =PP3V3_S5_MCP_GPIO
Y / Y TV_DAC_GREEN B36 CRT_IG_G_Y_Y OUT 68 71
1 26 IN MCP_CLK27M_XTALIN C38 XTALIN_TV
R1820 Comp / Pb TV_DAC_BLUE C36 CRT_IG_B_COMP_PB OUT 68 71
26 OUT MCP_CLK27M_XTALOUT D38 XTALOUT_TV
47K
5% TV_DAC_HSYNC/GPIO_44 D36 CRT_IG_HSYNC OUT 68 71
1/16W TV DAC Disable:
MF-LF TV_DAC_VSYNC/GPIO_45 C37 CRT_IG_VSYNC OUT 68 71
402
2
Okay to float all TV_DAC signals.
BI
LPCPLUS_GPIO E16 GPIO_6/FERR*/IGPU_GPIO_6 IFPA_TXC_P B35 LVDS_IG_A_CLK_P OUT 66 71 Okay to float XTALIN_TV and XTALOUT_TV.
67 IN DP_IG_CA_DET B15 GPIO_7/NFERR*/IGPU_GPIO_7 IFPA_TXC_N C35 LVDS_IG_A_CLK_N OUT 66 71 DDC_CLK0/DDC_DATA0 pull-ups still required.
43 7

IFPA_TXD0_P B32 LVDS_IG_A_DATA_P<0> OUT 7 66 71


Interface Mode 66 OUT LVDS_IG_BKL_PWM G39 LCD_BKL_CTL/GPIO_57
IFPA_TXD0_N A32 LVDS_IG_A_DATA_N<0> OUT 7 66 71
66 OUT LVDS_IG_BKL_ON E37 LCD_BKL_ON/GPIO_59
IFPA_TXD1_P D32 LVDS_IG_A_DATA_P<1> OUT 7 66 71
LVDS_IG_PANEL_PWR

FLAT PANEL
66 F40 LCD_PANEL_PWR/GPIO_58
OUT C32 LVDS_IG_A_DATA_N<1>
MCP Signal TMDS/HDMI DisplayPort IFPA_TXD1_N OUT 7 66 71

IFPA_TXD2_P D33 LVDS_IG_A_DATA_P<2> OUT 7 66 71


=MCP_HDMI_TXC_P/N TMDS_IG_TXC_P/N DP_IG_ML_P/N<3> 67 OUT MCP_HDMI_TXC_P D35 HDMI_TXC_P/ML0_LANE3_P
IFPA_TXD2_N C33 LVDS_IG_A_DATA_N<2> OUT 7 66 71
=MCP_HDMI_TXD_P/N<0> TMDS_IG_TXD_P/N<0> DP_IG_ML_P/N<2> 67 OUT MCP_HDMI_TXC_N E35 HDMI_TXC_N/ML0_LANE3_N
IFPA_TXD3_P B34 LVDS_IG_A_DATA_P<3> OUT 9 71
=MCP_HDMI_TXD_P/N<1> TMDS_IG_TXD_P/N<1> DP_IG_ML_P/N<1>
67 OUT MCP_HDMI_TXD_P<0> G35 HDMI_TXD0_P/ML0_LANE2_P IFPA_TXD3_N C34 LVDS_IG_A_DATA_N<3> OUT 9 71
=MCP_HDMI_TXD_P/N<2> TMDS_IG_TXD_P/N<2> DP_IG_ML_P/N<0>
67 OUT MCP_HDMI_TXD_N<0> F35 HDMI_TXD0_N/ML0_LANE2_N WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases
=MCP_HDMI_DDC_CLK TMDS_IG_DDC_CLK DP_IG_DDC_CLK
67 MCP_HDMI_TXD_P<1> F33 HDMI_TXD1_P/ML0_LANE1_P
B =MCP_HDMI_DDC_DATA
=MCP_HDMI_HPD
TMDS_IG_DDC_DATA
TMDS_IG_HPD
DP_IG_DDC_DATA
DP_IG_HPD
67
OUT
OUT MCP_HDMI_TXD_N<1> G33 HDMI_TXD1_N/ML0_LANE1_N
IFPB_TXC_P
IFPB_TXC_N
L31

K31
LVDS_IG_B_CLK_P
LVDS_IG_B_CLK_N
OUT
OUT
9 71

9 71
B
67 OUT MCP_HDMI_TXD_P<2> J33 HDMI_TXD2_P/ML0_LANE0_P
DP_IG_AUX_CH_P/N TP_DP_IG_AUX_CHP/N DP_IG_AUX_CH_P/N
67 OUT MCP_HDMI_TXD_N<2> H33 HDMI_TXD2_N/ML0_LANE0_N IFPB_TXD4_P J29 LVDS_IG_B_DATA_P<0> OUT 9 71

NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used. IFPB_TXD4_N H29 LVDS_IG_B_DATA_N<0> OUT 9 71

NOTE: 20K pull-down required on DP_HOTPLUG_DET. OUT TP_DP_IG_AUX_CHP D43 DP_AUX_CH0_P IFPB_TXD5_P L29 LVDS_IG_B_DATA_P<1> OUT 9 71

OUT TP_DP_IG_AUX_CHN C43 DP_AUX_CH0_N IFPB_TXD5_N K29 LVDS_IG_B_DATA_N<1> OUT 9 71


NOTE: HDMI port requires level-shifting. IFP interface can
IFPB_TXD6_P L30 LVDS_IG_B_DATA_P<2> OUT 9 71
be used to provide HDMI or dual-channel TMDS without
9 IN DP_HOTPLUG_DET C31 HPLUG_DET2/GPIO_22 IFPB_TXD6_N K30 LVDS_IG_B_DATA_N<2> OUT 9 71
level-shifters.
67 IN MCP_HDMI_HPD F31 HPLUG_DET3 IFPB_TXD7_P N30 LVDS_IG_B_DATA_P<3> OUT 9 71

IFPB_TXD7_N M30 LVDS_IG_B_DATA_N<3> OUT 9 71


25 8 =PP3V3R1V8_S0_MCP_IFP_VDD
190 mA (A01, 1.8V) M27 +VDD_IFPA
M26 +VDD_IFPB DDC_CLK2/GPIO_23 C30 LVDS_IG_DDC_CLK OUT 7 66
25 PP3V3_S0_MCP_VPLL
DDC_DATA2/GPIO_24 B30 LVDS_IG_DDC_DATA BI 7 66
16 mA (A01) 8 mA M28 +V_PLL_IFPAB
8 mA M29 +V_PLL_HDMI
DDC_CLK3 D31 =MCP_HDMI_DDC_CLK OUT 67

25 8 =PP1V05_S0_MCP_HDMI_VDD T25 +VDD_HDMI DDC_DATA3 E31 =MCP_HDMI_DDC_DATA BI 67

95 mA (A01)
71 25 OUT MCP_HDMI_RSET J31 HDMI_RSET IFPAB_RSET E32 MCP_IFPAB_RSET OUT 25 71

71 25 OUT MCP_HDMI_VPROBE J30 HDMI_VPROBE IFPAB_VPROBE G31 MCP_IFPAB_VPROBE OUT 25 71

1
R1850
10K
5%
1/16W

2
MF-LF
402 MCP Ethernet & Graphics
A GPIO 57-59 ( IF LCD PANEL IS USED):
IN MCP79 THESE PINS HAVE UNDOCUMENTED PULL HIGH
SYNC_MASTER=K36B_MLB

NOTICE OF PROPRIETARY PROPERTY


SYNC_DATE=08/17/2008
A
(~10K TO 3.3V). TO ENSURE PINS ARE LOW
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
BY DEFAULT, PULL DOWN(1K OR SRONGER) MUST BE USED PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-8089 02

APPLE INC. SCALE SHT OF


18 109
NONE

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

OMIT
U1400 21 18 8 =PP3V3_S0_MCP_GPIO
MCP79-TOPO-B
BGA
(7 OF 11)

72 19 PCI_REQ0_L T2 PCI_REQ0# PCI_GNT0# R3 TP_PCI_GNT0_L


19 MCP_RS232_SOUT_L R1989 8.2K 1 2
72 19 PCI_REQ1_L V9 PCI_REQ1#/FANRPM2 PCI_GNT1#/FANCTL2 U10 TP_PCI_GNT1_L 5% 1/16W MF-LF 402
19 OUT CRTMUX_SEL_TV_L T3 PCI_REQ2#/GPIO_40/RS232_DSR# PCI_GNT2#/GPIO_41/RS232_DTR# R4 GMUX_JTAG_TMS OUT 9 72 19 PCI_REQ0_L R1990 8.2K 1 2
5% 1/16W MF-LF 402
9 OUT AUD_IPHS_SWITCH_EN U9 PCI_REQ3#/GPIO_38/RS232_CTS# PCI_GNT3#/GPIO_39/RS232_RTS# U11 GMUX_JTAG_TDI OUT 9
72 19 PCI_REQ1_L R1991 8.2K 1 2
19 IN MCP_RS232_SIN_L T4 PCI_REQ4#/GPIO_52/RS232_SIN# PCI_GNT4#/GPIO_53/RS232_SOUT# P3 MCP_RS232_SOUT_L OUT 19 5% 1/16W MF-LF 402

D 72 13 7 BI MCP_DEBUG<0> AC3 PCI_AD0 PCI_CBE0# AA3 TP_PCI_C_BE_L<0>


19 CRTMUX_SEL_TV_L R1992 8.2K 1 2
5% 1/16W MF-LF 402 D
19 MCP_RS232_SIN_L R1994 8.2K 1 2
72 13 7 BI MCP_DEBUG<1> AE10 PCI_AD1 PCI_CBE1# AA6 TP_PCI_C_BE_L<1> 5% 1/16W MF-LF 402

72 13 7 BI MCP_DEBUG<2> AC4 PCI_AD2 PCI_CBE2# AA11 TP_PCI_C_BE_L<2>


72 13 7 BI MCP_DEBUG<3> AE11 PCI_AD3 PCI_CBE3# W10 TP_PCI_C_BE_L<3>
72 13 7 BI MCP_DEBUG<4> AB3 PCI_AD4
72 13 7 BI MCP_DEBUG<5> AC6 PCI_AD5 PCI_DEVSEL# AA9 TP_PCI_DEVSEL_L
72 13 7 BI MCP_DEBUG<6> AB2 PCI_AD6 PCI_FRAME# Y4 TP_PCI_FRAME_L
72 13 7 BI MCP_DEBUG<7> AC7 PCI_AD7 PCI_IRDY# AA10 TP_PCI_IRDY_L
TP_PCI_AD<8> AC8 PCI_AD8 PCI_PAR Y1 TP_PCI_PAR
TP_PCI_AD<9> AA2 PCI_AD9 PCI_PERR#/GPIO_43/RS232_DCD# AB9 TP_PCI_PERR_L
TP_PCI_AD<10> AC9 PCI_AD10 PCI_SERR# AA7 TP_PCI_SERR_L
TP_PCI_AD<11> AC10 PCI_AD11 PCI_STOP# Y2 TP_PCI_STOP_L

PCI
TP_PCI_AD<12> AC11 PCI_AD12
PCI_PME#/GPIO_30 T1 PM_LATRIGGER_L OUT 7 13
TP_PCI_AD<13> AA1 PCI_AD13
Int PU (S5)
TP_PCI_AD<14> AA5 PCI_AD14
TP_PCI_AD<15> Y5 PCI_AD15
TP_PCI_AD<16> W3 PCI_AD16 PCI_RESET0# R10 MEM_VTT_EN_R OUT 26

TP_PCI_AD<17> W6 PCI_AD17 PCI_RESET1# R11 TP_PCI_RESET1_L


TP_PCI_AD<18> W4 PCI_AD18
TP_PCI_AD<19> W7 PCI_AD19
TP_PCI_AD<20> V3 PCI_AD20
PCI_CLK0 R6 TP_PCI_CLK0
TP_PCI_AD<21> W8 PCI_AD21
PCI_CLK1 R7 TP_PCI_CLK1
TP_PCI_AD<22> V2 PCI_AD22
PCI_CLK2 R8 72 PCI_CLK33M_MCP_R
TP_PCI_AD<23> W9 PCI_AD23
TP_PCI_AD<24> U3 PCI_AD24 1
TP_PCI_AD<25> W11 PCI_AD25 R1910
C TP_PCI_AD<26>
TP_PCI_AD<27>
U2

U5
PCI_AD26
PCI_AD27
22
5%
1/16W
MF-LF
C
402
TP_PCI_AD<28> U1 PCI_AD28 2
PLACEMENT_NOTE=Place close to pin R8
TP_PCI_AD<29> U6 PCI_AD29 PCI_CLKIN R9 72 PCI_CLK33M_MCP
TP_PCI_AD<30> T5 PCI_AD30
TP_PCI_AD<31> U7 PCI_AD31

TP_PCI_INTW_L P2 PCI_INTW#
TP_PCI_INTX_L N3 PCI_INTX#
LPC_FRAME# AD4 LPC_FRAME_R_L R1960 22 1 2 LPC_FRAME_L OUT 7 41 43 72
TP_PCI_INTY_L N2 PCI_INTY# 5% 1/16W MF-LF 402
LPC_PWRDWN#/GPIO_54/EXT_NMI# AE12 LPC_PWRDWN_L OUT 7 41 43
TP_PCI_INTZ_L N1 PCI_INTZ#
LPC_RESET0# AE5 LPC_RESET_L OUT 26 72

LPC
TP_PCI_TRDY_L Y3 PCI_TRDY#
LPC_AD0 AD3 LPC_AD_R<0> R1950 0 1 2 LPC_AD<0> BI 7 41 43 72
5% 1/16W MF-LF 402
43 41 7 IN PM_CLKRUN_L AD11 PCI_CLKRUN#/GPIO_42 LPC_AD1 AD2 LPC_AD_R<1> R1951 0 1 2 LPC_AD<1> BI 7 41 43 72
5% 1/16W MF-LF 402
LPC_AD2 AD1 LPC_AD_R<2> R1952 0 1 2 LPC_AD<2> BI 7 41 43 72
5% 1/16W MF-LF 402
35 IN FW_PME_L AE2 LPC_DRQ1#/GPIO_19 Int PU LPC_AD3 AD5 LPC_AD_R<3> R1953 0 1 2 LPC_AD<3> BI 7 41 43 72
5% 1/16W MF-LF 402
TP_LPC_DRQ0_L AE1 LPC_DRQ0# Int PU
43 41 7 BI LPC_SERIRQ AE6 LPC_SERIRQ Int PU LPC_CLK0 AE9 LPC_CLK33M_SMC_R OUT 26 72

1
U24 GND65 GND98 Y26 R1961
10K
U26 GND66 GND99 Y27 5%
1/16W
U39 GND67 GND100 AB18 MF-LF
402
U4 H34 2
GND68 GND101
U8 GND69 GND102 AB20 Strap for Boot ROM Selection (See HDA_SDOUT)
V16 GND70 GND103 AB21

B V17 GND71 GND104 AB23 B


V18 GND72 GND105 AB24

V20 GND73 GND106 AB25

V22 GND74 GND107 AB26

V24 GND75 GND108 AB27

V26 GND76 GND109 AB28


GND

V27 GND77 GND110 AB34

V28 GND78 GND111 AB37

V33 GND79 GND112 AB4

V37 GND80 GND113 AB40


V4 GND81 GND114 AC22

V40 GND82 GND115 AC36

V7 GND83 GND116 AC40

W20 GND84 GND117 AB33

W22 GND85 GND118 AC5

W24 GND86 GND119 AD16

W36 GND87 GND120 AD17

W40 GND88 GND121 AD18

W43 GND89 GND122 AD19

Y16 GND90 GND123 AD20

Y17 GND91 GND124 AD24

Y18 GND92 GND125 AD25

Y19 GND93 GND126 AD26

Y20 GND94 GND127 AD27

Y22 GND95 GND128 AD28


MCP PCI & LPC
A Y24

Y25
GND96
GND97
GND129
GND130
AD33

AD34
SYNC_MASTER=K36B_MLB

NOTICE OF PROPRIETARY PROPERTY


SYNC_DATE=08/17/2008
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-8089 02

APPLE INC. SCALE SHT OF


NONE 19 109

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT
U1400
MCP79-TOPO-B
BGA
(8 OF 11) External A
71 38 OUT SATA_HDD_R2D_C_P AJ7 SATA_A0_TX_P USB0_P C29 USB_EXTA_P BI 39 72

71 38 OUT SATA_HDD_R2D_C_N AJ6 SATA_A0_TX_N USB0_N D29 USB_EXTA_N BI 39 72

AirPort (PCIe Mini-Card)


71 38 IN SATA_HDD_D2R_N AJ5 SATA_A0_RX_N USB1_P C28 USB_MINI_P BI 9 72

71 38 IN SATA_HDD_D2R_P AJ4 SATA_A0_RX_P USB1_N D28 USB_MINI_N BI 9 72

External D
D USB2_P A28 USB_EXTD_P BI 9 72 D
USB2_N B28 USB_EXTD_N BI 9 72

71 38 OUT SATA_ODD_R2D_C_P AJ11 SATA_A1_TX_P Camera


71 38 OUT SATA_ODD_R2D_C_N AJ10 SATA_A1_TX_N USB3_P F29 USB_CAMERA_P BI 66 72

USB3_N G29 USB_CAMERA_N BI 66 72

71 38 IN SATA_ODD_D2R_N AJ9 SATA_A1_RX_N IR


71 38 IN SATA_ODD_D2R_P AK9 SATA_A1_RX_P USB4_P K27 USB_IR_P BI 40 72

USB4_N L27 USB_IR_N BI 40 72

Geyser Trackpad/Keyboard
USB5_P J26 USB_TPAD_P BI 9 72

TP_SATA_C_R2D_CP AK2 SATA_B0_TX_P USB5_N J27 USB_TPAD_N BI 9 72

TP_SATA_C_R2D_CN AJ3 SATA_B0_TX_N Bluetooth


USB6_P F27 USB_BT_P BI 9 72

TP_SATA_C_D2RN AJ2 SATA_B0_RX_N USB6_N G27 USB_BT_N BI 9 72

TP_SATA_C_D2RP AJ1 SATA_B0_RX_P External B

SATA
USB7_P D27 USB_EXTB_P

USB
BI 39 72

USB7_N E27 USB_EXTB_N BI 39 72

ExpressCard
TP_SATA_D_R2D_CP AM4 SATA_B1_TX_P USB8_P K25 USB_EXCARD_P BI 9 72 =PP3V3_S5_MCP_GPIO 8 18

TP_SATA_D_R2D_CN AL3 SATA_B1_TX_N USB8_N L25 USB_EXCARD_N BI 9 72

External C
TP_SATA_D_D2RN AL4 SATA_B1_RX_N USB9_P H25 USB_EXTC_P BI 9 72
1
R2053
1
TP_SATA_D_D2RP AK3 SATA_B1_RX_P USB9_N J25 USB_EXTC_N BI 9 72
R2051 8.2K
8.2K 5%
5% 1/16W
1/16W MF-LF
USB10_P F25 TP_USB_10P MF-LF
2
402
402
G25 TP_USB_10N 2
USB10_N
R2052 1
C TP_SATA_E_R2D_CP
TP_SATA_E_R2D_CN
AN1

AM1
SATA_C0_TX_P
SATA_C0_TX_N USB11_P K23 TP_USB_11P R2050
8.2K
1 8.2K
5%
1/16W
C
USB11_N L23 TP_USB_11N 5% MF-LF
1/16W 402
TP_SATA_E_D2RN AM2 SATA_C0_RX_N MF-LF
2
402
TP_SATA_E_D2RP AM3 SATA_C0_RX_P 2

USB_OC0#/GPIO_25 L21 USB_EXTA_OC_L IN 39

USB_OC1#/GPIO_26 K21 USB_EXTB_OC_L IN 39

USB_OC2#/GPIO_27/MGPIO J21 USB_EXTC_OC_L IN


TP_SATA_F_R2D_CP AP3 SATA_C1_TX_P USB_OC3#/GPIO_28/MGPIO H21 EXCARD_OC_L IN 42

TP_SATA_F_R2D_CN AP2 SATA_C1_TX_N

+V_PLL_USB L28 PP3V3_S0_MCP_PLL_USB 24


TP_SATA_F_D2RN AN3 SATA_C1_RX_N
19 mA (A01)
TP_SATA_F_D2RP AN2 SATA_C1_RX_P
USB_RBIAS_GND A27 72 MCP_USB_RBIAS_GND

R2060 1
TP_MCP_SATALED_L E12 SATA_LED# GND131 AD35 806
1%
GND132 AD37 1/16W
MF-LF
GND133 AD38 402
24 PP1V05_S0_MCP_PLL_SATA AE16 +V_PLL_SATA 2
GND134 AE22
84 mA (A01)
GND135 AE24
8 =PP1V05_S0_MCP_SATA_DVDD0
GND136 AE39
43 mA (A01) AF19 +DVDD0_SATA1
GND137 AE4
AG16 +DVDD0_SATA2
GND138 AD6
AG17 +DVDD0_SATA3
GND139 AF16
AG19 +DVDD0_SATA4
GND140 AF17

GND141 AF18
=PP1V05_S0_MCP_SATA_DVDD1
B 8 AH17

AH19
+DVDD1_SATA1
+DVDD1_SATA2
GND142 AF20 B
GND143 AF22

8 =PP1V05_S0_MCP_SATA_AVDD0 GND144 AF26

127 mA (A01) AJ12 +AVDD0_SATA1 GND145 AF27

AN11 +AVDD0_SATA2 GND146 AF28

AK12 +AVDD0_SATA3 GND147 AF33

AK13 +AVDD0_SATA4 GND148 AF34

AL12 +AVDD0_SATA5 GND149 AF37

AM11 +AVDD0_SATA6 GND150 AF40

AM12 +AVDD0_SATA7 GND151 AG18

AN12 +AVDD0_SATA8 GND152 AG20

AL13 +AVDD0_SATA9 GND153 AG22

GND154 AG26

8 =PP1V05_S0_MCP_SATA_AVDD1 AN14 +AVDD1_SATA1 GND155 AG36

AL14 +AVDD1_SATA2 GND156 AG40

AM13 +AVDD1_SATA3 GND157 AH18

AM14 +AVDD1_SATA4 GND158 AH20

GND159 AH22

71 MCP_SATA_TERMP AE3 SATA_TERMP GND160 AH24

1
R2010
2.49K
1%
1/16W
MF-LF
2
402
MCP SATA & USB
A SYNC_MASTER=K36B_MLB

NOTICE OF PROPRIETARY PROPERTY


SYNC_DATE=08/17/2008
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-8089 02

APPLE INC. SCALE SHT OF


NONE 20 109

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

OMIT
U1400 =PP3V3R1V5_S0_MCP_HDA 8 21 24
MCP79-TOPO-B
BGA 7 mA (A01)
(9 OF 11)

J16 1
+V_DUAL_HDA1 R2160
+V_DUAL_HDA2 K16 8.2K
5%
1/16W

HDA
D 2
MF-LF
402
R2170
22
72 52 IN HDA_SDIN0 G15 HDA_SDATA_IN0 HDA_SDATA_OUT F15 72 21 HDA_SDOUT_R 1 2 HDA_SDOUT OUT 52 72

Int PD 5%
1/16W
MF-LF
BIOS Boot Select
R2171 402
22
TP_MLB_RAM_SIZE J14 HDA_SDATA_IN1_GPIO_2/PS2_KB_CLK HDA_BITCLK E15 72 21 HDA_BIT_CLK_R 1 2 HDA_BIT_CLK OUT 52 72 I/F HDA_SDOUT LPC_FRAME#
Int PD 5%
1/16W
MF-LF
402 R2172 LPC 0 0
22
TP_MLB_RAM_VENDOR J15 HDA_SDATA_IN2_GPIO_3/PS2_KB_DATA HDA_RESET* K15 72 21 HDA_RST_R_L 1 2 HDA_RST_L OUT 52 72
24 21 8 =PP3V3R1V5_S0_MCP_HDA PCI 0 1
Int PD 5%
1/16W
MF-LF
1
R2110 R2173 402 SPI0 1 0
22
49.9 HDA_SYNC L15 72 21 HDA_SYNC_R 1 2 HDA_SYNC OUT 52 72
1%
1/16W 5%
1/16W
SPI1 1 1
MF-LF
402 MF-LF
2 402
SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L
72 MCP_HDA_PULLDN_COMP A15 HDA_PULLDN_COMP HDA_DOCK_EN*_GPIO_4/PS2_MS_CLK K17 MCP_GPIO_4 OUT 21

HDA_DOCK_RST*_GPIO_5/PS2_MS_DATA L17 AUD_I2C_INT_L IN 21 R1961 and R2160 selects SPI0 ROM by


24 PP1V05_S0_MCP_PLL_NV default, LPC+ debug card pulls
37 mA (A01) 20 mA AE18 +V_PLL_NV_H SLP_S3* G17 PM_SLP_S3_L OUT 33 36 41 64 LPC_FRAME# high for SPI1 ROM override.
17 mA AE17 +V_PLL_SP_SPREF SLP_RMGT* J17 PM_SLP_RMGT_L OUT 9
NOTE: MCP79 does not support FWH, only
SLP_S5* H17 PM_SLP_S4_L OUT 41 42 64
LPC ROMs. So Apple designs will
26 22 PP3V3_G3_RTC not use LPC for BootROM override.
43 OUT =SPI_CS1_R_L_USE_MLB L24 GPIO_1/PWRDN_OK/SPI_CS1
THERM_DIODE_P B11 MCP_THMDIODE_P OUT 47
42 41 36 33 IN SMC_ADAPTER_EN L26 GPIO_12_SUS_STAT_ACCLMTR_EXT_TRIG_L NOTE: MCP79 rev A01 does not support
THERM_DIODE_N C11 MCP_THMDIODE_N OUT 47
=PP3V3_S0_MCP 8 22 24 SPI1 option.
1 1
R2120 R2121 TP_SB_A20GATE K13 A20GATE Int PU BOOT_MODE_SAFE
C 49.9K
1%
1/16W
MF-LF
49.9K
1%
1/16W
MF-LF 41
TP_MCP_KBDRSTIN_L
SMC_WAKE_SCI_L
L13

C19
KBRDRSTIN* Int PU
SIO_PME* Int PU (S5)
MCP_VID0/GPIO_13
MCP_VID1/GPIO_14
L20

M20
MCP_VID<0>
MCP_VID<1>
OUT 21 61

21 61
1
R2180
10K BUF_SIO_CLK Frequency
C
IN OUT
402 402 5%
2 2
41 IN SMC_RUNTIME_SCI_L C18 EXT_SMI/GPIO_32* Int PU (S5) MCP_VID2/GPIO_15 M21 MCP_VID<2> OUT 21 61 1/16W
MF-LF Frequency
2
402 HDA_SYNC
SM_INTRUDER_L B20 INTRUDER*
SPKR C13 9 MCP_SPKR
24 MHz 1
BOOT_MODE_USER
TP_MCP_LID_L M25 LID* Int PU (S5) 1
41 PM_BATLOW_L M24 LLB* Int PU (S5) SMB_CLK0 L19 SMBUS_MCP_0_CLK 7 13 44 72
R2181 14.31818 MHz 0
IN OUT
10K
SMB_DATA0 K19 SMBUS_MCP_0_DATA BI 7 13 44 72 5%

MISC
1/16W
69 60 IN PM_DPRSLPVR M22 CPU_DPRSLPVR SMB_CLK1/MSMB_CLK G21 SMBUS_MCP_1_CLK OUT 44 72 MF-LF
402
SMB_DATA1/MSMB_DATA F21 SMBUS_MCP_1_DATA BI 44 72
2

41 IN PM_PWRBTN_L C16 PWRBTN* Int PU (S5) SMB_ALERT*/GPIO_64 M23 AP_PWR_EN OUT 21 31 33 SPI Frequency Select
26 IN PM_SYSRST_DEBOUNCE_L D16 RSTBTN* Int PU
B12 MEM_EVENT_L
Frequency SPI_DO SPI_CLK
FANRPM0/GPIO_60 IN 21 28 29 41
RTC_RST_L C20 RTC_RST*
FANCTL0/GPIO_61 A12 ODD_PWR_EN_L OUT 38
D12 SMC_IG_THROTTLE_L
31 MHz 0 0
FANRPM1/GPIO_63 21 42
41 IN PM_RSMRST_L D20 PWRGD_SB
FANCTL1/GPIO_62 C12 ARB_DETECT 21
26 IN MCP_PS_PWRGD E20 PS_PWRGD 42 MHz 0 1

26 IN MCP_CPU_VLD C17 CPU_VLD CPUVDD_EN D17 MCP_CPUVDD_EN OUT 26 25 MHz 1 0

13 7 6 IN JTAG_MCP_TDI E19 JTAG_TDI Int PU C14 SPI_CS0_R_L


1 MHz 1 1
SPI_CS0/GPIO_10 OUT 43 72
6 OUT JTAG_MCP_TDO F19 JTAG_TDO
SPI_CLK/GPIO_11 D13 SPI_CLK_R OUT 43 72
13 7 6 IN JTAG_MCP_TMS J19 JTAG_TMS Int PU NOTE: Straps not provided on this page.
SPI_DI/GPIO_8 C15 SPI_MISO IN 43
13 7 6 IN JTAG_MCP_TRST_L J18 JTAG_TRST*
SPI_DO/GPIO_9 B14 SPI_MOSI_R OUT 43 72
13 7 6 IN JTAG_MCP_TCK G19 JTAG_TCK

B R21591
10K 26 IN MCP_CLK25M_XTALIN A16 XTALIN SUS_CLK/GPIO_34 B18 PM_CLK32K_SUSCLK_R OUT 26 72
B
5%
1/16W 26 OUT MCP_CLK25M_XTALOUT B16 XTALOUT BUF_SIO_CLK AE7 TP_MCP_BUF_SIO_CLK
MF-LF
402
2
26 IN RTC_CLK32K_XTALIN A19 XTALIN_RTC TEST_MODE_EN K22 MCP_TEST_MODE_EN
26 OUT RTC_CLK32K_XTALOUT B19 XTALOUT_RTC PKG_TEST L22

R21221 R2150 1 1
R2163 1
R2190
100K 10K 10K 1K
5% 5% 5% 1%
1/16W 1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF MF-LF
402 402 402 402
2 2 2 2

=PP3V3_S0_MCP_GPIO 8 18 19

HDA Output Caps 1 1 1 1


For EMI Reduction on HDA interface =PP3V3_S3_FET 8 65
R2143 R2140 R2141 R2142
10K 10K 10K 10K
5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF MF-LF
HDA_SDOUT_R 21 72 402 402 402 402
1 2 2 2 2
HDA_BIT_CLK_R 21 72
R2146
100K AUD_I2C_INT_L 21
5%
HDA_RST_R_L 21 72 1/16W MEM_EVENT_L 21 28 29 41

HDA_SYNC_R 21 72
2
MF-LF
402 SMC_IG_THROTTLE_L 21 42 MCP HDA & MISC
MCP_GPIO_4 21 MCP_VID<0> 21 61

A C2170
10PF
1
C2172
10PF
1 AP_PWR_EN 21 31 33

ARB_DETECT 21
MCP_VID<1>
MCP_VID<2>
21 61

21 61
SYNC_MASTER=K36B_MLB

NOTICE OF PROPRIETARY PROPERTY


SYNC_DATE=08/17/2008
A
5% 5%
50V 50V
CERM 2 CERM 2
402 402 1 1 1 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
R2147 R2155 R2156 R2157 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
100K 22K 22K 22K
5% 5% 5% 5% I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
1
C2171 1
C2173 1/16W 1/16W 1/16W 1/16W
10PF 10PF MF-LF MF-LF MF-LF MF-LF II NOT TO REPRODUCE OR COPY IT
402 402 402 402
5% 5% 2 2 2 2
50V 50V III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
2 CERM 2 CERM
402 402
SIZE DRAWING NUMBER REV.

D 051-8089 02

APPLE INC. SCALE SHT OF


NONE 21 109

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT OMIT
U1400 U1400
MCP79-TOPO-B MCP79-TOPO-B
BGA BGA
(11 OF 11) 61 46 24 8 =PPVCORE_S0_MCP (10 OF 11) =PP1V05_S0_MCP_FSB 8 14 24

AH26 GND161 GND253 AV40 23065 mA (A01, 1.2V) AA25 +VDD_CORE1 +VTT_CPU1 R32 1139 mA 1182 mA (A01)
AH33 GND162 GND254 BA1 16996 mA (A01, 1.0V) AC23 +VDD_CORE2 +VTT_CPU2 AC32

AH34 GND163 GND255 BA4 U25 +VDD_CORE3 +VTT_CPU3 E40

AH37 GND164 GND256 AW31 AH12 +VDD_CORE4 +VTT_CPU4 J36

AH38 GND165 GND257 AY6 AG10 +VDD_CORE5 +VTT_CPU5 N32

AJ39 GND166 GND258 L35 AG5 +VDD_CORE6 +VTT_CPU6 T32

D AJ8 GND167 GND259 BC33 Y21 +VDD_CORE7 +VTT_CPU7 U32 D


AK10 GND168 GND260 BC37 Y23 +VDD_CORE8 +VTT_CPU8 V32

AK33 GND169 GND261 BC41 AA16 +VDD_CORE9 +VTT_CPU9 W32

AK34 GND170 GND262 AY14 AA26 +VDD_CORE10 +VTT_CPU10 P31

AK37 GND171 GND263 BC5 AA27 +VDD_CORE11 +VTT_CPU11 AF32

AK4 GND172 GND264 C2 AA28 +VDD_CORE12 +VTT_CPU12 AE32

AK40 GND173 GND265 D10 AC16 +VDD_CORE13 +VTT_CPU13 AH32

AL36 GND174 GND266 D14 AC17 +VDD_CORE14 +VTT_CPU14 AJ32

AL40 GND175 GND267 D15 AC18 +VDD_CORE15 +VTT_CPU15 AK31

AL5 GND176 GND268 D18 AC19 +VDD_CORE16 +VTT_CPU16 AK32

AM10 GND177 GND269 D19 AC20 +VDD_CORE17 +VTT_CPU17 AD32

AM16 GND178 GND270 D22 AC21 +VDD_CORE18 +VTT_CPU18 AL31

AM18 GND179 GND271 D23 AA17 +VDD_CORE19 +VTT_CPU19 AB32

AM20 GND180 GND272 D26 AC24 +VDD_CORE20 +VTT_CPU20 B41

AM22 GND181 GND273 D30 AC25 +VDD_CORE21 +VTT_CPU21 B42

AM24 GND182 GND274 D37 AC26 +VDD_CORE22 +VTT_CPU22 C40

AM26 GND183 GND275 D6 AC27 +VDD_CORE23 +VTT_CPU23 C41

AM30 GND184 GND276 E13 AC28 +VDD_CORE24 +VTT_CPU24 C42

AM34 GND185 GND277 E17 AD21 +VDD_CORE25 +VTT_CPU25 D39

AM35 GND186 GND278 E21 AD23 +VDD_CORE26 +VTT_CPU26 D40

AM37 GND187 GND279 E25 W27 +VDD_CORE27 +VTT_CPU27 D41

AM38 GND188 GND280 E29 V25 +VDD_CORE28 +VTT_CPU28 E38

POWER
AM5 GND189 GND281 E33 AA18 +VDD_CORE29 +VTT_CPU29 E39

AM6 GND190 GND282 F12 AE19 +VDD_CORE30 +VTT_CPU30 F37

AM7 GND191 GND283 F16 AE21 +VDD_CORE31 +VTT_CPU31 F38

AM9 GND192 GND284 F32 AE23 +VDD_CORE32 +VTT_CPU32 F39

C AP26

AN28
GND193
GND194
GND285
GND286
F8

G10
AE25

AE26
+VDD_CORE33
+VDD_CORE34
+VTT_CPU33
+VTT_CPU34
G36

G37
C
AN30 GND195 GND287 G12 AE27 +VDD_CORE35 +VTT_CPU35 G38

AN39 GND196 GND288 G14 AE28 +VDD_CORE36 +VTT_CPU36 H35

AN4 GND197 GND289 G16 AF10 +VDD_CORE37 +VTT_CPU37 H37

Y7 GND198 GND290 BC12 AF11 +VDD_CORE38 +VTT_CPU38 J34

AP10 GND199 GND291 G22 AA19 +VDD_CORE39 +VTT_CPU39 J35

AU26 GND200 GND292 G24 AF2 +VDD_CORE40 +VTT_CPU40 K33

AP14 GND201 GND293 AW20 AF21 +VDD_CORE41 +VTT_CPU41 K34

AU14 GND202 GND294 G34 AF23 +VDD_CORE42 +VTT_CPU42 K35

AP28 GND203 GND295 G4 AF25 +VDD_CORE43 +VTT_CPU43 L32

AP32 GND204 GND296 G43 AF3 +VDD_CORE44 +VTT_CPU44 L33


GND

AP34 GND205 GND297 G6 AF4 +VDD_CORE45 +VTT_CPU45 L34

AP36 GND206 GND298 G8 AF7 +VDD_CORE46 +VTT_CPU46 M31

AP37 GND207 GND299 H11 AH23 +VDD_CORE47 +VTT_CPU47 M32

AP4 GND208 GND300 H15 AF9 +VDD_CORE48 +VTT_CPU48 M33

AP40 GND209 GND301 AW35 AA20 +VDD_CORE49 +VTT_CPU49 N31

AP7 GND210 GND302 H23 AG11 +VDD_CORE50 +VTT_CPU50 P32

AW23 GND211 GND303 AN8 AG12 +VDD_CORE51 +VTT_CPU51 Y32

AR28 GND212 GND304 G40 AG21 +VDD_CORE52 +VTT_CPU52 AA32

AR32 GND213 GND305 J12 AG23 +VDD_CORE53


AR40 GND214 GND306 J8 AG25 +VDD_CORE54 +VTT_CPUCLK AG32 43 mA
AT10 GND215 GND307 K10 AG3 +VDD_CORE55
AR12 GND216 GND308 K12 AG4 +VDD_CORE56
AT13 GND217 GND309 K18 AA21 +VDD_CORE57
=PP3V3_S0_MCP 8 21 24
AT29 GND218 GND310 K26 AG6 +VDD_CORE58
+3.3V_1 AD10 450 mA (A01)
AT33 GND219 GND311 K37 AG7 +VDD_CORE59
B AT6 GND220 GND312 K4 AG8 +VDD_CORE60
+3.3V_2
+3.3V_3
AE8
AB10
B
AT7 GND221 GND313 K40 AG9 +VDD_CORE61
+3.3V_4 AD9
AT9 GND222 GND314 K8 AH1 +VDD_CORE62
+3.3V_5 Y10
AY21 GND223 GND315 AU1 AH10 +VDD_CORE63
+3.3V_6 AB11
AY22 GND224 GND316 L40 AH11 +VDD_CORE64
+3.3V_7 AA8
L12 GND225 GND317 L43 W26 +VDD_CORE65
+3.3V_8 Y9
AU12 GND226 GND318 L5 AH2 +VDD_CORE66
AU28 GND227 GND319 M10 AA23 +VDD_CORE67
AP33 GND228 GND320 M34 W28 +VDD_CORE68
AU32 GND229 GND321 M35 AH25 +VDD_CORE69 =PP3V3_S5_MCP 8 24

AR30 GND230 GND322 M37 AH21 +VDD_CORE70 +3.3V_DUAL1 G18 16 mA 266 mA (A01)
AU36 GND231 GND323 Y28 AH3 +VDD_CORE71 +3.3V_DUAL2 H19

AU38 GND232 GND324 Y33 AH4 +VDD_CORE72 +3.3V_DUAL3 J20

AU4 GND233 GND325 Y34 AH5 +VDD_CORE73 +3.3V_DUAL4 K20

G28 GND234 GND326 Y35 AH6 +VDD_CORE74


F20 GND235 GND327 Y37 AH7 +VDD_CORE75 +3.3V_DUAL_USB1 G26 250 mA
AV28 GND236 GND328 Y38 AH9 +VDD_CORE76 +3.3V_DUAL_USB2 H27

AV32 GND237 GND329 AB17 AA24 +VDD_CORE77 +3.3V_DUAL_USB3 J28

AV36 GND238 GND330 AB16 W21 +VDD_CORE78 +3.3V_DUAL_USB4 K28


AV4 GND239 GND331 AN26 W23 +VDD_CORE79
AV7 GND240 GND332 AD7 W25 +VDD_CORE80
AW11 GND241 GND333 M11 AF12 +VDD_CORE81
=PP1V05_S5_MCP_VDD_AUXC 8 24
G20 GND242 GND334 AA4
+VDD_AUXC1 T21 105 mA (A01)
AR43 GND243 GND335 AB19 PP3V3_G3_RTC
AW43 GND244 GND336 AY13
26 21

10 uA (G3)
+VDD_AUXC2 U21 MCP Power & Ground
A20 +VBAT +VDD_AUXC3 V21

A AY10

AV12
GND245
GND246
GND337
GND338
P11

Y6
80 uA (S0) SYNC_MASTER=K36B_MLB

NOTICE OF PROPRIETARY PROPERTY


SYNC_DATE=08/17/2008
A
AY30 GND247 GND339 T11

AY33 GND248 GND340 V11 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AY34 GND249 GND341 Y11 AGREES TO THE FOLLOWING
AY37 GND250 GND342 AH16 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
AY38 GND251 GND343 T22 II NOT TO REPRODUCE OR COPY IT
AY41 GND252 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-8089 02

APPLE INC. SCALE SHT OF


22 109
NONE

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

C C

B B

MCP79 A01 Silicon Support


A SYNC_MASTER=K36B_MLB

NOTICE OF PROPRIETARY PROPERTY


SYNC_DATE=08/17/2008
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-8089 02

APPLE INC. SCALE SHT OF


NONE 24 109

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MCP Core Power NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF)
Apple: 4x 4.7uF 0402, 4x 1uF 0402, 6x 0.1uF 0402 (23.4 uF)
61 46 22 8 =PPVCORE_S0_MCP
23065 mA (A01, 1.2V)
16996 mA (A01, 1.0V)
1 1 1 1 1 1 1 1 1 1 1 1 1 1
C2500 C2501 C2502 C2503 C2504 C2505 C2506 C2507 C2508 C2509 C2510 C2511 C2512 C2513
(No IG vs. EG data) 4.7UF 4.7UF 4.7UF 4.7UF 1UF 1UF 1UF 1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 10% 10% 10% 10% 20% 20% 20% 20% 20% 20%
4V 4V 4V 4V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V
X5R 2 X5R 2 X5R 2 X5R 2 2 X5R 2 X5R 2 X5R 2 X5R 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402-1 402-1 402-1 402-1 402 402 402 402 402 402

D MCP PCIE (DVDD) Power MCP SATA (DVDD) Power


L2570 NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF) D
30-OHM-5A Apple: 5x 2.2uF 0402 (11 uF)
8 =PP1V05_S0_MCP_PEX_DVDD 8 =PP1V05_S0_MCP_SATA_DVDD 8 =PP1V05_S0_MCP_AVDD_UF PP1V05_S0_MCP_PEX_AVDD 7 8
1 2
MIN_LINE_WIDTH=0.4 MM
57 mA (A01) 43 mA (A01) 333 mA (A01) MIN_NECK_WIDTH=0.2 MM 206 mA (A01)
VOLTAGE=1.05V
0603

1 1 1 1 1 1 1 1 1 1 1 1
C2515 C2516 C2517 C2518 C2519 C2520 C2521 C2570 C2571 C2572 C2573 C2574
4.7UF 1UF 1UF 0.1uF 0.1uF 4.7UF 0.1uF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 10% 10% 20% 20% 20% 20% 20% 20% 20% 20% 20%
4V 10V 10V 10V 10V 4V 10V 6.3V 6.3V 6.3V 6.3V 6.3V
X5R 2 2 X5R 2 X5R 2 CERM 2 CERM X5R 2 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402-1 402-1 402 402 402 402 402-LF 402-LF 402-LF 402-LF 402-LF

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)


MCP 1.05V AUX Power MCP 1.05V RMGT Power
L2575 Apple: 2x 2.2uF 0402 (4.4 uF)
=PP1V05_S5_MCP_VDD_AUXC =PP1V05_ENET_MCP_RMGT 30-OHM-5A PP1V05_S0_MCP_SATA_AVDD
22 8 18 8 7 8
1 2
MIN_LINE_WIDTH=0.4 MM
105 mA (A01) 131 mA (A01) MIN_NECK_WIDTH=0.2 MM 127 mA (A01)
VOLTAGE=1.05V
0603

1 1 1 1 1 1
C2525 C2526 C2528 C2529 C2575 C2576
0.1uF 0.1uF 4.7uF 0.1uF 2.2UF 2.2UF
20% 20% 20% 20% 20% 20%
10V 10V 4V 10V 6.3V 6.3V
2 CERM 2 CERM X5R 2 2 CERM 2 CERM 2 CERM
402 402 402 402 402-LF 402-LF

MCP FSB (VTT) Power NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)
L2580
Apple: 7x 2.2uF 0402 (15.4 uF) 30-OHM-1.7A
22 14 8 =PP1V05_S0_MCP_FSB 8 =PP1V05_S0_MCP_PLL_UF PP1V05_S0_MCP_PLL_FSB 14
MIN_LINE_WIDTH=0.4 MM
1 2
1182 mA (A01) 562 mA (A01) MIN_NECK_WIDTH=0.2 MM 270 mA (A01)
VOLTAGE=1.05V
0402

C 1
C2530
2.2UF
1
C2531
2.2UF
1
C2532
2.2UF
1
C2533
2.2UF
1
C2534
2.2UF
1
C2535
2.2UF
1
C2536
2.2UF
C2580
4.7UF
1 1
C2581
0.1UF
C
20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 4V 10V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM X5R 2 2 CERM
402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402 402

MCP Memory Power


L2582
=PP1V8R1V5_S0_MCP_MEM 30-OHM-1.7A PP1V05_S0_MCP_PLL_PEX
16 8 17
1 2
MIN_LINE_WIDTH=0.4 MM
4771 MA (A01, DDR2) MIN_NECK_WIDTH=0.2 MM 84 mA (A01)
VOLTAGE=1.05V
0402

1 1 1 1 1 1 1 1 1 1 1 1
C2540 C2541 C2542 C2543 C2544 C2545 C2546 C2547 C2548 C2549 C2582 C2583
4.7UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 4.7UF 0.1UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
4V 10V 10V 10V 10V 10V 10V 10V 10V 10V 4V 10V
X5R 2 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM X5R 2 2 CERM
402 402 402 402 402 402 402 402 402 402 402 402

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)


MCP 3.3V Power NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF) L2584
L2555 Apple: 1x 2.2uF 0402 (2.2 uF) 30-OHM-1.7A PP1V05_S0_MCP_PLL_SATA
Apple: 4x 2.2uF 0402 (8.8 uF) 30-OHM-1.7A 20
22 21 8 =PP3V3_S0_MCP 8 =PP3V3_S0_MCP_PLL_UF PP3V3_S0_MCP_PLL_USB 20
1 2
MIN_LINE_WIDTH=0.4 MM
1 2
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM 84 mA (A01)
450 mA (A01) 19 mA (A01) MIN_NECK_WIDTH=0.2 MM 19 mA (A01) 0402
VOLTAGE=1.05V
VOLTAGE=3.3V
0402
1 1
C2584 C2585
1
C2550 1
C2551 1
C2552 1
C2553 1