FIELD EFFECT TRANSISTORS

Field-effect transistors

1. General overview
2. Types of field-effect transistors
3. Uses
1. General overview

• Field-effect transistors (FETs) follow an other principle than bipolar

junction transistors
• They rely on an electric field to control the shape and hence the
conductivity of a „channel“ in a semiconductor material
• FETs controlled by voltage (BJTs controlled by current)
1. General overview

• The concept of the field effect transistor predates the bipolar junction
transistor (BJT)
• Was not physically implemented until after BJTs, due to limitations of
semiconductor materials and relative ease of manufacturing BJTs
compared to FETs at that time.
1. General overview

• Basic principle of FETs

control terminal
control
voltage

of charge carriers for charge

current channel carriers

• The terminals of a FET refer to their function: Gate (G), Source (S), Drain (D)
1. General overview

• FETs are voltage-controlled by the voltage between gate and source

terminal
• Voltage effects the electric field of the transistor which enlarges or
diminishes the channel
 Effects the current stream through the FET
2. Types of field-effect transistors

Junction Field-Effect Transistors

JFETs
• Simplest type of FET
• Long channel semiconductor
• Either p- or n-doped ( p-type, n-type)
• A contact at each end  source and drain terminals
• Gate terminal surrounds the channel and is doped opposite to the
doping of the channel
2. Types of field-effect transistors

Junction Field-Effect Transistors

JFETs
• N-channel types and P-channel types
2. Types of field-effect transistors

Metal-Oxide-Semiconductor FETs
MOS-FETs
• Most common field-effect transistor
• traditional metal–oxide–semiconductor (MOS) structure is
obtained by depositing a layer of silicon dioxide and a layer of
metal on top of a semiconductor die. As the silicon dioxide is a
dielectric material its structure is equivalent to a planar capacitor,
with one of the electrodes replaced by a semiconductor
(substrate)
2. Types of field-effect transistors

Metal-Oxide-Semiconductor FETs
MOS-FETs
• Metal electrode is used as the gate, the other forms the so called
body/bulk/substrate terminal of a MOS-FET
• Opposite doted semiconductors placed within the substrate form the drain and
source terminals
• Modulating the MOS-Capacitance forms a channel between source and drain
terminals
• This controls the current flow through the MOS-FET
2. Types of field-effect transistors

Metal-Oxide-Semiconductor FETs
MOS-FETs
2. Types of field-effect transistors

Metal-Oxide-Semiconductor FETs
MOS-FETs

N-Channel

P-Channel

enhancement- depletion-
mode mode
3. Uses
• As well as BJTs, FETs can be used as switching and/or amplifying elements
• JFETs are also often used as variable, controlable resistors
• FETs, especially JFETs consumpt almost no current  high input impedance
• Makes JFETs very suitable for pre-amplifiers
• FETs behave like electron tubes from the old days
• Integrated circuits (CMOS, other modern elements) use MOS-FETs as the
switching element
• Power-MOS-FETs are used in HiFi power amplifiers and produce a sound
comparable to tube amplifiers
• Many, many more uses…
The Junction Field Effect Transistor
• The Junction Field Effect Transistor (JUGFET or JFET) has no PN-
junctions but instead has a narrow piece of high resistivity
semiconductor material forming a “Channel” of either N-type or P-
type silicon for the majority carriers to flow through with two ohmic
electrical connections at either end commonly called the Drain and
the Source respectively.
• There are two basic configurations of junction field effect transistor,
the N-channel JFET and the P-channel JFET. The N-channel JFET’s
channel is doped with donor impurities meaning that the flow of
current through the channel is negative (hence the term N-channel)
in the form of electrons.
• Likewise, the P-channel JFET’s channel is doped with acceptor impurities meaning
that the flow of current through the channel is positive (hence the term P-
channel) in the form of holes.
• N-channel JFET’s have a greater channel conductivity (lower resistance) than
their equivalent P-channel types, since electrons have a higher mobility through a
conductor compared to holes.
• This makes the N-channel JFET’s a more efficient conductor compared to their P-
channel counterparts.
• The semiconductor “channel” of the Junction Field Effect Transistor is a
resistive path through which a voltage VDS causes a current ID to flow and
as such the junction field effect transistor can conduct current equally well
in either direction. As the channel is resistive in nature, a voltage gradient
is thus formed down the length of the channel with this voltage becoming
less positive as we go from the Drain terminal to the Source terminal.
• The result is that the PN-junction therefore has a high reverse bias at the
Drain terminal and a lower reverse bias at the Source terminal. This bias
causes a “depletion layer” to be formed within the channel and whose
width increases with the bias.
• The magnitude of the current flowing through the channel between the
Drain and the Source terminals is controlled by a voltage applied to the
Gate terminal, which is a reverse-biased. In an N-channel JFET this Gate
voltage is negative while for a P-channel JFET the Gate voltage is positive.
The main difference between the JFET and a BJT device is that when the
JFET junction is reverse-biased the Gate current is practically zero, whereas
the Base current of the BJT is always some value greater than zero.
Biasing of an N-channel JFET
• The cross sectional diagram above shows an N-type semiconductor channel with
a P-type region called the Gate diffused into the N-type channel forming a
reverse biased PN-junction and it is this junction which forms the depletion
region around the Gate area when no external voltages are applied. JFETs are
therefore known as depletion mode devices.
• This depletion region produces a potential gradient which is of varying thickness
around the PN-junction and restrict the current flow through the channel by
reducing its effective width and thus increasing the overall resistance of the
channel itself.
• Then we can see that the most-depleted portion of the depletion region is in
between the Gate and the Drain, while the least-depleted area is between the
Gate and the Source. Then the JFET’s channel conducts with zero bias voltage
applied (ie, the depletion region has near zero width).
• With no external Gate voltage ( VG = 0 ), and a small voltage ( VDS ) applied
between the Drain and the Source, maximum saturation current ( IDSS ) will flow
through the channel from the Drain to the Source restricted only by the small
depletion region around the junctions.
• If a small negative voltage ( -VGS ) is now applied to the Gate the size
of the depletion region begins to increase reducing the overall
effective area of the channel and thus reducing the current flowing
through it, a sort of “squeezing” effect takes place. So by applying a
reverse bias voltage increases the width of the depletion region
which in turn reduces the conduction of the channel.
• Since the PN-junction is reverse biased, little current will flow into the
gate connection. As the Gate voltage ( -VGS ) is made more negative,
the width of the channel decreases until no more current flows
between the Drain and the Source and the FET is said to be “pinched-
off” (similar to the cut-off region for a BJT). The voltage at which the
channel closes is called the “pinch-off voltage”, ( VP ).
JFET Channel Pinched-off

In this pinch-off region the Gate voltage, VGS controls the channel current and VDS has little or no effect.
• The result is that the FET acts more like a voltage controlled resistor
which has zero resistance when VGS = 0 and maximum “ON”
resistance ( RDS ) when the Gate voltage is very negative. Under
normal operating conditions, the JFET gate is always negatively
biased relative to the source.
• It is essential that the Gate voltage is never positive since if it is all the
channel current will flow to the Gate and not to the Source, the result
is damage to the JFET. Then to close the channel:
• No Gate voltage ( VGS ) and VDS is increased from zero.
• No VDS and Gate control is decreased negatively from zero.
• VDS and VGS varying.
• The P-channel Junction Field Effect Transistor operates the same as
the N-channel above, with the following exceptions: 1). Channel
current is positive due to holes, 2). The polarity of the biasing voltage
needs to be reversed.
Output characteristic V-I curves of a typical
junction FET.
• The voltage VGS applied to the Gate controls the current flowing between the Drain and the Source terminals.
VGS refers to the voltage applied between the Gate and the Source while VDS refers to the voltage applied
between the Drain and the Source.
• Because a Junction Field Effect Transistor is a voltage controlled device, “NO current flows into the gate!”
then the Source current ( IS ) flowing out of the device equals the Drain current flowing into it and therefore
( ID = IS ).
• The characteristics curves example shown above, shows the four different regions of operation for a JFET and
these are given as:
• • Ohmic Region – When VGS = 0 the depletion layer of the channel is very small and the JFET acts like a
voltage controlled resistor.
• • Cut-off Region – This is also known as the pinch-off region were the Gate voltage, VGS is sufficient to cause
the JFET to act as an open circuit as the channel resistance is at maximum.
• • Saturation or Active Region – The JFET becomes a good conductor and is controlled by the Gate-Source
voltage, ( VGS ) while the Drain-Source voltage, ( VDS ) has little or no effect.
• • Breakdown Region – The voltage between the Drain and the Source, ( VDS ) is high enough to causes the
JFET’s resistive channel to break down and pass uncontrolled maximum current.
• The characteristics curves for a P-channel junction field effect transistor are the same as those above, except
that the Drain current ID decreases with an increasing positive Gate-Source voltage, VGS.
• The Drain current is zero when VGS = VP. For normal operation, VGS is biased to be somewhere between VP and
0. Then we can calculate the Drain current, ID for any given bias point in the saturation or active region as
follows:
Drain current in the active region.

Note that the value of the Drain current will be between zero (pinch-off) and IDSS
(maximum current). By knowing the Drain current ID and the Drain-Source voltage
VDS the resistance of the channel ( ID ) is given
Common Source (CS) Configuration

In the Common Source configuration (similar to common

emitter), the input is applied to the Gate and its output is
taken from the Drain as shown. This is the most common
mode of operation of the FET due to its high input impedance
and good voltage amplification and as such Common Source
amplifiers are widely used.
The common source mode of FET connection is generally used
audio frequency amplifiers and in high input impedance pre-
amps and stages. Being an amplifying circuit, the output signal
is 180o “out-of-phase” with the input.
Common Gate (CG) Configuration
In the Common Gate configuration (similar to common
base), the input is applied to the Source and its output is
taken from the Drain with the Gate connected directly to
ground (0v) as shown. The high input impedance feature
of the previous connection is lost in this configuration as
the common gate has a low input impedance, but a high
output impedance.
This type of FET configuration can be used in high
frequency circuits or in impedance matching circuits were
a low input impedance needs to be matched to a high
output impedance. The output is “in-phase” with the
input.
Common Drain (CD) Configuration
In the Common Drain configuration (similar to
common collector), the input is applied to the Gate
and its output is taken from the Source. The
common drain or “source follower” configuration
has a high input impedance and a low output
impedance and near-unity voltage gain so is
therefore used in buffer amplifiers. The voltage
gain of the source follower configuration is less
than unity, and the output signal is “in-phase”, 0o
with the input signal.
This type of configuration is referred to as
“Common Drain” because there is no signal
available at the drain connection, the voltage
present, +VDD just provides a bias. The output is in-
phase with the input.
Drain Characteristic With Shorted-Gate.
• The circuit diagram for determining the drain characteristic with shorted-gate for an N-channel JFET
is given in figure. and the drain characteristic with shorted-gate is shown in another figure.
• Initially when drain-source voltage Vns is zero, there is no attracting potential at the drain, so no
current flows inspite of the fact that the channel is fully open. This gives drain current Ip = 0. For
small applied voltage Vna, the N-type bar acts as a simple semiconductor resistor, and the drain
current increases linearly with_the increase in Vds, upto the knee point. This region, (to the left of
the knee point) of the curve is called the channel ohmic region, because in this region the FET
behaves like an ordinary resistor.
• With the increase in drain current ID, the ohmic voltage drop between the source and channel
region reverse-biases the gate junction. The reverse-biasing of the gate junction is not uniform
throughout., The reverse bias is more at the drain end than that at the source end of the channel, so
with the increase in Vds, the conducting portion of the channel begins to constrict more at the drain
end. Eventually a voltage Vds is reached at which the channel is pinched off. The drain current ID no
longer increases with the increase in Vds. It approaches a constant saturation value. The value of
voltage VDS at which the channel is pinched off (i.e. all the free charges from the channel get
removed), is called the pinch-off voltage Vp. The pinch-off voltage Vp, not too sharply defined on the
curve, where the drain current ID begins to level off and attains a constant value. From point A (knee
point) to the point B (pinch-off point) the drain current ID increases with the increase In voltage Vds
following a reverse square law. The region of the characteristic in which drain current ID remains
fairly constant is called the pinch-off region. It is also sometimes called the saturation region or
amplifier region. In this region the JFET operates as a constant current device sincedrain current (or
output current) remains almost constant. It is the normal operating region of the JFET when used as
an amplifier. The drain current in the pinch-off region with VGS = 0 is referred to the drain-source
saturation current, Idss).
• It is to be noted that in the pinch-off (or saturation) region the channel resistance
increases in proportion to increase in VDS and so keeps the drain current almost
constant and the reverse bias required by the gate-channel junction is supplied
entirely by the voltage drop across the channel resistance due to flow of IDsg and
not by the external bias because VGS = 0
• Drain current in the pinch-of region is given by Shockley’s equation
• where ID is the drain current at a given gate-source voltage VGS, IDSS is the drain-
current with gate shorted to source and VGS (0FF) is the gate-source cut-off voltage.
• If drain-source voltage, Vds is continuously increased, a stage comes when the
gate-channel junction breaksdown. At this point current increases very rapidly.
and the JFET may be destroyed. This happens because the charge carriers making
up the saturation current at the gate channel junction accelerate to a high
velocity and produce an avalanche effect.
Drain Characteristics With External Bias
• The circuit diagram for determining the drain characteristics with different values
of external bias is shown in figure. and a family of drain characteristics for different
values of gate-source voltage VGS is given in figure.
• It is observed that as the negative gate bias voltage is increased
• (1) The maximum saturation drain current becomes smaller because the conducting
channel now becomes narrower.
• (2) Pinch-off voltage is reached at a lower value of drain current ID than when VGS =
0. When an external bias of, say – 1 V is applied between the gate and the source,
the gate-channel junctions are reverse-biased even when drain current, ID is zero.
Hence the depletion regions are already penetrating the channel to a certain extent
when drain-| source voltage, VDS is zero. Due to this reason, a smaller voltage drop
along the channel (i.e. smaller than that for VGS = 0) will increase the depletion
regions to the point where 1 they pinch-off the current. Consequently, the pinch-
off voltage VP is reached at a lower 1 drain current, ID when VGS = 0.
• (3) The ohmic region portion decreases.
• (4) Value of drain-source voltage VDS for the avalanche breakdown of the gate
junction is reduced.
• Value of drain-source voltage, VDS for breakdown with the increase in
negative bias voltage is reduced simply due to the fact that gate-
source voltage, VGS keeps adding to the I reverse bias at the junction
produced by current flow. Thus the maximum value of VDS, that can
be applied to a FET is the lowest voltage which causes avalanche
breakdown.
Transfer Characteristic of JFET
• The transfer characteristic for a JFET can be determined experimentally, keeping
drain-source voltage, VDS constant and determining drain current, ID for various
values of gate-source voltage, VGS. The circuit diagram is shown in fig.
• The curve is plotted between gate-source voltage, VGS and drain current, ID, as
illustrated in fig.
• It is similar to the trans conductance characteristic of a vacuum tube or a
transistor. It is observed that
• (i) Drain current decreases with the increase in negative gate-source bias
• (ii) Drain current, ID = IDSS when VGS = 0
• (iii) Drain current, ID = 0 when VGS = VD.
• The transfer characteristic can also be derived from the drain characteristic by
noting values of drain current, IDcorresponding to various values of gate-source
voltage, VGS for a constant drain-source voltage and plotting them.
• It may be noted that a P-channel JFET operates in the same way and have the
similar characteristics as an N-channel JFET except that channel carriers are holes
instead of electrons and the polarities of VGS and VDS are reversed.
Metal–oxide–semiconductor field-effect
transistor (MOSFET)
• The metal–oxide–semiconductor field-effect transistor (MOSFET, MOS-FET,
or MOS FET) is a type of transistor used for amplifying or switching
electronic signals.
• Although the MOSFET is a four-terminal device with source (S), gate (G),
drain (D), and body (B) terminals.
• The body (or substrate) of the MOSFET is often connected to the source
terminal, making it a three-terminal device like other field-effect
transistors. Because these two terminals are normally connected to each
other (short-circuited) internally, only three terminals appear in electrical
diagrams.
• The MOSFET is by far the most common transistor in both digital and
analog circuits, though the bipolar junction transistor was at one time
much more common.
• In enhancement mode MOSFETs, a voltage drop across the oxide induces a
conducting channel between the source and drain contacts via the field
effect.
• The term "enhancement mode" refers to the increase of conductivity with
increase in oxide field that adds carriers to the channel, also referred to as
the inversion layer.
• The channel can contain electrons (called an nMOSFET or nMOS), or holes
(called a pMOSFET or pMOS), opposite in type to the substrate, so nMOS is
made with a p-type substrate, and pMOS with an n-type substrate.
• In the less common depletion mode MOSFET, detailed later on, the
channel consists of carriers in a surface impurity layer of opposite type to
the substrate, and conductivity is decreased by application of a field that
depletes carriers from this surface layer.
Threshold voltage
• The threshold voltage, commonly abbreviated as Vth or VGS (th), of a field-effect
transistor (FET) is the minimum gate-to-source voltage differential that is needed
to create a conducting path between the source and drain terminals.
• At gate-to-source voltages above the threshold voltage (VGS > Vth) but still
below saturation (less than "fully on", (VGS − Vth) > VDS), the transistor is in its
'linear region', also known as ohmic mode, where it behaves like a voltage-
controlled variable resistor.
• When referring to a junction field-effect transistor (JFET), the threshold voltage is
often called "pinch-off voltage" instead. This is somewhat confusing since "pinch
off" applied to insulated-gate field-effect transistor (IGFET) refers to the channel
pinching that leads to current saturation behaviour under high source–drain bias,
even though the current is never off. Unlike "pinch off", the term "threshold
voltage" is unambiguous and refers to the same concept in any field-effect
transistor.
Channel length modulation
• One of several short-channel effects in MOSFET scaling, channel length
modulation (CLM) is a shortening of the length of the inverted channel region
with increase in drain bias for large drain biases.
• The result of CLM is an increase in current with drain bias and a reduction of
output resistance. Channel length modulation occurs in all field effect transistors,
not just MOSFETs.
• To understand the effect, first the notion of pinch-off of the channel is
introduced. The channel is formed by attraction of carriers to the gate, and the
current drawn through the channel is nearly a constant independent of drain
voltage in saturation mode.
• However, near the drain, the gate and drain jointly determine the electric field
pattern. Instead of flowing in a channel, beyond the pinch-off point the carriers
flow in a subsurface pattern made possible because the drain and the gate both
control the current.
• In the figure at the right, the channel is indicated by a dashed line and becomes
weaker as the drain is approached, leaving a gap of uninverted silicon between
the end of the formed inversion layer and the drain (the pinch-off region).
Channel length modulation
• Explanation for channel length modulation
 Pinched point moves to source terminal with the
voltage vDS increased.
 Effective channel length reduced
 Channel resistance decreased
 Drain current increases with the voltage vDS
increased.
• Current drain is modified by the channel
length modulation
W
iD  1
2 k n ' （ v GS  Vt )（
2
1＋  v DS )
L
Channel length modulation

The MOSFET parameter VA depends on the process technology and, for a

given process, is proportional to the channel length L.
Channel length modulation
• MOS transistors don’t behave an ideal current
source due to channel length modulation.
• The output resistance is finite.
1
 iD  1 V
ro      A
 v
 DS  ID ID
v GS  const .

• The output resistance is inversely proportional to

the drain current.
• As the drain voltage increases, its control over the current extends further
toward the source, so the uninverted region expands toward the source,
shortening the length of the channel region, the effect called channel-
length modulation.
• Because resistance is proportional to length, shortening the channel
decreases its resistance, causing an increase in current with increase in
drain bias for a MOSFET operating in saturation.
• The effect is more pronounced the shorter the source-to-drain separation,
the deeper the drain junction, and the thicker the oxide insulator.
• In the weak inversion region, the influence of the drain analogous to
channel-length modulation leads to poorer device turn off behavior known
as drain-induced barrier lowering, a drain induced lowering of threshold
voltage.
• In bipolar devices a similar increase in current is seen with increased
collector voltage due to base-narrowing, known as the Early effect.
• The similarity in effect upon the current has led to use of the term "Early
effect" for MOSFETs as well, as an alternative name for "channel-length
modulation".
Large-signal equivalent circuit model

Large-signal equivalent circuit model of the n-channel

MOSFET in saturation, incorporating the output resistance
ro. The output resistance models the linear dependence of iD
on vDS
Characteristics of p channel device

(a) Circuit symbol for the p-channel enhancement-type MOSFET.

(b) Modified symbol with an arrowhead on the source lead.
(c) Simplified circuit symbol for the case where the source is connected to the
body.
Characteristics of p channel device

The MOSFET with voltages applied and the directions of

current flow indicated.
The relative levels of the terminal voltages of the
enhancement-type PMOS transistor for operation in the triode
region and in the saturation region.
Characteristics of p channel device

Large-signal equivalent circuit model of the p-channel

MOSFET in saturation, incorporating the output resistance
ro. The output resistance models the linear dependence of iD
on vDS
The conceptual circuit
 Conceptual circuit utilized to study
the operation of the MOSFET as a
small-signal amplifier.
 Small signal condition
v gs  2(VGS  V t )
The small-signal models

Without the channel-length With the channel-length

modulation effect modulation the effect by
iD W
including an output resistance
gm   kn ' V OV
 v GS L  v DS VA
v GS  V GS ro  
 iD ID
—transconductance
iD  I D
The small-signal models

The T model of the MOSFET An alternative representation

augmented with the drain-to- of the T model
source resistance ro
Modeling the body effect

Small-signal equivalent-circuit model of a MOSFET in

which the source is not connected to the body.
Basic structure of the circuit

Basic structure of the circuit

used to realize single-stage
discrete-circuit MOS
amplifier configurations.
The common-source amplifier

The simplest common-source

amplifier biased with constant-
current source.
CC1 And CC2 are coupling
capacitors.
CS is the bypass capacitor.
Equivalent circuit of the CS amplifier
Equivalent circuit of the CS amplifier

Small-signal analysis performed directly on the amplifier circuit

with the MOSFET model implicitly utilized.
Characteristics of CS amplifier
• Input resistance Rin  RG
• Voltage gain Av   g m (ro // RD // RL )
• Overall voltage gain Gv  
RG
g m ( RD // RL // ro )
RG  Rsig
• Output resistance
Rout  ro // RD
The CS amplifier with a source resistance
 Small-signal equivalent circuit with ro neglected
Voltage gain
g m ( R D // R L )
Av  
1  g m RS
Overall voltage gain
RG g m ( RD // RL )
Gv  
RG  Rsig 1  g m RS

 RS takes the effect of

negative feedback
 Gain is reduction by
(1+gmRS)
The Common-Gate amplifier

Biasing with constant

current source I
Input signal vsig is
applied to the source
Output is taken at the
drain
Gate is signal grounded
CC1 and CC2 are coupling
capacitors
The CG amplifier

A small-signal equivalent
circuit
T model is used in
preference to the π
model
Ro is neglecting
The CG amplifier fed with a current-signal input
• Voltage gain
Av  g m ( R D // R L )
• Overall voltage gain
g m ( RD // RL )
Gv 
1  g m Rsig
The common-drain or source-follower amplifier

Biasing with current source

Input signal is applied to gate, output signal is taken at the source
The CD or source-follower amplifier

 Small-signal equivalent-
circuit model
 T model makes analysis
simpler
 Drain is signal grounded
Overall voltage gain
RG ro // RL
Gv  1
RG  Rsig r // R  1
o L
gm
Circuit for determining the output resistance
Shichman–Hodges model
• In textbooks, channel length modulation in active mode usually is
described using the Shichman–Hodges model, accurate only for old
technology:
• where ID = drain current, K'n = technology parameter sometimes
called the transconductance coefficient, W ,L = MOSFET width and
length,
• VGS = gate-to-source voltage, Vth =threshold voltage, VDS = drain-to-source
voltage,
• VDS,sat = VGS - Vth, and λ = channel-length modulation parameter.\
• In the classic Shichman–Hodges model, Vth is a device constant, which
reflects the reality of transistors with long channels.
D-MOSFET & E-MOSFET
Depletion Mode MOSFET
• The depletion mode MOSFET shown as a N channel device (P channel
is also available) in Fig is more usually made as a discrete component,
i.e. a single transistor rather than IC form.
• In this device a thin layer of N type silicon is deposited just below the
gate−insulating layer, and forms a conducting channel between
source and drain.
• Therefore when the gate source voltage VGS is zero, current (in the
form of free electrons) can flow between source and drain.
• Note that the gate is totally insulated from the channel by the layer
of silicon dioxide.
• Now that a conducting channel is present the gate does not need to
cover the full width between source and drain.
• Because the gate is totally insulated from the rest of the transistor
this device, like other IGFETs, has a very high input resistance.
Operation of a Depletion Mode MOSFET
In the N channel device, shown in
Fig. 5.2 the gate is made negative
with respect to the source, which
has the effect of creating a
depletion area, free from charge
carriers, beneath the gate. This
restricts the depth of the
conducting channel, so increasing
channel resistance and reducing
current flow through the device.
• Depletion mode MOSFETS are also available in which the gate
extends the full width of the channel (from source to drain). In this
case it is also possible to operate the transistor in enhancement
mode.
• This is done by making the gate positive instead of negative. The
positive voltage on the gate attracts more free electrons into the
conducing channel, while at the same time repelling holes down into
the P type substrate.
• The more positive the gate potential, the deeper, and lower
resistance is the channel. Increasing positive bias therefore increases
current flow.
• This useful depletion/enhancement version has the disadvantage that,
as the gate area is increased, the gate capacitance is also larger than
true depletion types. This can present difficulties at higher
frequencies.
Circuit Symbols for Depletion Mode MOSFETs
Construction of a N Channel Enhancement
Mode MOSFET
The basic construction of a MOSFET is shown in
Fig. A body or substrate of P type silicon is used,
then two heavily doped N type regions are
diffused into the upper surface, to form a pair of
closely spaced strips.

A very thin (about 10−4 mm) layer of silicon

dioxide is then evaporated onto the top surface
forming an insulating layer. Parts of this layer are
then etched away above the N type regions using
a photographic mask to leave these regions
uncovered. On top of the insulating layer,
between the two N type regions, a layer of
aluminium is deposited. This acts as the GATE
electrode. Metal contacts are also deposited on
the N type regions, which act as the SOURCE and
DRAIN connectors
Enhancement Mode Operation.
The gate has a voltage applied to it that makes it
positive with respect to the source. This causes
holes in the P type layer close to the silicon
dioxide layer beneath the gate to be repelled
down into the P type substrate, and at the same
time this positive potential on the gate attracts
free electrons from the surrounding substrate
material..

These free electrons form a thin layer of charge carriers beneath the gate electrode (they can't reach the gate because
of the insulating silicon dioxide layer) bridging the gap between the heavily doped source and drain areas. This layer is
sometimes called an "inversion layer" because applying the gate voltage has caused the P type material immediately
under the gate to firstly become "intrinsic" (with hardly any charge carriers) and then an N type layer within the P type
substrate
• Any further increase in the gate voltage attracts more charge carriers into the
inversion layer, so reducing its resistance, and increasing current flow between
source and drain. Reducing the gate source voltage reduces current flow. When
the power is switched off, the area beneath the gate reverts to P type once more.

• As well as the type described above, devices having N type substrates and P type
(inversion layer) channels are also available. Operation is identical, but of course
the polarity of the gate voltage is reversed.

• This method of operation is called "ENHANCEMENT MODE" as the application of

gate source voltage makes a conducting channel "grow", therefore it enhances
the channel. Other devices are available in which the application of a bias voltage
reduces or "depletes" the conducting channel.
Circuit Symbols for Enhancement Mode
MOSFETs
 Current Equations for MOSFETs in Saturation
For PMOS devices
  p Cox 
Vsg  VTP 2
W
ID  
L  2 

k p ' Vsg  VTP   K p ' Vsg  VTP 

W 2 2
ID 
L ID
gm 
ID Vsg
gm 
ID  k p ' Vsg  VTP 
W
Vsg
2

 2 k p ' Vsg  VTP  

W
k p ' Vsg  VTP 
W
ID 
L L

W V  VTP  
ID
2
sg
k p ' ID W
kp'
L L
 For NMOS devices
W   n Cox 
Vgs  VTN  ID  k n ' Vgs  VTN   K n ' Vgs  VTN 
2 W
ID   2 2

L 2  L

ID
gm 
Vsg
W
2 k n ' ID
L
 Parameters
Parameter description value
W Gate width of either NMOS or PMOS
L Gate Length for either NMOS or PMOS
Lambda (l) Design parameter for scalable rules .35 microns
PMOS or NMOS minimum sized device Smallest possible PMOS or NMOS device W = 3l = 10.5m m
L = 2l = .75m m
Cox Gate capacitance per unit area ~2.5 fF/um2
Parameters specific to PMOS devices
p Effective mobility of holes
k’=p Cox)/2 -------
VTP PMOS Threshold Voltage
Cjsw Source/drain Side wall capacitance (F/m)
Cj Source/drain bottom plate capacitance Units
(F/m2)
Cjswg Source/drain Side wall capacitance on drain
side Units (F/m)
Cgdo Drain overlap capacitance (F/m)
Parameters specific to NMOS devices
n Effective mobility of electrons 446.9 cm2/V-sec
k’=n Cox)/2 -------
VTN NMOS Threshold Voltage
Cjsw Source/drain Side wall capacitance: (F/m)
Cj Source/drain bottom plate capacitance Units
(F/m2)
Cjswg Source/drain Side wall capacitance on drain
side: Units (F/m)
Cgdo Drain overlap capacitance (F/m)
FINFET
INTRODUCTION TO FINFET
• The term “FINFET” describes a non-planar, double
gate transistor built on an SOI substrate, based on the
single gate transistor design.
• The important characteristics of FINFET is that the
conducting channel is wrapped by a thin Si “fin”,
which forms the body of the device.
• The thickness of the fin determines the effective
channel length of the device.
HISTORY OF FINFET
• FINFET is a transistor design first developed by
Chenming Hu and his colleagues at the University of
California at Berkeley, which tries to overcome the
worst types of SCE(Short Channel Effect).
• Originally, FINFET was developed for use on Silicon-
On-Insulator(SOI).
• SOI FINFET with thick oxide on top of fin are called
“Double-Gate” and those with thin oxide on top as
well as on sides are called “Triple-Gate” FINFETs
REASON FOR EVOLUTION OF
FINFET
• For the double gate SOI MOSFETs, the gates control
the energy barrier b/w source and drain effectively.
• Therefore, the Short Channel Effect(SCE) can be
suppressed without increasing the channel impurity
concentration.
GENERAL LAYOUT & MODE OF OPERATION
• The basic electrical layout and mode of operation of a FINFET does
not differ from a traditional FET.
• There is one source and one drain contact as well as a gate to control
the current flow.
• In contrast to planar MOSFET, the channel b/w source and drain is
build as 3D bar on top of the Si substrate and are called fin.
CONTINUED………

The gate electrode is then wrapped around the channel, so

that there can be formed several gate electrodes on each side
which leads to the reduction in the leakage currents and an
enhanced drive current.
“FINS”
• The fin is used to form the raised channel.
• As the channel is very thin the gate has a great control over carriers
within it, but, when the device is switched on, the shape limits the
current through it to a low level.
• The thickness of the fin (measured in the direction from source to
drain) determines the effective length of the device.
FABRICATION OF FINFET
• The heart of the FINFET is a thin Si fin, which serves as
a body of the MOSFET.
• A heavily doped poly Si film wraps around the fin and
makes the electrical contact to the vertical faces of
the fin.
• A gap is etched through the poly Si film to separate
the source and drain.
The various steps in the fabrication of FINFETs are
discussed as follows.
CHEMICAL VAPOUR DEPOSITION(CVD)
• SiN and SiO layers are deposited on Si film to make a hard mask or a
cover layer.
• The cover layer will protect the Si fin throughout the fabrication
process.
• Then, a layer of SiO2 is developed by the process of dry etching.
• The layer of SiO2 is used to relieve the stress.
ELECTRON BEAM LITHOGRAPHY
• The fine Si fin is patterned by EB Lithography with 100keV
acceleration energy.
• The resist pattern is slightly ashed at 5W and 30 sec to reduce the Si
fin width.
• Then using top SiO layer as a hard etching mask, the SiO layer is
etched.
• By this process, the silicon fin is patterned.
NEXT PROCESSES
• A thin layer of sacrificial layer of SiO2 is grown.
• Then, the sacrificial oxide is stripped completely to remove etch
damage.
• While the cover layer protects the Si fin, the amorphous Si is
completely removed from the side of the Si fin.
• The amorphous Si is in contact with the Si fin at its side surfaces
becomes the impurity diffusion source that forms the transistor
source and drain.
OXIDATION
• The gate oxidation should thin the Si fin width slightly.
• By oxidizing the Si surface, gate oxide as thin as 2.5nm is grown.
• Because the area of Si fin inside the surface is too small, we use
dummy wafers to measure the oxide thickness.
• Hence the gate oxide is grown.
FORMATION OF POLY-Si GATE
• The boron doped Si is deposited at 475`C as the gate material.
• Because the source and drain extension is already formed and
covered by thick SiO layer, no high temperature steps are required
after the gate deposition.
• The total parasitic resistance due to probing is about 3000.
HOW TO REDUCE COMPLEXITY OF
FABRICATION???
• Due to the complexity of fabrication process, the FINFET design was proposed
to have a delta structure, so that after the reduction of vertical feature height,
the gate channel-Gate stacked structure is realized by a Quasi-Planar
technology.
EVALUATION OF FINFET

• Current performance is poor.

• Conducted only in high voltages

REASON FOR POOR PERFORMANCE:
• Large bits and holes in the Si fin and the source drain areas.

• In fabrication, photo resist alone is not a sufficient task.

PARASITIC CAPACITANCE
• It is also known as stray capacitance.
• In electrical circuits, Parasitic capacitance is an unavoidable and
usually wanted capacitance that exists b/w parts of an electronic
component or circuit simply because of their proximity (relationship)
to each other.
• Circuit elements such as inductors, diodes and transistors have
internal capacitance and derivate from the circuit elements.
HOW TO AVOID PARASITIC CAPACITANCE
• Additional process steps are required to induce impurities
(appropriate type) below the fin to provide a Punch-Through
Stop(PTS), ensuring there is no direct current path b/w gate and
source and are electrically controlled by gate input.
SHORT CHANNEL EFFECT
• It is an effect whereby a MOSFET in which the channel length is the
same order of magnitude as the depletion layer widths of source &
drain junctions, behaves differently from the other MOSFETs.
• As the channel length ‘l’ is reduced to increase both the operation
speed and the number of components per chip, the so called SCE
occurs.
ATTRIBUTES OF THE SHORT CHANNEL EFFECT
1. Limitation imposed on the electron drift characteristics in the
channel.

2. Modification of threshold voltage (Short Channel Effect(SCE))

Effective channel width
(W)=(Tfin+(2*Hfin))

Effective channel length

(Leff)=(Lgate+(2*Lext))
ADVANTAGES OF FINFET
• Higher technological maturity than planar DG.

• Suppressed Short Channel Effect(SCE)

• Better in driving current

• More compact

• Low cost
DISADVANTAGES OF FINFET
• Reduced mobility for electrons

• Higher source and drain resistances

• Poor reliability
Dual-gate MOSFET
• The dual-gate MOSFET has a tetrode configuration, where both gates control the
current in the device.
• It is commonly used for small-signal devices in radio frequency applications
where biasing the drain-side gate at constant potential reduces the gain loss
caused by Miller effect, replacing two separate transistors in cascode
configuration.
• Other common uses in RF circuits include gain control and mixing (frequency
conversion). The "tetrode" description, though accurate, does not replicate the
vacuum-tube tetrode. Vacuum-tube tetrodes, using a screen grid, exhibit much
lower grid-plate capacitance and much higher output impedance and voltage
gains than triode vacuum tubes.
• These improvements are commonly an order of magnitude (10 times) or
considerably more. Tetrode transistors (whether bipolar junction or field-effect)
do not exhibit improvements of such a great degree.