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5> OCTOBER 1974

[31 E. J. Boleky, ‘%ubnanosecond switching delays using CMOS/ Kapazitat auf Source und Drain im Ersatzschaltbild eines
SOS silicon-gate technology,” in 1971 Int. Solid-State Cir- MOS-Transistors,” Siemenx Forxchungs- und Ent wicldwrgs-
cuit Conj., Dig. Tech. Papers, p. 225, berichte 1, no. 3$ pp. X4-286, 1972.
[41 E. J. Boleliy and J. E. Meyer, “High-performance low-power [121 J. R. Burns, “Switching response of complementary+sym-
CMOS memories using silicon-on-sapphire technology,” metry MOS transistors logic circuits,” RCA Rev., vol. 25,
IEEE J. Solid-State Circuits (Special Issue on Micropower pp. 627481, 1964.
Electronics), vol. SC-7, pp. 135-145, Apr. 1972. [131 R. w. Ahrons and P. D. Gardner, ‘[Introduction of tech-
[5’1 R. W. Bower, H. G. Dill, K. G. Aubuchon, and S. A. Thomp- nology and performance in complementary symmetry cir-
son, ‘[MOS field effect transistors by gate masked ion im- cuits,” IEEE J. Solid-State Circuits (Special Issue on Tech-
plantation,” IEEE !t’’rams. Electron Devices, vol. ED-15, pp. nology jor Integrated-Circuit Design), vol. SC-5, pp. 24–29,
757-761, Oct. 1968. Feb. 1970.
[61 J. Tihanyi, “Complementary ESFI MOS devices with gate [141 F. F. Fang and H. Rupprecht, “High performance MOS in-
self adjustment by ion implantation,” in Proc. 5,th Iwt. Conj. tegrated circuits using ion implantation technique,” pre-
Microelectronics in Munich, Nov. 27–29, 1972. Munchen- sented at the 1973 ESSDERC, Munich, Germany,
Wien, Germany: R. Oldenbourg Verlag, pp. 437447.
[71 E. J. Boleky, “The performance of complementary MOS
transistors on insulating substrates,” RCA Rev., vol. 80, pp.
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[81 K. Goser, ‘[Channel formation in an insulated gate field
effect transistor ( IGFET) and its emrivalent circuit .“ Sienzen.s Michael Pomper, for a photograph and biography, please see p.
Forschungs- und Entwiclclungsbekhte, no. 1, pp.’ 3-9, 1971. 238 of this issue.
[91 A. E. Ruehli and P, A. Brennan, “Accurate metallization
capacitances for integrated circuits and packages,” IEEE J.
Solid-State Circwits (Corresp.), vol. SC-8, pp. 289-290, Aug.
[101 SINAP (Siemens Netzwerk Analyse Programm Paket),
Siemens AG, Munich, Germany. Jeno Tlhanyi, for a photograph and biogra~hy, please see p.
[111 K, Goser and K. Steinhubl, ‘[Aufteilung der Gate-Kanal- 238 of this issue.

Design of Ion-Implanted MOSFET’S with
Very Small Physical Dimensions

Absfracf—This paper considers the design, fabrication, and LIST OF SYMBOLS
characterization of very small MOSI?ET switching devices suitable
for digital integrated circuits using dimensions of the order of 1 p. a Inverse semilogarithmic slope of sub-
Scaling relationships are presented which show how a conventional threshold characteristic.
MOSFET can be reduced in size. An improved small device struc- D Width of idealized step function pro-
ture is presented that uses ion implantation to provide shallow fde for chaDnel implant.
source and drain regions and a nonuniform substrate doping pro-
AW, Work function difference between gate
file. One-dimensional models are used to predict the substrate
doping profile and the corresponding threshold voltage versus and substrate.
source voltage characteristic. A two-dimensional current transport Dielectric constants for silicon and
model is used to predict the relative degree of short-channel effects silicon dioxide.
for different device parameter combinations. Polysilicon-gate Drain current.
MOSFET’S with channel lengths as short as 0.5 ~ were fabricated,
Boltzmann’s constant.
and the device characteristics measured and compared with pre-
dicted values. The performance improvement expected from using Unitless scaling constant.
these very small devices in highly miniaturized integrated circuits MOSFET channel length.
is projected. Effective surface mobility.
Intrinsic carrier concentration.
Substrate acceptor concentration.
Band bending in silicon at the onset of
Manuscript received May 20, 1974; revised July 3, 1974.
The aubhors are with the IBM T. J. Watson Research Center, strong inversion for zero substrate
Yorktown Heights, N.Y. 10598. voltage.

concise manner the general design trends to be followed centration of doping atoms allows the substrate doping in dccreming the size and increasing the performance of profile in the channel region under the gate to be in. Next. the channel length) of an FET formance. First. gate insulator thickn. :N+ ~N+o ___. the fabrication process These changes become significant when the depletion for an improved scaled-down device structure using ion regions surrounding the source and drain extend over a implantation is described. switching device which can be fabricated with a thicker tion lithographic techniques requires the development of gate insulator if desired. which offers some advantages with respect to thresh- properly designed conventional-size MOSFET shows that old control. this channel INTRODUCTION implant reduces the sensitivity of the threshold voltage to changes in the source-to-substrate (“backdate”) bias. For switching applications. which has well-controlled thresh- new device designs.Wd Source and drain depletion layer Conventional commercially available device structure.DENN. ) along with the horizontal mensional simulation.. to-substrate capacitances). proach is then presented. compared . interelectrode capacitances (e. Experimental verification of the scaling ap- leads to undesirable changes in the device characteristics. and which has significantly reduced can be optimized for very small dimensions. Finally. ion implantation allows the formation of very new techniques. electron beam pattern writing has been shallow source and drain regions which are more favor- widely used for experimental device fabrication [1] – [4] able with respect to short-channel effects.g. gate and substrate volt- ages. Built-in junction potential. _- Vd. of these features in an all-implanted design gives a Full realization of the benefits of these new high-resolu. 5P =. and a gate threshold voltage at which the device turns on.”b Source voltage relative to substrate. L’l - source. v.. Effective oxide charge. (b) V. A major consideration of this paper is to show how DEVICE SCALING the use of ion implantation leads to an improved design for very small scaled-down MOSFET’S. and structures which old characteristics. junction depth. Fig. GATE ~ tox=loooh GATE &*200A (1 Charge on the electron.intendedfor zero substrate centration [7]. from integrated circuits that use these very small FET’s. EW HIGH resolution lithographic techniques for This reduced “substrate sensitivity” can then be traded forming semiconductor integrated circuit patterns N off for a thicker gate insulator of 350-A thickness which offer a decrease in linewidth of five to ten times over the optical contact masking approach which is com- tends to be easier to fabricate reproducibly and reliably. Q. Design considerations for this large portion of the region in the silicon substrate under all-implanted structure are based on two analytical tools: the gate electrode.-. the ability The principles of device scaling [7]. Using the two-di- ess. VaubDrain. NA=5 x 10’5/cm3 N~=25x10’6/cm a a Vd. and char. v.___. while also proportionately decreasing the Yarious parameters is shown. drain-to-gate or drain- what is substrate in this This paper concerns the design. The predicted results from both analyses are down the vertical dimensions (e. Fig. which two-dimensional current-transport model that predicts is aggravated by high drain voltages. fabrication. etc. lIOSFET switching devices. : ION-IMPLANTED MOSFET’S 257 *.g... Of the Second. -OILhp ‘+ /l ‘+ t ox Gate oxide thickness. 1. w MOSFET channel width.e. detailed attention is applied voltages and increasing the substrate doping con. case? acterization of very small MOSFET switching devices This paper begins by describing the scaling principles suitable for digital integrated circuits using dimensions which are applied to a conventional MOSFET to obtain of the order of 1 p. the most a simple one-dimensional model that predicts the sub- undesirable “short-channel” effect is a reduction in the strate sensitivity for long channel-length devices. monly used in the semiconductor industry today. Gate threshold voltage. givcll to all alternate design. The combination ing [6] have also exhibited high-resolution capability. It has been shown the device turn-on characteristics as a function of chan- that these short-channel effects can be avoided by scaling nel length... 1 compares a state-of- creased in a controlled manner. (a) w.. the paper concludes with a discus- a 200-A gate insulator is required if the channel length sion of the performance improvements to be expected is to be reduced to 1 ~. . [8].vith experimental data. taining an acceptable sheet resistance. Then. the sensitivity of the design to dimensions. a very small device structure capable of improved per- to-drain spacing (i. 1. /L\ --0 T Absolute temperature. [8] show in a of ion implantation to accurately introduce a low con. Illustration of device scaling principles with K = 5..4m et al. Applying this scaling approach to a bins. widths. Drain voltage relative to source. relatively lightly doped starting substrate. (a) v. When combined with a the-art n-channel lllOSFET [9] with a scaled-down . technologies. while main- while X-ray lithography [5] and optical projection print. (b) Scaled-down device structure. It is known that reducing the source.

iL OF SOLIC)-STATE CIRCUITS.258 IEEE JOURFJ.. ). while the changes in are shown in Fig. the fixed substrate bias supply normally used strate sensitivity..J. Na’ = ~Na)._ d P. – ~7t – K — vd/~ ) (Vet/K) = Id/K (3) tration will modify the surface potential and significantly lower the threshold voltage. the design pa. w. ancl approximately cancels out *. since the clevice current is reduced reduction in channel length to 1 p. (1) Thus..g.’) = V. factor of K.. which opposite to that of the substrate or aluminum gates on confirms the scaling predictions./K)./K. Furthermore. Other scaling rela- that the clcvicc will function properly in a circuit with tionships for power density... delay time. e.. + [~~. First. on circuit performance... From (3).. Thus.. ~ 9. where the primed parameters clude electric field patterns and current clensity.. t.. V~S’ = Vd. ~. Third.’ = {[2cs. tOx/K. In Fig.e. (–)( w/K L/ii — V.. the channel current per unit of channel width IV The scaling relationships were developed by observing is unchanged by scaling..V. and doping. normalized to W/L = 1. ) = (~. junction depth. etc. ~.’ = (2kT/q) h] (.e. This All of the equations that clescribe the MOSFET clevice restriction arises primarily from the penetration of the characteristics may be scaled as demonstrated above.. voltage. neglecting (i. agnin using the same scaling factor locity effects will be similar in both devices....’ 1 (a) is reasonably typical of commercially a~ailable de. V.. two sets of experimental devices o were fabricated with gate insulators + (AJVf + ~. A substrate doping of 5 X 10’5 increased eloping since ~0’ @ *./K)]’”} In order to verify the scaling relationships. are given reducecl voltage levels. 1 (a). OCTOBER 1974 clevice clesignecl following the device scaling principles to p-type substrates) the work function difference A~Vf is be described later.. The measured drain voltage In (2) the reduction in Tt is primarily due to the de.’ + tant criterion in digital switching circuits employing V.ox’ = &’K. of opposite sign.) /K.g. electrons per unit gate area) arc reducecl in proportion to the device climensions due to moving at the same velocity. all linear clirnensions are reduced by a unitless scaling It is possible to generalize the scaling approach to in- faCtOr K. by K... In most quite similar when plotted with voltage and current scales cases of interest (i. K = 5). two o~er the full range of variation of the source voltage.e. assuming no change in mobility. 5 p. For a maxi- of approximately 12-15 V this pene.. 2. is the band bencling in the silicon (i. the substrate doping concen- changed due to scaling and. Thus. 1 (b’) was microscopic cliff erences due to the fixed crystal lattice obtained using K = 5 which corresponds to the desired dimensions. as well as the horizontal di- coordinates.. the volt- any corresponding point is un?hanged because V/c = ages applied to the device are reduced by the same factor V’/x’. For depletion region surrounding the clrain into the area example.e. e. rameters limit the channel length L to about.’/n.(V~’ + V.. This is consistent with the same that the depletion layer widths in the scaled-down device sheet density of carriers (i. + V. the exact . can be re- For the clevice illustrated in Fig. any saturation ve- tration is increased. The clesign shown in Fig./Ic.’ = (tO=/KCOf) { –Q. The tin-o sets of characteristics are the voltage and doping terms tend to cancel out. with n-channel devices can be adjusted so that (~. the mobility is reduced slightly clue to increased three variables: dimension.. the MOSFET current equation [9] given by normally mum controlled ch-ain voltage by the gate electrode. extent in the new device. (~) of 1000 ancl 200 A (i. thethreshold voltage increases by more than a factor of the potential drop across the source or drain junctions.-. The threshold voltage at turn-on [9] is also decreased complementing the higher density of immobile charge in clirect pro~ortion to the reduced device voltages so clue to the heavier doped substrate. due to the shallower cliffusions.. This reduction electric field distribution is maintained in the scaled- il~cludes vertical dimensions such as gate insulator thick- clown device except for a change in scale for the spatial ness. However. CIUCeC{ by K. creased insulator thickness. It uses a 1OOO-A gate insulator thickness with a bias. impurity scattering in the heavier doped substrate.. is seen to be reduced by a. the device is scaled by a transformation in Actually. for any given set In order to clesigl~ a new device suitable for smaller of applied voltages.JK)l/CIKN. In the vicinity of the clrain. It would appear that the *’ terms appearing in (1) substrate doping ancl substrate bias chosen to give a and (2) prevent exact scaling since they rcxnain approxi- gate threshold voltage I:r of approximately 2 V relative mately constant.. the clensity of mobile carriers per unit volume will bc higher in the space-charge region around the drain. values of L.~K~a(+s’ + Vs-s.e. by scaling clown the ap- source followers because the design becomes difficult if plied substrate bias more than the other applied voltages. etc. }”2 m w. cm-3 is low enough to give an acceptable value of sub.. tial) at the onset of strong inversion for zero substrate niques. the reducecl potentials ancl the increased doping. The larger structure shown in Fig. hence. the surface poten- vices fahricatecl by using conventional diffusion tech. The substrate sensitivity is an impor.. actually increasing slightly due to the to the source potential. tOx/K. the carrier velocity at any point is also un- (e. For ex- the carriers will move away from the surface to a lesser ample. The refer to the new scaled-down device. characteristics of these devices. or across the depletion region under the gate. polysilicon gates of doping type of the smaller clevice reduced by a factor of five. Second. the electric field strength at mensions of channel length and width. This is shown by the threshold in Table I ancl will be discussed in a subsequent section voltage equation for the scaled-down device.

increase in the effective surface mobility shows an approximate reduction of ten pcrccnt in mobility [ 12] and thereby invalidate the current scaling rclation- for dcviccs with the heavier doped substrate. one must accept the.65V 5 Q 0 5 10 15 20 DRAINVOLTAGE[V] (a) 0. 1.5 .5 VSu~=-7V most logic circuit design purposes.0 tox =10001! When proj ccted to intcrccpt the gate voltage axis this =5V ‘ds linear relationship defines a threshold voltage useful for 2.DENNARD et at. but this lT70uld cause with larger width and Icngth dimensions on the same chip <% significant. =0. Experimental turn-on characteristics for conventional and scaled-down devices shown in Fig.5 is in the subthrcshold pr weak inversion region of the turn-on characteristic. 2. a. In order to design devices for operation at threshold voltage also scales correctly by a factor of room temperature and above.. drain voltage is large enough to cause pinchoff and the 3. is exponentially 1. 1. fact five is verified in Fig. ~~ versus ~T. 3.8 1.2 3 .5. The lJaramctcr ~ is important to dynamic memory circuits because it determines the gate voltage excursion rcq~lired match on the current scale is thought to be fortuitous to go froln tile low Current “off” state to the high current since there is some experimental uncertainty in the magni.. ‘(on” state ( 11].6 a ()dccadc = d log. scaling relationships to ~ one could reduce the operating istics (see Appendix). and (b) scaled-down structures shown in Fig. T’ = ~/K).2 1. [10]. volts flv. += sO. For the cases Shon-nj the istic is of particular concern to Ininiaturc dynamic menl- .3 GATE VOLTAGE[v] 0. In an attempt to also extend the linear tude of the channel length used to normalize the character.. which is the same as for the original larger clcvice. : ION-IMPbiNTED MOSFET’S 259 1..65V fid 2.o Onc area in which the dcvicc characteristics fail to scale [#A] ’’2. 3.5~ GATEVOLTAGE [V] 20 tox=100ox 10- L *w=5p v~ub=-?v 0. L1orc accurate data from dcviccs temperature in (4) (i. 1 normalized to W/L = 1.e.’ ( how 4 .. 0 IF + ~ o 0 I 2 3 4 DRAIN VOLTAGE[v] (b) Fig.0 dependent on V.’ GATE VOLTAGE[V] Fig.5 charact cristics exhibit the expected linear relationship. 3. 1 nor- malized to W/L = 1. [11] which for the scaled-down device is given by 0. That the shi~) of (3). turn-on characteristics for the original This nonscaling property of the subthreshold character- and the scaled-down devices. which SIIOJVS tllc cxpcrirncntal that the subthreshold behavior does not scale’ as desired. with an inverse scmilogarithrnic slopc. B@ow threshold. 1#.Expcrimentzd drain voltage characteristics for (a) con- ventional.

when it is not too light).1( . and the gate regions threshold voltage as will be shown later. high dose low implanted n+ regions of depth comparable to the (4 x 10’5 atoms/cm’) As” implantation through the implanted p-type surface layer. low energy how? the depletion’ layer will extend deeper into the lighter (40 keV). . In’ contrast. and due to the natural self- alignment afforded by the ion implantation process which (b) reduces the overlap of the polysilicon gate over the . 4 (a).e.P channel length shown in Fig. With this improvement in substrate the implanted regions. and (b) corresponding ion-implanted device structure. The depletion regions under the source and drain extend much further into the lighter doped substrate. The device capacitances are reduced with the ion-im- how. OCTOBER 1974 260 under the gate electrode at the edges of the source and t~* drain are then inhibited by the heavier doped surface layer. cm (i. .y~~=-lv threshold voltage increase. -. 1 .-.. .. The ion-implanted device uses an ing with high quality master masks for process develop- initial substrate doping that is lower by about a factor ment.. punchthrough at high drain voltages. 4 (b). . the . and be- when the device is turned on with the source grounded. FABRICATION OF ION-IMPLANTED MOS~ET’s ory circuits which require low source-to-drain leakage currents.5x lo15cnl-3 -. . and the additional exposed “bulk” implanted into the wafers. it was more convenient to use contact mask- shown in Fig. and an implanted boron surface layer having a for the gate pattern which uses lines as small as 1. . Figs. 4(b). . the shal- lower junctions give a more favorable electric field pat- \ I tern which avoids these effects when the substrate doping 1 V. . of Fig. . .7 x 101’ atoms/cmz) B“ ions were doped substrate. With deeper junctions these depletion regions (a) would tend to merge in the lighter doped material which would cause a loss of threshold control or. 4(a). gate capacitance. source and drain gives reduced regions. The method of fabrication for the thick face layer are chosen so that this heavier doped region oxide isolation between adj scent FET’s is not described will be completely within the surface depletion layer as it is not essential to the work presented here. for the case of a turned-off device. .5 to 10 p. sensitivity the gate insulator thickness can be increased After the channel implantation.. 7. in the extreme. The thicker but gate insulator the performance also ) p-Si 7. deep were formed by a high energy (100 keV). raising the boron doping near charge will be reasonably small and will cause only a the silicon surface. The depletion regions same 350-A oxide layer. . . the corresponding improved design Though the eventual aim is to use electron-beam pattern utilizing the capability afforded by ion implantation is exposure. compared to 3 V for the sc-sled-down device ture. “. IEEE JOURNAL OF SOLID-STATE CIRCUITS. delineated.= -Iv concentration is properly chosen (i.e. .. ing dry thermal growth of the gate oxide. benefit To compensate in this respect is offset by the decreased for the thicker gate oxide and the expected gate field. a 3500-A thick poly - to as much ‘as 350A and still maintain a reasonable gate silicon layer was deposited. The fabrication process for the ion-implanted MOS- FET’s used in this study will now be described.5 x 1015cm-’).5 p con’eentration somewhat greater than the concentration which are reduced in the subsequent processing.. . . Detailed cross sections for (a) scaled-down device struc. n“ source and drain regions 2000-A Another aspect of the design philosophy is to use shal. when the source is biased above ground potential. . 4. cause several suitable techniques are available. The used throughout the unimplanted structure of Fig. . devices with channel lengths ranging from 0.. a design objective was set at 4 V for the ion-implanted for maximum design drain in Fig. Fig. . about The concentration and the depth of the implanted sur. i cannot see it in the figure? planted structure due to the increased depletion layer width separating the source and drain from the substrate [cf. For this purpose high resolution is required only of four. roughly pictured in Fig. 4(a). starting substrate resistivity was 2 CI. Next. During this step. The scaling considerations just presented lead to the n-channel MOSFET’s on a test chip which contains device structure with a l-. however. . 4(b). However. 4(a) and 4(b) ]. A four- ION-IMPLANTED DEVICE DESIGN mask process was used to fabricate polysilicon-gate.. doped n’. . All implantations were performed modest increase in the gate-to-source voltage required to after gate oxide growth in order to restrict diffusion of turn on the device. Follow- Thus. low dose (6.

the boron is redistributed as shown by the heavier plant. For p. ‘The step profile ap- implantation damage without greatly spreading out the proximates the final predicted profile rather well and implanted doses. The program assumes that boron atoms ions underneath the edges of the gates. the old voltage has been developed from piecewise solutions contact holes to the n+ and polysilicon regions were de. The dashed line.. 6. After metaliza.. 5.. which is more than adequate to anneal out the as shown by the solid line in Fig.. sensitivity characteristics for the nonimplanted device with a 200-A gate insulator and a constant background ONE-DIMENSIONAL (LONG CHANNEL) ANALYSIS doping. tdb Fig.. and for a hypothetical device having a 350-A The substrate doping profile for the 40 keV. F. The concentration at the time is also low. 350-A gate insulator. These predicted profiles were obtained using etching process used to delineate the gates results in a a computer program developed by F. tions [11 ]. Following the AS’5 implant. For comparison. high substrate sensitivity. 6 also shows the substrate gas was performed to decrease the fast-state density. ANNEALING # . sulating oxide layer 2000-A thick was deposited using Using the step profile. all have the same active dose. i ‘E ~ . the active dose in the silicon sensitivity. ing..7 X 10’1 gate insulator like the implanted structure and a con- atoms/cm~ channel implant incident on the 350-A gate stant background doping like the nonimplanted structure. On the other hand. oxide.: ION-IMPLANTED MOSS13T’s 261 V. 5 polysilicon areas. -i ~ +IOEALIZED ~ X3 -/ STEP . and the metalization was applied and delineated.S. case shows a higher threshold. 5. respectively ably low substrate sensitivity. step-function representation of the doping profile. iV~. Predicted substrate doping profile for basic ion-implanted acteristics for non-implanted devices with 200. of Poisson’s equation with appropriate boundary condi- fined. 4 0 ~ \l‘. and 11 min at ized. 5. The one-dimensional model considers only Electrical contact directly to the shallow implanted the vertical dimension and cannot account for horizontal source and drain regions was accomplished by a suitably short-channel effects.I~> [ 131... a steep slope occurs because the . absorbing all of the As” dose incident there. Ns ~ e ..(fo. _ I- ‘. vw~=-l) [v] z:~ 6. polysilicon gate masks the channel region from the im. the projected range and standard both a sufficiently high threshold voltage and a reason- deviation were taken as 1300 A and 500 i%. to-substrate bias for the ion-implanted step profile shown tion an annealing step of 400 “C for 20 min in forming in Fig.. ! \. ideal- implantations include 20 min at 900°C. The high temperature processing steps that follow the modeling purposes it is convenient to use a simple. particularly for V~. Then. . Results of the model are shown in chosen metallurgy to avoid junction penetration due to Fig.and 350-A gate device design for 40 keV BI1 ions implanted through the 350-A insulators. and 40 fI/D for the simple parameters. 6. 1000°C. and for corresponding ion-implanted device with gate insulator.-. Morehead of sloping sidewall which allows a slight penetration of ASP5 our laboratories.2 face and thereby raise the surface concentration.DENNARD ei! al. Typical sheet resistances were 50 O/D offers the advantage that it can be described by a few for the source and drain regions. but with an undesirably sian function added to the background doping level.. The ion-implanted case offers For 40 keV B“ ions. 5. The nonirnplanted 200-A case exhibits a low substrate cent of the incident dose. The gate-to-drain diffusing in the silicon reflect from the silicon-oxide inter- (or source) overlap is estimated to be of the order of 0. For Vs. a final in. < 1 V. _ ORIGINAL :\ IMPLANT t5 l!i m. the nonimplanted 350-A of the implantation is given by the lightly dashed Gaus. After the heat treatments of the subsequent process. 6 which plots the threshold voltage versus source- alloying during the final annealing step. 1 V.. but the magnitude of the threshold voltage is 6. Since the oxide absorbs 3 per.. Calculated and experimental substrate sensitivity char- Fig. a model for determining thresh- low-temperature chemical-vapor deposition. Fig. is shown in Fig. FUNCTION Z* : \\ / ‘1 AFTER 2+ . The three profiles shown in Fig.5 x 10~1 atoms/cm2.

V.8 I .+f not exceed ~. z 4 V. shifts to a lower gate voltage due to a lowering of the Another form of presentation of this data is shown in threshold voltage.1 a ~ . Thus.. For .75 V.8(3 ~vfie~Qd~ – 1 V. the turn-on characteristic especially considering the somewhat different values of L. rcdllccd to the order of 1 p.0 0. and falls by a reasonably response on this semilogarithmic plot) to the Id m Vqz small amount as L is decreased from 2 to 1 p. under worst case.. jected threshold voltage. 6 x 10’1 atoms/cm2 implant was used to achieve this result. A 35 keV. Fig.u~=-IV +// +// +/’ ~. more rapidly with further reductions in L. The threshold voltage occurs at about Fig. the two-dimensional numerical current acteristics were plotted in the manner of Fig. 1 I 1 1 plications. These data agree reasonably well with the calculated curve.fl. as well as for a relatively long- nel length for very short devices is described in the Ap- channel device with L = 10 . complicated for the ion-implanted structure by the non- uniform doping profile which leads to an electric field identified from Fig.—— the depletion region in the silicon under the gate does L= 0. so. H“ v. +. OCTOBER 1974 .6 0. v.. threshold considerably). rather than the slightly higher design value of 40 kel’ and 6. For the ion. bending... and then square-law behavior. While some models have been developed voltage on channel length for basic ion-implanted design with which account for this behavior [14]. vice by a point-by-point computation of the device cur- MOSFET’S with various channel lengths were meas- rent I“or increasing values of gate voltage.u. The computer program was modified by W. the threshold voltage GATE VOLTAGE.~l’ of the source voltage (e. [11]. 8 where the threshold voltage is plotted as a func- 10-7 A where the turn-on characteristics make a transi.. 3 as the actual current at the pro- pattern that is difficult to approximate.17Y I L=9. r 1 i i . the value of 10-7 A was used calculate the turn-on behavior of the ion-implanted de- in all cases with a resultant small error in Vt.2 0.2 .+ . with a fixed substrate bias of g I / . results are shown in Fig. Vd ❑4V -m // // // planted region. the threshold will still be high enough so that the device can be turned off to a negligible conduction level as required for dynamic memory ap. 6 from measurements made on relatively long devices (i. . at inversion the deple.2+ lop ~ 10-6 . As the channel length is and show good agreement with the calculated curves.+/ . = 4 v. 7 for two values of channel The technique for experimentally determining the chan- length in the range of 1 p.b = –1 v. heavier substrate concentrations gave a higher current at The numerical current transport... ‘Ike experimental results are plotted in Fig. for simplicity. 3 they gave transport model of Kennedy and Mock [15]. z – 1 V. Vg (V) is significantly higher for the implanted design which allows adequate design margin so that. Experimental and calculated dependence of threshold by the gate. Calculated lu-ed to test the predictions of the two-dimensional model. When the computed char- implanted case. This current level can also be dccrca. for the of the the I_J???5 12345678 SOURCE-DRAIN SPACING.7 x 1011 atoms/cm2. the problem is V. V*. L (MICRONS) 910 drain field into the channel region normally controlled Fig.4 0. All cases were normalized to a width-to-length ratio of unity. L = 10 . 7 of 4 V was used in all cases. [16] was 4 X 10-8 A at threshold for all device lengths.4 implanted 200-A design.ed and experimental subthreshold turn-on char- conditions (e.8/L 1. short-channel effects which reduce the acteristic for basic ion-implanted design for various channel lengths with V.. However. Experimental results are also given in Fig.g.~-lo If 0.262 IEEE JOURNAL OF SOLID-STATE CIRCUITS. 8.0 1. and a drain voltage pendix.1. Some of the other device designs considered with strate doping profiles considered for these devices. tion of channel length. ground potential to 4 V) is /-EXPERIMENTAL. The threshold voltage is essen- tion from the exponential subthreshold behavior (a linear tially constant for L > 2 p..75p reasonably low and very similar to the slope of the non. the substrate sensitivity over the operating range K n 10-9 y{~. 10-7 tion region now extends into the lighter doped substrate ‘T- U /’r’f’ K and thethreshold voltage then increases relatively slowly K ~ 10-s +1 4’ i with V. The band utilized.. IIwang [171 to handle the abrupt sub.~-5 surface inversion layer in the channel is obtained while CALCULATED.u. at this threshold condition is approximately Chang and P. Calucu!at.b > 1 V. 0.e.. the step width of the heavier doped im. model was used to threshold. h86p J.g. For V. TWO-DIMENSIONAL For devices with one-dimensional threshold voltage sufficiently model lowering (SHORT is inadequate due CHANNEL) short-channel to to account penetration ANALYSIS lengths..p) which have no short-channel effects.

9 for the grounded source condition.0 X 10’1 band voltage of –1.4 .8p laop lo2p 10p BASIC N+ DESIGN (a) ] 7. However.DENNARDet al. Forexample.p. (b) xj=o. with a slightly to the reduced depletion layer widths around the source higher concentration in the surface layer to give the and drain with the lower voltage drop across those j unc- same threshold for a long-channel device [Fig.1 p. This was found to give an ap- is completely depleted at turn-on with a grounded source.I-.1 V is assumed. 10(d) ]. L = 1. Another perturbation from the about the same as for an L = 1. the threshold voltage as a function of channel length for the calculated values show almost identical thresholds com- indicated voltages. the threshold voltage is reason- ably well controlled. drain voltage 4 P V. and turn-on is controlled. Curve tracer parameters. The general shape of the characteristics is the same as those observed for much larger devices. This puts the value of the shallower threshold for this case for a device with L = 0.~ L=o.3 * 0. The next possible departure from much less at threshold. “ circuit applications the nominal value of L could be set somewhat greater than 1 . tion it is possible to use zero substrate bias and still have The first perturbation to the basic design was an increase good substrate sensitivity since the heavier doped region in junction depth to 0. Fig.: ION-IMPLANTEDMoSF@i3 263 CALCULATED THRESHOLD VOLTAGE vd=+4v “9 [ VOLTS ) FOR Ids = 10-7 AMPERES y_?-. tions. particularly near the source where the basic design is the use of a shallower boron implanta. is junctions in perspective. This important improvement is apparently due strate doping lighter by a factor of 2. 10(b). onlY the band bending.”~‘ ~ Vm ? m DEEPER ~+ N+ SOURCE/ORAIN ---- JUNCTIONS Fig. The two-dimensional simulations were also used to test considering that. Also. only half as deep. appears across this depletion tion in the channel region. 10. design. device of the basic basic design which was considered was the use of a sub. wiih a region.0 to 1. the the basic design. Experimental drain voltage characteristics for basic ion. the boron dose implanted in the silicon the sensitivity of the design to various parameters. A flat- plantation energy and dose of 35 keV and 6. Threshold voltage calculated using two-dimensional cur- 6-9 were taken from devices using a B“ channel im- rent transport model for various parameter conditions. atoms/cm2. and W = 12. :TRATE @vm istics for an ion-implanted MOSFET with a I. 10 which tabulates values of more short-channel effects would occur. . +$. No ex- traneous short-channel effects were observed for drain Su voltages as large as 4 V. which may help prevent the penetration of field heavier concentration to give the same long-channel lines from the drain into this region where the device threshold [Fig. 1O(C) ]. Fig.30 Q. The calculations for this case (from 1. In fact. O& O. The experimental data in Figs. 9. With the shallower implanta- tion for the basic design that has been discussed thus far. respectively.P so that. Viewed another way. The experimental drain character. load resistance .5 V apart.l Vfromchip tochipdue to this short- channel effect alone. This would be tolerable for many circuit applications because of the tracking of different devices on a given chip.2 ~.2 p) to obtain a threshold comparable to show appreciably less short-channel effect. the minimum with a heavier concentration to give the same long-chan- device length would have to be increased by 20 percent nel threshold [Fig. the The results for smaller devices proved to be similar to the depletion layer depth in the silicon under the gate is case of deeper j unc~ions.3 pwould give V~ = l. L = 1.if indeed this degree of control ofL can be achieved. 10(a) is an idealized representa- pared to the basic design. gate voltage (U V in 8 steps each 0. 10 (e) 1. .8 p.5E15 J v. with these bias and doping conditions. over an expected range of deviation of L.P.~ = —1 V. With the shallower profile.0 . it was expected that results are given in Fig.4p implanted design with Vs. preciable reduction in threshold voltage for the shorter The last design perturbation considers such a cascj again devices in Fig. The is about 20 percent less in this case.P chan- nel length are shown in Fig.

however. OCTOBER 1974 1. elevated temperature ag- same for this design with zero substrate bias as for the gravates the situation [18].ub = – 1 V case shown in Fig.o. Substrate sensitivity characteristics for ion-implanted 11 and corresponds very well to the calculated values. 13 for different values of L. The consequence for dynamic memory ap.2 1 i [ I I i I 1 I —*— . o obtain a shallower implanted layer of approximately 1OOO-A depth [11]. 6. even though the zero substrate bias changes are indicated in terms of the dimensionless scal- .264 IEEEJouRNALoF soLm-STATECIRCUITS. 12 for differ- old turn-on characteristic. 11. ● Vd =4 VOLTS (EXH I A Vd =4 VOLTS (THEORY) 1- 1 t 1 I I I I I I 0.8 ~ %’ a i ~ 0. The results barely suitable if the device is turned off by bringing its show that the substrate sensitivity is indeed about the gate to ground. Experimental and calculated dependence of threshold voltage on channel length for ion-implanted zero substrate bias design. characteristic with relatively lower thresholds at high values of source (and drain) voltage.+ f o 1 > 20 KeV. 1. Experi- mental devices corresponding to this design were built and tested with various channel lengths. 12. CIRCUIT PERFORMANCE WITH SCALED-DOWN DEVICES The turn-on characteristics for the zero substrate bias design.u~ = —1 V. it is worthwhile to review its properties more fully.05 VOLTS (EXI?) g 0.4 - g + Vd = 0. These plications is that. For such applications the ent values of L. Fig. Data on threshold voltage for these -substrate Vsource (VOLTS) devices with 4 V applied to the drain is presented in Fig. the performance changes due to size reduction alone case than for the V. as expected. and substrate doping in the same manner as the paper [11 ].0 x 10” atoms/cm2 Bll implant was used to ~. parably small dimensions is discussed in this section. The relatively small very small MOSFET’S in integrated circuits of com- shift in threshold for the short-channel devices is evident.<p:*--———— k— *—* ~ Lo - -1 2 0 ~ 0. original design with V. the turn-on rate is considerably slower for this First. device changes described with respect to Fig. this advantage is offset by the flatter subthresh- on source-to-substrate bias is shown in Fig. 7. for dynamic memo~. Note that the smaller the basic design with V@ = – 1 V presented earlier is devices show a somewhat flatter substrate sensitivity preferred. CHARACTERISTICS OF THE ZERO SUBSTRATE ‘“’r————————————l BIAS DESIGN Since the last design shown in Fig. zero substrate bias design with channel length as parameter. both experimental and calculated.0 01234 678910 L?(p) Fig. Data for a small drain voltage is also given in this figure. In this case a 20 keV. are shown in The performance improvement expected from using I?ig. Furthermore. Thus.6. This are obtained from the scaling considerations given earlier. showing much less variation of threshold with channel design offers improved threshold control for strong in- length. is discussed in some detail for these devices in another voltages. is dropped across the gate insulator capacitance rather Table I lists the changes in integrated circuit perform- than across the silicon depletion layer capacitance. This ance which follow from scaling the circuit dimensions. The dependence of threshold voltage version. is due to the fact that the depletion region in the silicon The influence on the circuit performance due to the under the gate is very shallow for this zero substrate bias structural changes of the ion-implanted design is then case so that a large portion of a given gate voltage change discussed.6Ellcm”2 2 0.2 . 13 is a constant low value for this measurement. The drain-to-source voltage was held at noise margin with the turn-on characteristic of Fig. 10(e) appears to be better behaved in terms of short-channel effects.

and furthermore because the MOSFET circuits. R~ = pL/Wt K Normalized voltage drop IR~/V K . the cooling problem is essentially unchanged.4NTED iWOSFET’S 265 . + Line resistance. and reduced depletion layer widths.6EII cm-z SCALING RESULTS FOR INTERCONNECTION LINES ]o-6 .. . the resistance of a given line increases directly with the It is argued that all nodal voltages are reduced in the scaling factor K. The problems may be percentage accuracy. The circuits operate properly at density in a scaled-down conductor is increased by K. This follows because the quiescent voltage levels times greater in comparison to the lower operating volt- in digital MC)SFET circuits are either the supply levels ages. The IR drop in such a line is therefore miniaturized circuits in proportion to the reduced supply constant (with the decreased current levels) ~ but is K voltages. which will be propagation over long lines is involved.4 V). Thus. For the implanted dcviccs with the higher operating volt- ponents. Scaling Factor It is assumed here that the thicknesses of the conductors Device dlmensiontO.4 0.0-8 Line response time R~C 1 L=l. even if many more circuits are placed on a given integrated circuit chip. L.: 10N-1MH. Justifying these results here in great detail any increase in conductivity. . Noise margins are reduced. V. lines for signal propagation.e. Parameter Scaling Factor . are necessarily reduced along with the widths because Doping concentration Na K of the more stringent resolution requirements (e. the power density remains constant.0-7 W%~~ENTAL /.-5 . . TABLE II 20 KeV. because of the reduction by K’ in the area of these com.0-10 ~.lp .2 0. The response time of an unterminated transmission or some intermediate level given by a voltage divider line is characteristically limited by its time constant consisting of two or more devices. W’ 1/.2 1.[ CTvj ances V/I sultant reduction factor of K. 13. and is also reasonable for degenerately doped semiconducting lines where solid volubility and impurity scattering considerations limit ing factor K.DENNASDet at. etc. the current examined subsequently. These reduced ca- “ A pacitances are driven by the unchanged device resist- . Fig. In conventional scales as shown in (2). the current level will be reduced . Calculated and experimental subthreshold turn-on char- acteristics for ion-implanted zero substrate bias design. which is partially cancelled by the decrease in ages (4 V instead of 3 V) and higher threshold voltages the electrode spacing by K due to thinner insulating films ( *) .j on Voltage V 1/. TABLE I As indicated in Table II. lower voltages because the device threshold voltage Vt which causes a reliability concern. etching. L=lOp ~ Line current density I/A K & 10-9 .0 1. interconnection lines as well as devices) will have paper will give similar performance improvement to that their capacitances reduced by a factor of K. Since the area of a given device or circuit is also reduced by K2.8 1. simplified treatment is given. Under these assumptions would be tedious. but they become significant for line- as well if each parameter in (2) is controlled to the same widths of micron dimensions. This occurs of the scaled-down device with K = 5 given in Table I. ). a number of problems arise SCALING RESULTS FOR CIRCUIT PERFORMANCE from the fact that the cross-sectional area of conductors Device or Circuit Parameter is decreased by K2 while the length is decreased only by K.9 V instead of 0. this makes ance V/I of each device is unchanged by scaling. Also. but at circumvented in high performance circuits by widening the same time internally generated noise coupling volt.. vg [v] so the power-delay product is improved by K8. the power buses and by avoiding the use of n+ doped ages are reduced by the lower signal voltage swings. Current 1 1/..=4V / v$.0.4 duced by K’ due to the reduced voltage and current levels. R~C. however. all circuit elements Use of the ion-implanted devices considered in this (i. so only a. The giving decreased transition in the delay time of each circuit by a power dissipation of each circuit is re- times with a re- o 0. Power dissipation/circnit VI very small dimensions (until the mean free path becomes 1 /K2 Power density VI/A 1 comparable to the thickness). The conductivity is considered to remain Capacitance EA It l/K constant which is reasonable for metal films down to Delay time/circuit VC/Z 1/.6 .~=o .. which is unchanged by scaling. An it difficult to take advantage of the higher switching assumption is made that parasitic resistance elements are speeds inherent in the scaled-down devices when signaI either negligible or unchanged by scaling. Due to the reduction in dimensions. these conductivity problems are re- tolerance spreads on Vt should be proportionately reduced latively minor. and because the resist.

. Vg=Vt+ 0. and pCl. The experimental values of W and l?. and Rla. These considerations are applicable to highly I 2 3 4 miniaturized integrated circuits fabricated by high-re. 14. and to deduce W from the resistance of a long.. = (V. and / AL=0.l is the load resistance of the measurement cir- APPENDIX cuit. Also presented was an ion-implanted design in.0 x 10” atoms/cm’ B“ channel implant. slender. length L for very small MOSFET’S from ex. or per- formance. The general objective of the study pendent of L.(.m (Al) these difficulties without sacrificing device area. All device capacitances ate about a factor of two less in the im. /! z + than a factor of two. on range. value of W. the channel sheet resistance is relatively inde- rameter combinations. where Rc is the contact resistance of the source or drain. region. Lmosk (}) solution lithographic techniques such as electron-beam Fig.. with a l-P channel length for high-density source-fol.OCTOBER 1974 in proportion to (Vg — T’t) ‘/tox to about 80 percent of the 12 I I 1 J current in the scaled-down device. Finally R.. A consistent set of scaling relationships channel length. The power dissipation II - per circuit is thus about the same in both cases.... An example of this The most satisfactory combination of subthreshold turn.!- vices. and an applied substrate bias of n+ sheet resistance allows us to compute the source and – 1 V...(R. a plot of w&han versus L~.. Then. For a fixed value of V~ — Vt > particularly valuable in predicting the relative degree of 0. fabrication. and n+ interconnection lines will show 20 KeV. The procedure is EXPERIMENTAL DETERMINATION OF GHANNEL LENGTH more simple and accurate if one uses a set of MOSFET’S A technique for determining the effective electrical having different values of L~. threshold control. however.~~the sheet modified for use with ion-implanted structures proved resistance of the channel. 8.nnsl.86P I- characterization of very small MOSFET switching de.~~ — L. and R.ll axis at AL because AL = L~. v~ub=f) ments such as metal interconnection lines would be ~ 47 – essentially unchanged so that the overall capacitance z improvement in a typical circuit would be somewhat less x6 .~ but all with the same channel.f/.Then one needs only to plot Rchan versus perimental data is described here. The delay time per circuit which z & 5- is proportional to VC/I thus appears to be about the +/ same for the implanted and for the directly scaled-down 4- micron devices shown in Fig.!. the sizable performance improvement expected from using very small MOSFET)S in integrated circuits of (A2) comparably small dimensions was projected. technique is illustrated in Fig. The technique is based L. 4 x 10’5 atoms/cm’ As” source/drain implant..5 V with a small applied drain voltage of 50 or 100 mV. and with the device turned on in the below-pinchoff short-channel effects arising from different device pa. First. Illustration of experimental technique used to determine pattern writing. 10.05 VOLTS ing ancl dec~:ased junction depth.. +/: planted devices.J1.he Lm.hnn= VC.266 IEEEJOURNALOFSOLID-STATE CIRCUrrS.j =0. It was then shown how an all ion-implanted structure can bc used to overcome WR. The channel resist- tended for zero substrate bias that is more attractive from the point of view of threshold control but suffers ance can be calculated from from an increased subthreshold turn-on range. – I. a relatively large four-point probe structure. were presented that show how a conventional device can be reduced in size. L. 14. + R. . 6. used in Fig. /1 00 . this direct scaling approach leads to some challenging technological requirements on the observation that such as very thin gate insulators. + 2Rc + R1omi))/Id. a 100 of the icm-implanted n+ region was determined using a keV. sion due to exposure and etching. 4.6EII Cniz 9– the same improvement due to the lighter substrate dop.].w = LP. drain resistance R. Id was determined at VO = Vt + 0. Knowing the 350-A ~gate insulator. n+ line. and substrate sensitivity was achieved by an experimental lMOSFET that used a 35 14 were obtained as follows.~~~ 1s the channel resistance.k will was to design an n-channel polysilicon-gate MOSFET intercept t. 1 / NJMMARY 2- / This paper has considered the design..5 VOLTS +/ V.. Some capacitance ele. where AL is the processing reduction in the mask dimen- lower circuits such as those used in dynamic memories. the sheet resistance keV. A two-dimensional current transport model where li. in cwder to determine AL. / L= Lma~k-AL 3.

.. “ in Tech. R. N. April 1972. Dec. group which is exploring high density digital integrated circuits cation of ion implanted high-performance FET circuits. L. Dig. p. 16. vol. Since 1971 he has been manager of a [11 F. “An analysis of the threshold voltage for short While at the University. H. and A. Tingj “Electron-beam fabri. Dennard.. and M. Prior to 1966 he served as Assistant Pro. trons in inverted Si surfaces. 17.” IEEE J. H. Tex. Smith. Circuits. Vt. J.” in Tech. Dennard. 138-140. S. ~i~ital u. pp. high resolution replication process. Int. F.” IBM J. Voshchenkow. Develop. “Impact of electron beam integrated circuits like miniaturization. degrees in electrical engineering B. E. and Ph. Dr. Germany. R. J. Hwa-Nien Yu (M’6. [141 H. in [51 D. of new devices and circuits for logic and paration and testing activities. [111 V. Feb. and C.” Solid State Tech. Kennedy and P.nol. 146-153. Since joining the IBM cal theory for the insulated gate field effect transistor. the Dipl. Dennard. [2] J. where he is currently a IEEE Int. 1407. I.. memory applications. ..S. R. R. member of a semiconductor device and process design group. Troutman. vol. In 1966 he joined the IB”M T. vol.i [41 ‘R. 1973. 44-46. “Ion-implanted comple- mentary MOS transistors in low-voltage circuits. p. The devices were fabri. H. Gaensslen. p. Rev. sisters. F. 1973. Mallcry. “Transport properties of elec. Mock. 830-841. Pa. where he worked with a group exploring large-scale integra- tion (LSI). low-noise transistor fabricated with electron beam lithography. Germany. Hwang and W. H. p.” in IAWCC Dig.” Solid-State Elec. Dall- as. Int. Gaensslen was born in Tuebingen. “Subthreshold design considerations for the Manager of Semiconductor Technology at the IBM T. respectively. After working with the Advanced Sys- the insulated-gate field-effect transistor. Tex. device simulation. Washington. His current technical interests involve various aspects of advanced [81 A.” IBM J. ‘{Device design considerations for ion implanted n-channel MOS- FET’s. pp. Publication). eds.. Vat. He received dom access 1024-bit memory made with electron litho.S. Yorktown Heights. M. Res. Yu. private communication. 15. and 1958. China. Gaensslen. Y. tems Development Division from 1959 to 1962. Bur. [31 H. “Projection masking. ” Ph~s. Chang and P. SC-9. engineering from the University of Illinois. in 1932. he has been IBi14 J.” Soiid-State Electron.. Kuhn. Wadsack. Ing.. menium dcvicc technology. Schuster. M. Electron Devices Meeting. LeBlanc. Sci. P. ‘[A high speed p-channel ran. Electron Devices Meeting. Illiac-11 computer. Swanson and J. Develop. During this period he was working on the synthesis of linear and [71 R. Pease.~ networks.” IBM J. experimental high-density memory array fabricated with electron beam. p. S. he rejoined the tron.S. Critchlow. Murley. DiLonardo assisted with the mask pre. N. and H. 55. 601. Germany. Fung. Technol. and L. 16.5) was born in Shanghai. private communication. fessor in the Department of Electrical En- [61 S. Broers and R. D. We wish to acknowledge the valuable contributions of and M .. degrees in electrical [131 W.D.Y. C. Pankrantz. Munich. B. 1929. Dig. B. “A two-dimensional mathematical model of device research activities. Y. . R. Silicon ion implantation. L. and ion implantations and related design information. Electron Devices Meeting. “. Urbana.. assignment at the IBM Laboratory. April 1974. Munich. S..4NTEDMOSFET’S 267 ACKNOWLEDGMENT Robert H. L. “A high- gain. pp. Pittsburgh. C. 1082. N.. search Assistant in the Digital Computer 1973. “Design Sclmft. 1. Rideout. L. Dr. N. pp. Watson Research Center. A. Tech. Lee. 430. SC-7. Middlehoek. M. insulated gate field-effect transistors. Crowder and F. tcrn exposure. vol. IBM System Products Division. “Steady state mathemati. 619. vol. Fowler. to be published. 14. Fang and A. J. T. 1973. ~:~ inn~fereuce effects. 17. and FET memory RE~EREN-CES cells and organizations.” presented at the search Center. F. vol. J. [101 R. F. 1973. versity of Munich. Yuan. ~pears and H. Dec.D. ?vIorehead who provided the from . Yorktown Heights. MOSFET device and integrated circuit design. 1973. H. vol. Fritz H.. Solid-State Circuits. Ing and Dr. 21. trical engineering from the Technical Uni- 1973. ” Research Laboratory in 1957. Gaensslcn is a member of the Nachrichtentechnische Gesell- [91 D. Laboratory and worked on the design of the [151 D. characteristics of n-channel insulated-gate field-effect tran. M. 1972. Solid-State Watson Research Center. N. Res. Creagh. respectively. Huff and R. and technology on silicon device fabrication. “Design of micron MOS switching devices. degree from Carnegie Institute of important were the contributions of l?. ” IEEE J. Res. p. !w–wl inn . Johnson. Boeblingen.. T. P. 1973.. Yu. . 1972. 1931. IBM System Products Division. vol. R. From Scptcmbcr 1973 he was on a. 1954. gess. Hatzakis. “X-Ray lithography—a new 1959 and 1966. N. Since 1963 he has been cated by the staff of the silicon technology facility at the at the IBM T. Papers. vision where his experience included study Walker and V.. on October 4.” Semicond. Technology. engaged in various exploratory solid-state [161 M. P. 10.. p.Y. Yorktown Heights. vol. p. S. H.. He is currently [181 R. H. and R. C. H. Fishkill. on January 17.: ION-IMPL.Southern Methodist University. Research Division in 1962 to work on the ultra-high speed ger- [171 W. Dennard (M’65) was born in Terrell. Meindl. Sot. [121 F. Chang. degrees in elec- graphy. N. respectively. T. Hwang. Res. Technical University of Munich. J. while making contributions in cost and yield models. E.. D&nard. ‘H. Develop. he was a Re- channel IGFET’s.DENNARDet U1. advanced silicon LSI device technology research. In 1958 he joined the IBM Research Di- Chang to two-dimensional device computations. 1973. p. in 1953. and S. W. one year (Electrochem. Watson Research center. ” using advanced technology concepts such as electron beam ~at- J. Watson Re. D. Henderson. vol. Yu is a member of Sigma Xi. F. in 1954 and 1956. 169. Since 1967. Also the Ph. Hatzakis. he has been engaged in Essex Junction. L. and devclo~ment of advanced datz communication techniques. Germany. J. H. in 1958. Dec. M. L. T. He received the 1968. thin photoresist layers gineering. He received the B.

on September 1. C. Esaki where he worked on fabrication and contact technology for multi- heterojunction “superlattice” structures using gallium-arsenide.. Yorktown Heights.C. in 1959 he took an educational leave of Ernest Bassous was born in Alexandria. Alexandria. Egypt. R.268 IEEE JOURNALOF SOLID-STATE CIRCUITS. in 1957. LeBlanc (M’74) received the B. Burlington. Tau Prior to joining IBM. Eindhoven. oratory. . Edison Research Stanford.E. His present research interests concern respectively. The Netherlands.. degree in physics from the University of Dr.Y. Essex Junction. British Boys’ School. Dr. Crowell concerned thermally In 1964 he joined the IBM Research Lab- assisted current transport in platinum sili. the Exploratory Memory Group at the IBM Laborato~. Since 1972 he has been degree in electrical engineering. His thesis work at U. Phi Kappa Phi.S. germanium transistors and metal-semiconductor Schottky barriers Mr. Brooklyn. his activities included studies in arc dis- sity of Southern California (U.S. phosphide and gallium-aluminum-arsenide. Albuquerque. tions and twelve papers.Y. d’Etudes des Telecommunications. de. SC. he was affiliated with G. N.S. Patents. the M. He received the B. He received the B.E.. degree in Laboratory in West Orange.). ultra violet absorption Angeles. Watson Research Center. Assistant in the department of Materials Science at the Tech- nological University of Eindhoven. studying acoustoelectric effects in cadmium sulphide. to work cide Schottky barriers. J. R. in 1962. Andre R. in 1941. worked at the Thomas A. on semiconductors. Seine. degree in chemistry from the Uni. Beta Pi. N. N. Prof. and the D. Eta Kappa Nu. as well as several IBM Technical Re- From 1954 to 1959 he taught Chemistry and Physics at the ports. in 1956 and 1959. He is presently a member of 1931. Brooklyn. Rideout is a member of the Electrochemical Society.E. He is the author or co-author trical engineering from the University of of 20 technical papers and 3 U. In 1966 he spent a year as a Research the American Association for the Advancement of Science. In 1970 he joined IBM Research in the device research group of Dr. Dennard at the IBM T. Junction. He went to France in Dr.S.S. and the MS.Y. New Mexico.S. absence to complete his doctorate. and organic semiconductors.E.S. as an electrical engineer and also with Sandia Cor~oration in conjunction with the Uni- versity of New Mexico.D. Issy-les- sity of Wisconsin.E. degree in elec- high density silicon FET technology.C. Madison. Calif. LeBlanc is a member of Sigma Xi and Tau Beta Pi.. Essex versity of London. where materials science in 1970 from the Univer.J. SC. Leo Rideout (S’61–M’65) was born in 1959 where he worked for 1 year on infra N. N. in 1965. He has authored five publics. and the a member of the semiconductor device and circuit design group M. and the Ph. Yorktown Heights. and Sigma Xi. As a member of the Research staff he is pres- From 1963 to 1965 he was a member of the technical staff of ently engaged in the study of materials and processes used in Bell Telephone Laboratories where he worked on high-frequency the fabrication of silicon integrated circuits. of Vermont. L. under spectroscopy. From 1960 to 1964 he degree in 1964 from Stanford University. Vt. Egypt. Londonj England in 1953. Los charge phenomena. red detectors at the Centre National gree with honors in 1963 from the Univer.J. where his current technical interest includes a study of degree in physical chemistry from the Polytechnic Institute of short-channel MOSFET devices.OCTOBER 1974 V. Bassous is a member of the Electrochemical Society and on potassium tantalate. Moulineaux.