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UCC1837

UCC2837
UCC3837
8-Pin N-FET Linear Regulator Controller
FEATURES DESCRIPTION
• On Board Charge Pump to Drive The UCC3837 Linear Regulator Controller includes all the features re-
External N-MOSFET quired for an extremely low dropout linear regulator that uses an external
N-channel MOSFET as the pass transistor. The device can operate from
• Input Voltage as Low as 3V
input voltages as low as 3V and can provide high current levels, thus pro-
• Duty Ratio Mode Over Current viding an efficient linear solution for custom processor voltages, bus ter-
Protection mination voltages, and other logic level voltages below 3V. The on board
• Extremely Low Dropout Voltage charge pump creates a gate drive voltage capable of driving an external
N-MOSFET which is optimal for low dropout voltage and high efficiency.
• Low External Parts Count The wide versatility of this IC allows the user to optimize the setting of
both current limit and output voltage for applications beyond or between
• Output Voltages as Low as 1.5V
standard 3-terminal linear regulator ranges.
This 8-pin controller IC features a duty ratio current limiting technique that
provides peak transient loading capability while limiting the average
power dissipation of the pass transistor during fault conditions. See the
Application Section for detailed information.

BLOCK DIAGRAM
VDD CS CAP
1 8 2

CHARGE LEVEL
5 VOUT
PUMP SHIFT

CURRENT SENSE
AMPLIFIER ERROR AMPLIFIER
140mV
6 FB
+

UVLO
CURRENT SENSE 1.5V REF
COMPARATOR
100mV 3 GND
TIMER
+

7 4
CT COMP UDG-99145

SLUS228A - AUGUST 1999

. .65 3.00 V Minimum Voltage After Start 1. +300°C Currents are positive into. . . . . FB . .3 1. .5 1.4 0. . . Consult Packaging Section of Databook for thermal limitations and considerations of packages. . . . .5 5 µA Current Fault Timer CT Charge Current VCT = 1V 16 36 56 µA CT Discharge Current VCT = 1V 0. . . .7 V Fault Duty Cycle 2 3. –55°C to +150°C Lead Temperature (Soldering. .545 V Current Sense Comparator Offset 0°C to 70°C 90 100 110 mV Comparator Offset –55°C to 125°C 85 100 115 mV Amplifier Offset 120 140 160 mV Input Bias Current VCS = 5V 0. SOIC-8 (Top View) Storage Temperature . .) . CCAP = 100nF. . –0.6 2. . . . . ELECTRICAL CHARACTERISTICS: Unless otherwise specified. . 10sec.5 mA VDD = 10V 1.4 1.65 V Reference ( Note 1 ) VREF 25°C 1.530 V –55°C to 125°C 1. . . .9 µA CT Fault Low Threshold 0.3 5 % Error Amplifier Input Bias Current 0.45 0. . D Package Junction Temperature . . . .5 1. .455 1. . . . . –65°C to +150°C J or N Package. .3V to VDD + 0.00 2. . . . . . UCC1837 UCC2837 UCC3837 ABSOLUTE MAXIMUM RATINGS CONNECTION DIAGRAM All pins referenced to GND . . .6 V CT Fault Hi Threshold 1. . . . . –0. . . .2 1. CT. . . –25°C to 85°C for the UCC2837 and 0°C to 70°C for UCC3837. . . . . . . . . PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Input Supply Supply Current VDD = 5V 1 1.5 0.3V to +15V CS. . .2 2 mA Under Voltage Lockout Minimum Voltage to Start 2.5 2 µA Open Loop Gain 60 90 dB Transconductance –10µA to 10µA 2 5 8 mMho Charge Current VCOMP = 6V 20 40 60 µA Discharge Current VCOMP = 6V 10 25 40 µA 2 .3V DIL-8. . . .5 1. CT = 10nF.2 2. .515 V 0°C to 70°C 1. . . .25 0. VDD = 5V. . negative out of the specified terminal. .485 1. . .470 1. . . . . TA = –55°C to 125°C for the UCC1837.6 V Hysteresis 0. . . .5 1. . . . . .

The voltage is used to provide gate drive current to the exter.7 V VDD = 4. CAP can be directly connected to an exter.5V. The UCC3837 can operate in several guide for understanding the operation of the circuit states including having the error amplifier disabled (shut shown in Fig. current loop when Current Sense Amplifier is active in over curret mode). and should be used as a from its ideal level. VDD = 5V. This pin side of the Current Sense Amplifier and Comparator. There is an internal 5V clamp at the input The charge pump output is designed to supply 10µA of of the charge pump however that insures the voltage at average current to the load which is typically the CAP does not exceed the ratings of the IC. VDD: The system input voltage is connected to this point. For accurate out- fier and current sense amplifier. A capacitor is connected between this pin and GND to provide a is connected from this pin to GND.5V COMP: The output of the transconductance error ampli.5V. at the CAP pin. VOUT: This pin directly drives the gate of the external N-MOSFET pass element. The charge pump output has Unitrode Application Note U-152 is a detailed design of a a typical impedance of 80kΩ and therefore the loading of low dropout linear regulator using an N-channel the IC and the external gate drive reduces the voltage MOSFET as a pass element. IOUT = 0µA 8. VDD must be above 3V.5 1. –55°C to 125°C 7. CCAP = 100nF. This CAP MOSFET gate capacitance present at the VOUT pin. TA = –55°C to 125°C for the UCC1837. IOUT = 10µA.5 9 V Charge Pump CAP Voltage VDD = 4.5 V Note 1: This is defined as the voltage on FB which results in a DC voltage of 8V on VOUT.01µF ceramic capacitor is rec. down). Used for compensating put voltage regulation. IOUT = 10µA. nal regulated source such as +12V.5 V VDD = 12V. –25°C to 85°C for the UCC2837 and 0°C to 70°C for UCC3837. setting the maximum floating bias voltage for an N-Channel MOSFET gate ON time of the over current protection circuits. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS FET Driver Peak Output Current VCAP = 10V. in normal linear regulation mode. GND: Ground reference for the device. GND should be referenced to the the small signal characteristics of the voltage loop (and output load ground. A capacitor CT: The input to the duty cycle timer circuit.4 9. 1. VOUT = 1V 0.5kΩ. and in overdrive mode where the linear regulator is responding to a tran- Charge Pump Operation sient load or line condition. capacitor value used at CAP is chosen to provide holdup nal pass element as well as bias current to internal sec- 3 .5V. The nominal DC operating N-Channel MOSFET. The typical output impedance of this pin is 6.5 mA Average Output Current VOUT = 1V 25 100 175 µA Max Output Voltage VDD = 4. See the drive. C/S = 0V 11 12. The maximum output voltage The internal charge pump of the UCC3837 is designed to available at VOUT is shown in Fig. A minimum of a 0. C/S = 0V 15 16. 2 for these various create a voltage equal to 3 times the input VDD voltage modes of operation. CT = 10nF. APPLICATION INFORMATION Topology and General Operation tions of the UCC3837 itself. UCC1837 UCC2837 UCC3837 ELECTRICAL CHARACTERISTICS: Unless otherwise specified. should be connected through a low noise path to the low side of the current sense resistor. FB: The inverting terminal of the voltage error amplifier. Application Section for programming instructions. in which case the used to feedback the output voltage for comparison with external voltage will be the source for driving the the internal reference voltage. PIN DESCRIPTIONS CAP: The output of the charge pump circuit. 0°C to 70°C 8 9 V VDD = 4.5 2. ommended. VDD also acts as one CS: The negative current sense input signal.5V. voltage at this pin is 1.

The value of CAP also determines the startup time of the linear regulator. which A second method of disabling the UCC3837 is to place a may be useful when a standard level MOSFET is used or short circuit across CCOMP. resulting in a lower volt- source should be decoupled to GND using a minimum of age at CAP.020 14 OVERDRIVE UCC3837 13 LINEAR REGULATOR C1 330µF CS 8 12 Q1 E/A DISABLED 1 VDD IRL2203N 11 OR EQUIVALENT VOUT VOUT 5 3.3V 10 2 CAP ON/OFF R2 C3 9 1. 5A RDS(on) value. This pole can be canceled by programming a zero fre- A MOSFET used in linear regulation is typically operated quency on the output of the UCC3837 error amplifier at a gate voltage between the threshold voltage and the equal to the pole frequency. With an external source applied completely discharged. 3 indicates on the input voltage. and the that in the normal operation of a linear regulator using a available voltage at VOUT as discussed previously. An external voltage such as +12V may be tied to the CAP pin directly to insure a higher value of VOUT. Therefore: gate plateau voltage in order to maintain high gain. Typical VOUT(max) vs. The device used to charge pump output impedance (typically 80kΩ) and the short the output of CAP should have a very low leakage value of the capacitor on CAP. of the CAP voltage should the external load exceed the when minimum dropout voltage is required. Fig.1µF 5 4 COMP 3 4 5 6 7 8 9 10 11 12 RCOMP VDD 10k CCOMP Figure 2. This will have an advantage when VDD is very low and the resulting VOUT voltage of a quicker restart time as the voltage at CAP will not be may need to be higher. Typical application 5V to 3. the gate capacitance can be predicted directly MOSFET selection should be based on required dropout from the MOSFET characteristic charge curve.8k 1000µF Q1 0. but this ∆Qgth type of MOSFET will have higher gate capacitance which C IN = ∆Vgth may result in a slower transient response. A lower RDS(on) relationship: MOSFET is used when low dropout is required.The external +12V amplifier with this configuration. VDD. average current. UCC1837 UCC2837 UCC3837 APPLICATION INFORMATION R1 15 5V 0. The voltage at CAP Grounding the CAP pin will remove the drive voltage and charges up with a time constant determined by the effectively disable the output voltage. using the voltage and gate drive characteristics. ROUT. The MOSFET should only be operated in the non-linear (switch) mode under transient conditions. since even a few microamps will lower the charge pump voltage. typically 6.3V. the required gate drive. the maximum voltage at VOUT will be approxi. 820pF UDG-99137 mode of operation is linear. a 0. which occurs during load and line tran- Disabling the UCC3837 sient conditions. This 4 . down by the typical 40µA charging current of the error mately 1V below the external source. current when in the OPEN state. Compensating the Error Amplifier Choosing a Pass Element Using a MOSFET as an external pass element intro- The UCC3837 is designed for use with an N-channel duces a pole in the control loop that is a function of the MOSFET pass element only. and a logic level or standard gate level MOSFET depending the MOSFET input gate capacitance.01µF capacitor. The designer may choose UCC3837 output impedance.5kΩ.5k GND 3 6 7 CT 0.1µF FB 6 8 R3 7 1. and therefore the channel re- sistance is higher than the manufacturer’s published Figure 1. MOSFET. The charge pump will be loaded to CAP.

The response of the voltage at the gate of the ex. If at 2 • π • C IN • ROUT any time the voltage across the current sense resistor 1 crosses the comparator threshold. 5 . MOSFET turn-on characteristics.7µs. if the current forces 140mV across the 1 sense amplifier. timing capacitor voltage and ternal pass element is therefore a function of the 1. The error am- plifier will then slew at approximately 50mV per micro- second as the 40µA charges CCOMP. During the 3% on time. With 1.5mA. The value of VOUT will increase the same amount as the UDG-97046 increase in the error amplifier output. is internally limited to 1.6V. Load current. to deliver 5A is 2. Note that the initial where CIN is the MOSFET input capacitance and ROUT is fault time is longer than subsequent cycles due to the the output impedance of VOUT.5V. The output of the amplifier will therefore respond by first stepping the voltage propor- tional to 40µA times RCOMP. Figure 3. however. Fig.6V. the required time UDG-97046 to charge the gate is therefore 4.) For the application circuit shown in Fig. the UCC3837 error amplifier will increase its charge current to a typical value of 40µA. Figure 4. the typical required gate voltage at room temperature. fact that the timing capacitor is completely discharged The value of CCOMP should be large enough that and must initially charge to the reset threshold of 0. the voltage at the error amplifier output will increase quickly by 400mV due to the 40µA current through RCOMP.5mA output voltage under fault conditions. where the output current steps from a low value to a high value. Dynamic response can therefore be improved by increasing RCOMP and decreasing CCOMP . In re- sponse to the decrease in feedback voltage at FB. The UCC3837 out- put gate drive current. the UCC3837 begins F ZERO = F POLE = 2 • π • RCOMP • CCOMP to modulate the output driver at a 3% duty cycle. From the IRL2203N data sheet. Consider a load tran- sient on the application circuit of Fig. as obtained from the MOSFET data sheet gate charge curve. the UCC3837 will enter a constant out- RCOMP CCOMP = 2 • π • F POLE put current mode. approximately 7nC charge is required to change the gate voltage from 1.5mA gate drive current. Transient Response The transient performance of a linear regulator built us- ing the UCC3837 can be predicted by understanding the dynamics of the transient event. Overcurrent Protection and Thermal Management: Overcurrent protection is provided via the UCC3837’s in- 1 F POLE = ternal current amplifier and overcurrent comparator. parasitics connected to COMP do not effect the zero fre- quency. drive current and the external gate charge. and then ramping up pro- portional to 40µA and the value of CCOMP. From the gate charge curve for the IRL2203N. Initially. UCC1837 UCC2837 UCC3837 APPLICATION INFORMATION (cont. the output voltage will drop as a function of the output capacitors ESR times the load current change. The threshold for the device is approximately 1.5V. 4 illustrates the cyclical retry of the UCC3837 under fault conditions. 1.5V to 2. A minimum of 220pF is recommended. 1.

6 0. load current. assume a maxi. The cycle will sink resistivity of θCS = 0. The Using Printed Circuit Board Etch as a Sense Resistor minimum required fault time can then be calculated as Unitrode Design Note DN-71 discusses the use of follows: printed circuit board copper etch as a low ohm sense re- COUT • VOUT (2) sistor. Fault time vs. under short circuit conditions. The application circuit shown in Fig.25V input and a t FAULT = CT • = CT • = 27. sense resistor to result in a 100mV current sense com- ing for CT. parator signal for the UCC3837.8 °C/W or less should suffice. 25 − 7 • (0 . the 6 . to maintain a 125°C junction temperature can be calcu- lated as follows: 30 T J = T A + P (θ JC + θCS + θ SA ) (5) 25 125 = 50 + 9 . demanding a 20mΩ stituting equation (1) for tFAULT in equation (2) and solv. and the maximum output current.4 0. 5 (1) not the full short circuit power. 1. constant cur- function of temperature. With a 5.57 inches long results in a resistance of 20mΩ at an ambient temperature of 70°C and an operat- Switchmode protection offers significant heat sinking ad- ing current of 5A. the heat sink required then repeat.8W. the ing an ambient temperature of 50°C and a case to heat charge accumulated on the output capacitance will be depleted by the load during the “off” time. This leaves nal dissipation. 8 • 10 • (I MAX − ITRIP ) 3 wide and 1. with a 5A average load current. 02) − 3 . a 1 ounce outer layer etch of 0. The maximum ambient temperature of the linear regulator is 70°C. almost four times the nomi- mum load current just less than the trip limit. This linear regulator is designed The minimum timing capacitor can be calculated by sub. 25W The “on” or fault time must be of sufficient duration to Given that the thermal resistivity of the MOSFET is spec- charge the load capacitance during a normal startup se- ified as 1°C/W for the TO-220 package style and assum- quence or when recovering from a fault. 5 − 0. If not. Since the average power during a fault atures will be higher. P = ( 5 . 1 can I MAX − ITRIP be used as an example. 25 − ( 5 • 0.8 1 CT (uF) P= [(5. the current limit at lower temper- rent solutions.8 • 10 3 • CT maximum output current of 5A. according to the following equation: sorb the maximum steady state power dissipation and ∆V 1. 25 • (1 + 0. dissipation would be 35. timing capacitance. as shown in Fig. UCC1837 UCC2837 UCC3837 Fault time duration is controlled by the value of the timing heat sink need only have adequate thermal mass to ab- capacitor. timing capacitance. 6. 8 ° C FAULT TIME (ms) 20 W 15 Based on this analysis. CT. condition is reduced as a function of the duty cycle.05 inches 27 . The current in 10 the circuit of Fig. will be limited to 7A at a 3% duty cycle. Because the resistivity of copper is a vantages when compared to conventional.3 + θ SA ) θ SA ≤ 6 . 07W Figure 5. resulting in a MOSFET 5 power dissipation of only: 0 P= [(V IN (max ) ) ] − IOUT • (R SENSE ) • IOUT • Duty (6) 0 0.2 0. the difference between the IMAX and ITRIP values as the current available to charge the output capacitance. 3) • 5 = 9 . 5 provides a plot of fault time vs. P = (V IN − V SENSE − VOUT ) • IOUT (4) The fault time duration is set based upon the load capac- itance.3°C/W. preventing the output from turning on. 02)) • 7] • 0 . the power dissipated in I 36 • 10 −6 the MOSFET is given by: Fig. the short circuit power To determine the minimum fault time. This technique can easily be applied when using t FAULT (min) = the UCC3837. COUT • VOUT (3) CT (min) = Using DN-71. any heatsink with a thermal re- sistivity of 6. Without switchmode protection. 03 = 1.

At a load current of 3A. consider the effects of a 1. including temperature and Figure 6. Calculations of the dropout voltage of 0 20 40 60 80 a linear regulator based on the UCC3837 Controller AMBIENT TEMPERATURE [°C] should consider all of the following: • Sense resistor drop. • Path resistance drops on both the input and output Practical Considerations voltages.07" wide trace of 1oz. In order to achieve the expected performance. traces carrying high current should be made as short and wide as possible in order to minimize parasitic resistance and inductance effects. UCC1837 UCC2837 UCC3837 APPLICATION INFORMATION RESISTANCE SHORT CIRCUIT LIMIT To illustrate the importance of these concepts. Likewise. 16 The dropout voltage of a linear regulator is often a key 15 4 design parameter. Copper resistance and short circuit limit tolerance effects. • MOSFET resistance as a function of temperature and tention must be paid to circuit layout. careful at. board should be designed using a single point ground. NH 03054 TEL. (603) 424-2410 FAX (603) 424-3460 7 . resulting in a 91mV spike dur- 17 ing the 100ns it takes the load current to slew from 5 200mA to 3A. A SHORT CIRCUIT CURRENT COPPER RESISTANCE [mW] 20 0. for example resistor. copper results in an equivalent 8 resistance of 10. All • Ground path drops. • MERRIMACK.5" PCB trace located between the out- 21 9 put capacitor and the UCC3837 feedback reference.4mΩ. including transient performance. contributing almost 1% error to 7 18 the DC regulation. the inductance of the trace 6 is approximately 3. UNITRODE CORPORATION 7 CONTINENTAL BLVD.2mV is 19 dropped across the trace. referenced to the return of the output capacitor. The printed circuit gate drive. 31.24nH.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package. PACKAGE OPTION ADDENDUM www. Addendum-Page 1 . NRND: Not recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued. (4) There may be additional marking.ti. TBD: The Pb-Free/Green conversion plan has not been defined. and peak solder temperature. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. or 2) lead-based die adhesive used between the die and leadframe. Samples may or may not be available.ti. .The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible).com 30-Jan-2016 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) UCC2837D ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UCC2837 & no Sb/Br) UCC2837DG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UCC2837 & no Sb/Br) UCC2837DTR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UCC2837 & no Sb/Br) UCC3837D ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UCC3837 & no Sb/Br) UCC3837DG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UCC3837 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. Where designed to be soldered at high temperatures. OBSOLETE: TI has discontinued the production of the device. and a lifetime-buy period is in effect. including the requirement that lead not exceed 0. which relates to the logo. PREVIEW: Device has been announced but is not in production. or Green (RoHS & no Sb/Br) . Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances.The planned eco-friendly classification: Pb-Free (RoHS). or the environmental category on the device. the lot trace code information.please check http://www. Peak Temp.1% by weight in homogeneous material) (3) MSL. (5) Multiple Device Markings will be inside parentheses. Device is in production to support existing customers. and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.com/productcontent for the latest availability information and additional product content details. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.1% by weight in homogeneous materials. TI Pb-Free products are suitable for use in specified lead-free processes. (2) Eco Plan . Pb-Free (RoHS Exempt). but TI does not recommend using this part in a new design. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

com 30-Jan-2016 (6) Lead/Ball Finish . Efforts are underway to better integrate information from third parties. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.Orderable Devices may have multiple material finish options. TI and TI suppliers consider certain information to be proprietary. TI bases its knowledge and belief on information provided by third parties. Finish options are separated by a vertical ruled line. and makes no representation or warranty as to the accuracy of such information.ti. PACKAGE OPTION ADDENDUM www. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. Addendum-Page 2 . TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. and thus CAS numbers and other limited information may not be available for release.

0 Q1 Pack Materials-Page 1 .4 5.4 6.1 8.0 12.com 2-Sep-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1 (mm) UCC2837DTR SOIC D 8 2500 330.ti.2 2. PACKAGE MATERIALS INFORMATION www.0 12.

PACKAGE MATERIALS INFORMATION www.ti.0 367.0 Pack Materials-Page 2 .0 35.com 2-Sep-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCC2837DTR SOIC D 8 2500 367.

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