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Timing_sense : Timing Arc in .LIB Files (Part1)
STA & SI:: Chapter 1: Introduction
1.1a 1.1b 1.1c 1.2a 1.2b
INTRODUC Timing Unate: Unateness of Complex Circuit: LIB File syntax for Logic Gates: LIB File syntax for Complex Circuit:
TION Arc Timing Arc Timing Arc Timing Sense Timing Sense

Representation of The Unateness of timing Arc In timing Library:

In the Timing Library, "Timing Arc information" is stored with the syntax "timing_sense". Vlsi expert
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1) For Single Input and Single Output

Buffer : timing_sense: positive_unate Be the first of your friends to like th

/* --------------- *
* Design : BUF2X1 *
* --------------- */ Blog A
cell (buf){
► 20
....
pin (A) { ▼ 20
.... ▼
direction : input;
capacitance : 1.0;
} /* End pin (A) */ VLSI EXPERT (vlsi EG)
pin(Y){
Bridging Gap Between
direction : output; Acdamia and Industry
capacitance : 0.0;
function : "(A)"; Follow
....
333 followers ►
....
timing(A_Y) { ►
related_pin : "A"; ►
timing_sense : positive_unate; Total Pageviews

....
.... 5,787,874 ► 20
}
► 20
...
... ► 20
}/* End pin (Y) */ ► 20
}/* End cell (buf) */ ► 20
Subscribe To VLSI EXPERT ► 20

Posts ► 20

So basically "timing_sense" will represent the unateness of a particular pin. But remember, if you wants to know the number of Timing Arc - ► 20
then it's 2. One for Falling edge and other for Rising Edge.
EDN:
Inverter : timing_sense: negative_unate Popular Posts
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"Timing Paths" : Static ve
Timing Analysis (STA) two
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* Design : INVX1 * Design
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"Setup and Hold Time
pin(Y){ Violation" : Static
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direction : output;
basic (Part 3b)
capacitance : 0.0;
function : "(!A)"; Delay - "Wire Load
.... Model" : Static Timing
.... Analysis (STA) basic
(Part 4c)
timing(A_Y) {
related_pin : "A"; Delay - "Interconnect
timing_sense : negative_unate; Delay Models" : Static
.... Timing Analysis (STA)
basic (Part 4b)
....
} "Time Borrowing" :
... Static Timing Analysis
... (STA) basic (Part 2)
}/* End pin (Y) */
10 Ways to fix SETUP
}/* End cell (inv) */ and HOLD violation:
Static Timing Analysis
(STA) Basic (Part-8)

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Note: Interview

If you have noticed (or If you will compare in .lib file), through most of the parameters it's very difficult to understand whether it's Buffer
or Inverter. There are only 2 parameter which can help you: "function" and "timing_sense".
Recent Visitors
Name inside the timing() - is the Timing Arc name.
You can see (in above examples) there is 1 Input Pin - which is A and one Output Pin which is Y. Now timing() is "related to" output
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Pin Y because timing arc is attached to an output pin. (you can get more clarity on this point later in this article)
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AND gate: timing_sense: positive_unate Bangalore,
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To know more about the Unateness of AND gate, please read Article "Unateness- Timing Arc: AND gate" Timing
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How to Prepare Good
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* Design : AND2X1 * A visitor from
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cell (AND2X1) { viewed Create N-well
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direction : input; arrived from
rise_capacitance : 0.01; and viewed
fall_capacitance : 0.01; "Examples
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}
and viewed Synopsys
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pin(Y) {
(SDC) Basics...
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direction : output;
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capacitance : 0;
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rise_capacitance : 0;
Design Constraints
fall_capacitance : 0; A visitor from India
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timing(A_Y) { A visitor from
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.....
}
....
.... Followers
}
.....
.....
}

In this case both the Pins are of same type, we can combine the definition of timing arc into one. Like
Followers (480) Next

timing(A_Y, B_Y) {
related_pin : "A B";
timing_sense : positive_unate;
....
....
}

Follow

Remember, all the parameters should be same. There are few parameters which we haven't discuss till now, but in reality before combining we
have to review all.

OR gate: timing_sense: positive_unate

To know more about the Unateness of OR Gate, please read Article "Unateness- Timing Arc: OR Gate"

/* -------------- *
* Design : OR2X1 *
* -------------- */
cell (OR2X1) {
....
....
pin(A) {
direction : input;
capacitance : 0.015;
rise_capacitance : 0.015;
fall_capacitance : 0.015;
}
pin(B) {
direction : input;
capacitance : 0.01;
rise_capacitance : 0.01;
fall_capacitance : 0.01;
}
pin(Y) {
direction : output;
capacitance : 0;
rise_capacitance : 0;
fall_capacitance : 0;
max_capacitance : 0.4;
function : "(A+B)";
timing(A_Y) {
related_pin : "A";
timing_sense : positive_unate;
....
....
}
timing(B_Y) {
related_pin : "B";
timing_sense : positive_unate;
....
....
}
....
....
}
}

NOR gate: timing_sense: negative_unate

To know more about the Unateness of NOR gate, please read Article "Unateness- Timing Arc: NOR gate"

/* -------------- *
* Design : NOR2X1 *
* -------------- */
cell (NOR2X1) {
....
....
pin(A) {
direction : input;
capacitance : 0.015;
rise_capacitance : 0.015;
fall_capacitance : 0.015;
}
pin(B) {
direction : input;
capacitance : 0.01;
rise_capacitance : 0.01;
fall_capacitance : 0.01;
}
pin(Y) {
direction : output;
capacitance : 0;
rise_capacitance : 0;
fall_capacitance : 0;
max_capacitance : 0.4;
function : "(!(A+B))";
timing(A_Y) {
related_pin : "A";
timing_sense : negative_unate;
....
....
}
timing(B_Y) {
related_pin : "B";
timing_sense : negative_unate;
....
....
}
....
....
}
}

NAND gate: timing_sense: negative_unate

To know more about the Unateness of NAND gate, please read Article "Unateness- Timing Arc: NAND gate"

/* --------------- *
* Design : NAND2X1 *
* --------------- */
cell (NAND2X1) {
....
....
pin(A) {
direction : input;
capacitance : 0.01;
rise_capacitance : 0.01;
fall_capacitance : 0.01;
}

pin(B) {
direction : input;
capacitance : 0.01;
rise_capacitance : 0.01;
fall_capacitance : 0.01;
}

pin(Y) {
direction : output;
capacitance : 0;
rise_capacitance : 0;
fall_capacitance : 0;
max_capacitance : 0.5;
function : "(!(A B))";
timing(A_Y) {
related_pin : "A";
timing_sense : negative_unate;
.....
.....
}
timing(B_Y) {
related_pin : "B";
timing_sense : negative_unate;
.....
.....
}
....
....
}
.....
.....
}

XNOR gate: timing_sense: non_unate

To know more about the Unateness of XNOR gate, please read Article "Unateness- Timing Arc: XNOR gate"

/* -------------- *
* Design : XNOR2X1 *
* -------------- */
cell (XNOR2X1) {
....
pin(A) {
direction : input;
....;
}
pin(B) {
direction : input;
....;
}
pin(Y) {
direction : output;
....;
function : "(!(A^B))";
timing(A_Y) {
related_pin : "A";
timing_sense : non_unate;
....
....
}
timing(B_Y) {
related_pin : "B";
timing_sense : non_unate;
....
....
}
....
}
}

XOR gate: timing_sense: non_unate

To know more about the Unateness of XOR gate, please read Article "Unateness- Timing Arc: XOR gate"

/* -------------- *
* Design : XOR2X1 *
* -------------- */
cell (XOR2X1) {
....
....
pin(A) {
direction : input;
....;
}
pin(B) {
direction : input;
....;
}
pin(Y) {
direction : output;
....;
function : "(A^B)";
timing(A_Y) {
related_pin : "A";
timing_sense : non_unate;
....
....
}
timing(B_Y) {
related_pin : "B";
timing_sense : non_unate;
....
....
}
....
}
}

Representation of Unateness for few more complex circuits (like MUX) and Sequential circuits, we will discuss in next Articles.

Posted by VLSI EXPERT at 1:19 AM

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