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# Chapter 8:

FET Amplifiers
Introduction

FETs provide:

## • Excellent voltage gain

• Hi h input
High i impedance
i d
• Low-power consumption
• Good frequency range

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FET Small-
Small-Signal
g Model

Transconductance

The relationship
Th l ti hi off a change
h in
i ID to
t th
the corresponding
di change
h iin
VGS is called transconductance

## Transconductance is denoted gm and given by:

ΔI D
gm =
ΔV GS

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Graphical
p Determination of gm

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Mathematical Definitions of gm
ΔI D
gm =
ΔVGS

2I DSS ⎡ VGS ⎤
gm = ⎢1 − ⎥
VP ⎣ VP ⎦

2I DSS
Where VGS =0V g m0 =
VP
⎡ V ⎤
g m = g m0 ⎢1 − GS ⎥
⎣ VP ⎦

Where 1 − VGS = ID
VP I DSS

⎛ V ⎞ ID
g m = g m0 ⎜⎜ 1 − GS ⎟⎟ = g m0
⎝ VP ⎠ I DSS

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FET Impedance
p
Input impedance:
Z i = ∞Ω

Output Impedance:
1
Z o = rd =
y os

where:
ΔVDS
rd = VGS = constant
ΔI D
yos= admittance parameter listed on FET specification sheets.

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FET AC Equivalent Circuit

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Common--Source ((CS)) Fixed-
Common Fixed-Bias Circuit

## The input is on the gate and the

output is on the drain

## There is a 180° phase shift

between input and output

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Calculations
Input impedance:

Zi = RG

Output
p impedance:
p

Z o = R D || rd

Zo ≅ R D
rd ≥ 10R D

Voltage gain:
Vo
Av = = − g m (rd || R D )
Vi
Vo
Av = = −g m R D
Vi rd ≥ 10R D

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Common--Source ((CS)) Self-
Common Self-Bias Circuit
This is a common-source amplifier
configuration, so the input is on the gate
and the output is on the drain

## There is a 180° phase shift between

input and output

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Calculations
Input impedance:
Zi = RG

Output
p impedance:
p

Z o = rd || R D

Zo ≅ R D
rd ≥ 10R D

Voltage gain:

A v = − g m (rd || R D )

A v = −g m R D
rd ≥ 10R D

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Common--Source (CS) Self
Common Self--Bias Circuit
Removing Cs affects
the ggain of the circuit.

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Calculations
Input impedance:
Zi = RG

Output impedance:

Zo ≅ R D
rd ≥ 10R D

Voltage gain:
Vo gm R D
Av = =−
Vi R + RS
1 + gm RS + D
rd
Vo gm R D
Av = =− r ≥ 10(R D + R S )
Vi 1 + gmRS d

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Common--Source (CS) Voltage
Common Voltage--Divider Bias

This is a common-source
amplifier configuration, so the
input
p is on the ggate and the
output is on the drain.

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Impedances
Input impedance:

Z i = R 1 || R 2

Output impedance:

Z o = rd || R D

Zo ≅ R D
rd ≥ 10R D

Voltage gain:
A v = − g m (rd || R D )

A v = −g m R D
rd ≥ 10R D

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Source Follower (Common-
(Common-Drain) Circuit
In a common
common-drain
drain amplifier
configuration, the input is on the
gate, but the output is from the
source.
source

## There is no phase shift between

i
input
t andd output.
t t

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Impedances
Input impedance:
Zi = RG

Output impedance:
1
Z o = rd || R S ||
gm
1
Z o ≅ R S || r ≥ 10R S
gm d

Voltage gain:
Vo g m (rd || R S )
Av = =
Vi 1 + g m (rd || R S )
Vo gmRS
Av = = r ≥ 10
Vi 1 + g m R S d

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Common--Gate ((CG)) Circuit
Common

## The input is on the source

and the output is on the
drain.

## There is no phase shift

between input and output.

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Calculations
Input impedance:

⎡ r + RD ⎤
Z i = R S || ⎢ d ⎥
⎣ 1 + g m rd ⎦
1
Z i ≅ R S || r ≥ 10R D
gm d

Output impedance:

Z o = R D || rd
Voltage gain:
Z o ≅ R D rd ≥ 10
⎡ RD ⎤
⎢ m D
g R + ⎥
Vo ⎣ rd ⎦ A v = g m R D rd ≥ 10R D
Av = =
Vi ⎡ RD ⎤
⎢1 + ⎥
⎣ rd ⎦

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D-Type
yp MOSFET AC Equivalent
q

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E-Type MOSFET AC Equivalent

## gm and rd can be found in

the specification sheet for
the FET.

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Common--Source Drain
Common Drain--Feedback

## There is a 180° phase shift

between input and output.

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Calculations
Input impedance:
R F + rd || R D
Zi =
1 + g m (rd || R D )
RF
Zi ≅ R >> rd || R D , rd ≥ 10R D
1 + gmR D F

Output
p impedance
p :
Z o = R F || rd ||R D

Z o ≅ R D R F >> rd || R D , rd ≥ 10R D

Voltage gain:

A v = − g m (R F || rd || R D )
A v ≅ − g m R D R F >> rd ||R D ,rd ≥10R D

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Common--Source Voltage-
Common Voltage-Divider Bias

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Calculations
Input impedance:
Z i = R 1 || R 2

O t t impedance:
Output i d
Z o = rd || R D
Z o ≅ R D rd ≥ 10

Voltage gain:
A v = − g m (rd || R D )
A v ≅ − g m R D rd ≥ 10R D

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Summary
y Table

more…
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Summary
y Table

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Troubleshooting
Check the DC bias voltages:

If not correct check power supply, resistors, FET. Also check to ensure
that the coupling capacitor between amplifier stages is OK.
.
Check the AC voltages:

## If not correct check FET,

FET capacitors and the loading effect of the next
stage

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