You are on page 1of 4

Operational amplifiers
As the name implies, if we finally put together all the elementary blocks above (transistors, current
mirrors, current sources, differential stages and buffers) we finally come to something usable, the
operational amplifier (op amp).

Figure 9 shows a basic op amp essentially composed of three stages, the input differential-to-single stage,
the gain stage, and the output buffer stage. The input stage shown here is inverted to the one in figure 7,
namely with respect to the PNP differential pair and NPN mirror (also called active load). The
intermediate stage is shown as a simple NPN transistor, and more often will be a full-fledged Darlington
stage (two cascaded NPN transistors gaining beta squared or β2). The output stage is the buffer discussed
in the previous section.

Inverting and non-inverting inputs

The op amp here is shown as an open loop. Before closing the loop ï¾ namely connecting the inverting
input to the output for negative feedback ï¾ it is a good idea to find out the inverting versus the
non-inverting input.

Figure 9. Bipolar op amp schematic.

Click to Enlarge

The arrows in figure 9 help in determining the input sign; note that an arrow on top of a wire indicates a
small signal current flow in that wire while a floating arrow near a node indicates a small voltage signal

1 of 4 7-9-2010 20:00

acting on that node. Applying a positive voltage to the Vin" input (and correspondingly a negative one to
the Vin+) we cause more current flow in the base of T5. Collectively it will draw more current, pulling
down the buffer and thus the output. Since the output moves low when Vin" moves high, Vin" is indeed
the inverting output as its name seemed to imply at the start.

Rail to rail output operation

In figure 9 the output cannot get any closer to V+ than the sum of the Vbe of T6 and the Vcesat of the
current source (Vcesat of T2 in the current mirror of Figure 4 is driven by a current sink Iin and thus is
indeed a current source). Similarly, the output cannot get any closer to ground than the sum of the Vbe of
T7 and the Vcesat of T5. In order to have low dropout operation (also referred to as rail to rail output
operation) the shorter path between output and V+ or ground must be a Vcesat.

Figure 10. Low dropout op amp.

Click to Enlarge

In figure 10 the principle of output rail-to-rail operation is illustrated.

Current mirroring plays a heavy role here: mirrors T5:T7, T8:T9 and T6:T10 with ratios of 1:6, 1:8 and 1:8
respectively, provide a balanced current bias for the circuit.

CMOS Op amps

As explained earlier, the bipolar op amp in figure 10 cam be easily replicated in CMOS by substituting
NPN with N-Channel MOS transistors and PNPs with P-Channel MOS transistors. In figure 11 transistors
T1, T2 and T7 are P-Channel and T4 through T6 are P-Channel, resulting in a simple CMOS version of an
op amp.

Figure 11. CMOS op amp schematic.

Click to Enlarge

2 of 4 7-9-2010 20:00

Op amp symbol and configurations

Figure 12. Op amp symbol and configurations: (a) inverting, (b) non-inverting and (c) unity gain


Click to Enlarge

In figure12 we have the op amp in some common configurations. Notice how in closed loop configuration
the feedback network (R1 and R2) sets the forward gain. The same feedback network returns to the input
an amount of output signal that is inversely proportional to the gain. The max amount of feedback signal is
returned in the case of the unity gain buffer configuration, where all the output signal is returned to the
input. From a loop stability standpoint then, the unity gain buffer configuration appears to be the most

DC open loop gain

The DC gain of the bipolar op amp in figure 9 is calculated as follows. If a small signal dVin is applied to
the input differential (Vin+ " Vin"), the output of this first stage will produce a current equal to dVin/rE.
This current drives the base of T5, which develops a collector current β5 times higher. This current is
further amplified by T6 (or T7 depending on the polarity of the incoming current) by another factor of β6.
Finally this current is delivered to the load RL. Mathematically: dVin*(1/rE)* β5 *6 *RL =dVout [12] from
which, assuming for simplicity the two β are identical the open loop DC gain is: GDCOL = dVout/dVin =
β2*RL/ rE [13] For example, if rE and RL are both 2.6kΩ, (rE is 2.6kΩ at Ie= 10uA) and the β are both
100, the open loop gain is 10,000. This means that to move 1V at the output only 1V/10,000


one tenth of a thousandth of a Volt (100 μV where μV stands for micro Volt or a millionth of a Volt or
10-6V), of signal swing is needed at the input. Commercial products exhibit even higher gains. With
differential input variations (Vin+ " Vin") in the order of μV, no wonder an op amp may have Volts
swinging at its output with no appreciable voltage visible at its direct differential inputs. Accordingly,
when a non-inverting input is connected to ground — as happens in many configurations — the inverting
pin will appear to be grounded as well. The term "virtual ground" refers to such input.

AC open loop gain

To be useful, the op amp will be ultimately connected in a closed loop configuration. A closed electrical
loop is subject to oscillations or frequency instabilities due to parasitic reactive components (capacitors
and inductors) present in each component in the loop and causing phase shifts. Oscillation occurs in any
regenerative closed loop system, especially those in which a signal injected in any point returns with equal
or higher amplitude after a circulation (loop gain =>1) and roughly equal phase (low phase margin). Such
oscillations are eliminated if the open loop gain is made to be un-regenerative, namely assumes a value

3 of 4 7-9-2010 20:00

smaller than unity, at the critical frequency where the parasitic components become active. Intuitively if
an electric signal is cyclically multiplied (in a closed loop circuit) by a factor higher than one (amplified)
its amplitude will continually increases (regenerative loop) leading to self-sustained oscillations.
Vice-versa, the same signal cyclically multiplied by a factor lower than one (attenuated) will eventually be
reduced down to zero (no oscillations).

In traditional bipolar design the most notorious source of phase shift is the PNP with its low fT frequency
around 1MHz. Hence the AC open loop gain needs to be less than unity at that frequency. In that case the
system will be stable with 45-degree of phase margin or better (stability criterion). In calculating the AC
loop gain we will assume to be " namely all the calculations are conducted at - around the cutoff
frequency of 1MHz as this is the zone of interest for stability. This assumption allows the use of a
simplified expression for the elements of the loop gain. At the basis of such circuit analysis simplification
is the property that capacitors behave like short circuits (a piece of wire) and inductors behave like open
circuits (a wire cut open) at sufficiently high frequencies. The same technique is used for calculating the
DC gain, the difference being that at the high frequency chosen for this analysis, the current out of the
input stage will bypass the transistor T5 in figure 9.

Instead, the current will go through the capacitor C, developing at its output a voltage in proportion of its
impedance of amplitude 1/C. The capacitor then presents this voltage to the output buffer which will pass
it unchanged to the output:

dVin*(1/rE)* 1/ωC =dVout [14]

GACOL = dVin/dVout= 1/ ω C rE = 1/2π f CrE [15]

Such gain has to be less than or equal to one at f=fT hence by setting GACOL = 1 we have:

1=1/2π fT C rE [16]

from which we can calculate the compensation capacitor:

C= 1=1/2π fT rE =1/(2*3.14*1MHz*2.6kΩ) = 61pF [17]

This value is in the right ballpark but integrating 60pF capacitor may take quite a lot of die space. Since fT
is a given parameter, depending on the process at hand,


ends up being the only parameter to play with. For example if Ie is reduced from 10 to 5μA, rE will double
and C can then be reduced to 30pF.

Part 1: Elementary devices and circuits.

Part 3: Next Week

4 of 4 7-9-2010 20:00