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Development Environment Using FPGA for

Domotics Applications Based on X10

Chapter · August 2008

DOI: 10.1007/978-1-4020-8737-0_27


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Development Environment Using FPGA for Domotics
Applications Based on X10 Technology
Manuel D. Cruz1, Juan A. Ortega1, Ángel Barriga2 and Alejandro Fernández-Montes1

Department of Languages and Computer Systems, University of Seville, Spain.
IMSE CNM-CSIC / University of Seville, Spain.

Abstract—This communication proposes a basic software integrated in a domotics system it is possible to obtain an
and hardware architecture of a controller for the X10 important power saving and an increase of the comfort. The
technology interface CM11A, oriented to the world of home next section describes briefly the X10 protocol. Later the
automation. The implementation of the system is based in the FPGA platform is presented. Finally, the last section
use of programmable devices such as FPGA (Field describes the design of the system.
Programmable Gate Array). With this controller an end user
will be able to control and to manage a set of devices
distributed in a domotics space.
The X10 communication protocol allows controlling
I. INTRODUCTION remote devices using the electrical network and the specific
In order to find home automation low-cost and little- modules to which they are connected. The control signals
invasive technological solutions, and easy handling for the are based on the transmission of RF pulses (120 KHz). The
end user, the use of FPGA embedded systems will be an transmissions are synchronized with the crossing by zero of
implementation option to have into account [1]. Home the alternating current (AC). The binary one is represented
automation or domotics are automation technologies applied by a pulse of 120 KHz. during 1 millisecond whereas binary
to buildings. This automation technologies use control zero is represented by the lack of this 120 KHz pulse.
devices, sensors and actuators. These devices communicate The protocol [9] consists of address bits and commands.
between them by different communication schemes such as In an X10 network can coexist up to 256 different
specific buses, wireless communication, or electrical interconnected modules. The way of identifying them is by a
network. From end of the nineties there appeared different code (housecode) composed by a letter (from A to P) and by
standards of communication like CEBus, LonWorks, KNX a number (from 1 to 16, the device code). These modules
[2, 3]. can recognize (depending on its characteristics.) up to 16
The use of the electrical network facilitates the different operation codes.
installation of these technologies in the buildings since it is An X10 transmission from the controller, implemented in
not needed of any additional communication infrastructure. a development board (DB), to the X10 interface consists of
In this sense, devices and communications protocols adapted the communication of a housecode and device code
to this media have been developed [4, 5]. One of the most combination followed by the command code. The sequence
widespread is the X10 protocol [5, 6]. This one was of the transmission can be seen in the figure 1. We can
developed in 1978 by engineers of the company Pico observe what each one of the frames of bytes means. This
Electronics Ltd. in Glenrothes, Scotland. Since then the format of transmission is always the same regardless of
technologies based on the utilization of the electrical command or address.
network known by Power Line Carrier (PLC) have been
spreading, appearing a great variety of commercial products
and standards [7].
In the area of home automation architectures focused on
the education, the systems based on FPGA open a broad
field of possibilities [8]. The present communication focuses
the process of implementation of a controller capable of
communicating with all the devices connected to an X10
network distributed in a domotics space. In particular the
developed system focuses in an application to the
illumination control. With the control of the illumination

T. Sobh et al. (eds.), Novel Algorithms and Techniques in Telecommunications, Automation and Industrial Electronics, 150–153.
© Springer Science+Business Media B.V. 2008

JTAG port
Standard transm ission

Spartan 3 X10Interface:CM11A

1: Header:Code FPGA

2: return checksum

3: Acknowledge port 7-segments

4: return interface ready to receive

Push buttons

Fig. 2. Xilinx’s Spartan-3 development board

Fig. 1. X10 standard transmission

1. The DB transmit the header:code/command to The FPGA development environment is the Xilinx
the X10 interface. Platform Studio (XPS), of which we have used the tools that
2. The X10 interface receives the frame and makes allow covering the design flow of embedded systems. This
a checksum. It transmits it back, to the DB. flow consists of the hardware architecture description stage,
3. The DB checks the checksum and sends an the synthesis and implementation of the control circuit, the
acknowledgement (ACK) frame. development of the software applications, the compilation of
4. The interface receives the ACK and informs that the above mentioned applications and the programming of
it is ready for more transmissions. the FPGA and the SRAM memory.
We can observe a code example in the System Design The FPGA board controls any X10 receiver module in the
section, subsection B. home by means of the computer interface module CM11A
There are an extensive range of products based on X10 (figure 3a). The CM11A plugs into an outlet and connects to
protocol which can be classified in the following categories: the RS232 serial port on the FPGA board
controllers, modules and complements. The system describe The lamp module, shown in figure 3b, is used to control a
in this paper is composed by a CM11A model PC lamp through X10 protocol. It is controlled by the remote
programmer (belonging to the category of the controllers.) CM11A module. It connects the existing lamp in the socket
and a lamp module (that receives commands from the of this module, which is connected in the socket of the wall.
electrical network and acts on a lamp.). It is the interface module between the lamp and the socket of
the wall without requiring any additional connection and any
III. HARDWARE DEVELOPMENT PLATFORM modification in the existing electrical circuit. It offers the
possibility of switch on/off the lamp and varying its
The control system has been implemented on an FPGA
luminosity remotely by means of an X10 controller.
development board containing a Xilinx Spartan-3 [10]. The
system operates with a clock frequency of 50 MHz
determined by an oscillator included on the board. The
board incorporates a set of elements that facilitate the system IV. SYSTEM DESIGN
development and allows diverse applications. It has two
A. Hardware architecture
SRAM memory modules up to 256 KB that store the
application. The RS232 port allows the communication with Figure 4 illustrate the configuration scheme of the system.
the X10 interface. In this scheme the controller has been implemented on the
The address (housecode) and the command FPGA development board described in the previous section.
(operationcode) are formed activating four push-buttons. This board communicates with the X10 interface module by
The 7-segments displays allow verifying the operation and means of the RS232 port. This one transmits the address and
inform, as well, about the state of the controller or the X10 commands through the electrical network. The X10 lamp
devices. Finally, the JTAG communication port has been module that has been address receives the commands and
used for download and test the application in the FPGA In acts on the device that it has connected.
figure 2 the components that have been used are shown.


BRAM Local Memory Bus MicroBlaze

On-chip Peripheral Bus


Fig. 3. a) CM11A X10 computer interface module, b) lamp module

2. Transmit to interface Fig. 5. Controller architecture

(ON/OFF commands)

The processor communicates with the peripheral devices

by an OPB (On-chip Peripheral Bus) IBM's standard bus.
The peripheral ones are mapped in the memory address
space. This means that the inclusion of new peripheral
3. Transmit to
lamp module consists simply of connecting it to the OPB bus and
1. Set push buttons including it within the memory address space of the
4. Switch ON/OFF lamp processor. In our application only the three devices shown in
device plugged on module figure 5 have been required. The peripheral devices
correspond to a parallel port (gpio), a serial port (uart) and a
memory controller (emc). The parallel port receives
Fig. 4. Communications scheme information of the push-buttons of the board and generates
the signals to the 7-segment displays. The serial port allows
The design of the controller has been realized applying a realizing the transmission of information towards the X10
hardware&software codesign methodology that has allowed module. The external memory controller facilitates the
defining an open and flexible architecture. The architecture transfer of information with the SRAM memory that
is open in the sense that allows incorporating new elements contains the application software.
and it is flexible because it allows to be reconfigured. In figure 5 it is possible to observe that the system has
The system is constituted by two types of elements: the two RAM memory blocks: BRAM and SRAM. BRAM is
hardware components that constitute the circuit programmed the FPGA internal RAM memory whereas the SRAM is the
in the FPGA, and the application software that runs on the FPGA external memory module. The employment of both
hardware and is stored in the system memory. The partition memories justifies itself due to the fact of the size of the
of the functionality of the system into the hardware and software application requirements. BRAM module has better
software components has been realized having in account access time (one clock cycle), nevertheless its size is limited.
the already mentioned of open and flexible architecture. For Block SRAM can be expanded based on the system
it the circuit has been developed with IP (Intellectual requirements. There are three expansion connectors in the
Property) modules. These IP modules allow the reuse and development board to adapt any additional device such as a
easy the insertion of new functionality. memory module.
The architecture, which shows in figure 5, is based on the
utilization of the MicroBlaze processor from Xilinx. The B. Software application development
MicroBlaze processor is a soft-core 32 bits RISC The software application has been implemented using
architecture that can be include in Xilinx's FPGA as an IP C++ language. The XPS development environment provides
module. MicroBlaze has Harvard architecture; this means a series of software packages developed in ANSI C that
separated data and addresses buses. It has several structures facilitate the codification of the user's applications
of buses of which we have used the LMB (Local Memory (peripheral drivers, libraries and operating systems) [11].
Bus) and the OPB (Peripheral On-chip Bus). Bus LMB Figure 6 shows the model-view-controller (MVC) of the
allows accessing the internal FPGA memory in only a clock software application describing the classes’ graph. The
cycle. The disadvantage is in that the size of this memory pattern has been used in order to separate data and user
(BRAM) is limited to the available resources in the FPGA interface. In that way it is possible to improve and expand
device. the application in an easy manner. This model divides the
application in three layers:

• View: it is the layer that transmits and receives to incorporate new external devices in order to increase the
information of the end user. In order to include new functionality and improving the user interface (numeric
services it is necessary to add more classes that keypads, LCD screens, tactile screens, etc). The system
implement the interconnection between the final user presented in this communication constitutes a development
and the devices. Two classes belong to this layer: platform focused on economic solutions and easy managing
DisplayDriverClass: it is the class that shows the in the world of the home automation
results and information of interest in the 7-segment
display. …
//next transmission, it send the address A1
ButtonsDriverClass: it is the class that receives the
outputBuffer = _HEADER_;//header
push-buttons signals and transmits the information to while (!XUartLite_Send (&uart, &outputBuffer, 1));
the controller.
«uses» «uses» outputBuffer = _DEVICE_ADDRESS;//device address
while (!XUartLite_Send (&uart, &outputBuffer, 1));
«uses» while (!XUartLite_Recv (&uart, &inputBuffer, 1));
//check the checksum
if (inputBuffer == ((_HEADER_ + _DEVICE_ADDRESS)&0xff))
View //checksum ok
Model //transmit ACK to the board
DisplayDriverClass outputBuffer = _OK_;
while (!XUartLite_Send (&uart, &outputBuffer, 1));

ButtonsDriverClass while (!XUartLite_Recv (&uart, &inputBuffer, 1));

for (j=0; j<20000000; j++);//wait for synchronize
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if (inputBuffer == 0x55)
ExternalLibraries {
//interface ready for the next transmission
Fig. 6. Model-view-controller. …

• Controller: in this layer the information is processed Fig. 7. Code example of the X10 transmission
and transmitted up to the other two layers. For
example, it receives the information of the pressed
button and transmits the orders to the model layer, ACKNOWLEDGEMENT
which will transmit the command to the target device This work was supported in part by the Spanish
through the serial port. Education and Research Council under grants no. TEC2005-
X10Client: this class works as an adapter, reducing 04359/MIC and no. TSI2006-13390-C02-02, and by the
responsibility to the classes of the other two layers and Andalusia Regional Government under grants no. TIC2006-
improving the model of the system. This way a major 635 and no. TIC2141.
independence is obtained between all the classes
facilitating later modifications. REFERENCES
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