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A B C D E

COMPAL CONFIDENTIAL
MODEL NAME : QAL70
1 1

PCB NO : LA-7741P(DAB00000800)
BOM P/N : 4619EO31L01 TPM ;4519EO31L02 TPM/TAA
GPIO MAP: Rev0.9

2
Dalmore 13 UMA 2

@ Ivy Bridge + Panther POINT

2011-06-23
REV : 0.1 (X00)
@ : Nopop Component
CONN@ : Connector Component
3 3

MB Type BOM P/N

TPM EN/ TCM DIS 1@ 3@

TPM DIS/ TCM EN 2@ 4@

TPM DIS/ TCM DIS 2@ 3@

TAA @TAA

SPI ON BOARD @SPI

4 4

MB PCB DELL CONFIDENTIAL/PROPRIETARY


Part Number Description

DA80000I700 PCB 0FH LA-6562P REV0 M/B UMA Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Cover Sheet
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-7741
Date: Thursday, June 23, 2011 Sheet 1 of 56

A B C D E
A B C D E

Block Diagram
Memory BUS (DDR3) DDRIII-DIMM X2
1333/1600 MHz BANK 0, 1, 2, 3, 4 ,5 ,6 ,7

1 1
Ivy Bridge
On IO board
BGA 2C 1023P
CRT CONN VGA For MB/DOCK
Video Switch BT 4.0
VGA PI3V713-AZLEX
FDI DMI2 Camera Trough Cable
Lane x 8 Lane x 4
VGA
HDMI CONN DPB SATA Repeater
INTEL USB SATA
PS8511B E-SATA
DPC
DPD Panther POINT-M USB 2.0 Port
DOCKING PORT
USB3.0
BGA 989P USB3.0/2.0
DAI
LVDS CONN LVDS
2 2
USB3.0
USB2.0 [3,8] USB3.0
PS8710B USB3.0
SATA5
Repeater USB3.0/2.0+PS
DOCK LAN PI5USB1457A USB
USB3.0 [4] SDXC/MMC Card Reader PCIE x1 Power Share
Intel Lewisville
OZ600FJ0LN PCI Express BUS 100MHz 82579LM
HD Audio I/F
PCI Express BUS 100MHz
Option
SPI S-ATA 0/1 6GB/s, S-ATA 2/3/4/5 3GB/s
PCIE3 PCIE5 PCIE2 PCIE1
DOCK LAN
LAN SWITCH
EXPRESS 1/2 Mini Card 1/2 Mini Card Full Mini Card China TCM1.2 LPC BUS SATA PI3L720
33MHz INT.Speaker
Card PP WLAN/WiFi WWAN SSX44B HDA Codec
W25Q64BVSSIG SATA Repeater 92HD90B3
USB10 USB6 USB4 USB5 64M 4K sector Parade PS8520B
3
Combo Jack RJ45 3

USH W25Q32BVSSIG
Smart Card TDA8034HN HDD
BCM5882 16M 4K sector on IO board
CPU XDP Port
DAI
To Docking side
RFID Fingerprint FFS LNG3DM
PCH XDP Port FP_USB USB7
CONN Dig.
USH Module
MIC
WiFi ON/OFF PCIE4 E-Module Trough LVDS Cable
SMSC SIO
DC/DC Interface BC BUS
ECE5048
LED SMSC KBC
BC BUS
4
PWM FAN MEC5055 Discrete TPM
4

SMSC
AT97SC3204
4021 DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
UMA Block Diagram
TP CONN KB CONN Size Document Number Rev
0.1
LA-7741
Date: Thursday, June 23, 2011 Sheet 2 of 56
A B C D E
5 4 3 2 1

POWER STATES
USB PORT# DESTINATION
Signal SLP SLP SLP SLP ALWAYS M SUS RUN CLOCKS
State S3# S4# S5# A# PLANE PLANE PLANE PLANE
0 JUSB1 (Right side )
S0 (Full ON) / M0 HIGH HIGH HIGH HIGH ON ON ON ON ON
1 JUSB2 (Rear Left side)
D D
S3 (Suspend to RAM) / M3 LOW HIGH HIGH HIGH ON ON ON OFF OFF
2 NA
S4 (Suspend to DISK) / M3 LOW LOW HIGH HIGH ON ON OFF OFF OFF
3 MLK DOCK
S5 (SOFT OFF) / M3 LOW LOW LOW HIGH ON ON OFF OFF OFF
4 WLAN
S3 (Suspend to RAM) / M-OFF LOW HIGH HIGH LOW ON OFF ON OFF OFF
5 WWAN
S4 (Suspend to DISK) / M-OFF LOW LOW HIGH LOW ON OFF OFF OFF OFF
PCH
6 JMINI3(PP)
S5 (SOFT OFF) / M-OFF LOW LOW LOW LOW ON OFF OFF OFF OFF
7 USH->BIO

8 DOCKING
PM TABLE
9 JESATA1 ( right side)
+15V_ALW +3.3V_SUS +5V_RUN +3.3V_M +3.3V_M
C
SATA DESTINATION C
+5V_ALW +1.5V_MEM +3.3V_RUN +1.05V_M +1.05V_M
10 Express card
+3.3V_ALW_PCH +1.8V_RUN (M-OFF)
power SATA 0 HDD
+3.3V_RTC_LDO +1.5V_RUN
plane 11 Bluetooth
+0.75V_DDR_VTT
SATA 1 ODD/ E3 Module Bay
+VCC_CORE
12 Camera
+1.05V_RUN_VTT
SATA 2 NA
+1.05V_RUN
State 13 NA
SATA 3 NA

S0 ON ON ON ON ON SATA 4 ESATA 0 BIO


USH
S3 ON ON OFF ON OFF SATA 5 Dock 1 NA

S5 S4/AC ON OFF OFF ON OFF

B
S5 S4/AC don't exist OFF OFF OFF OFF OFF PCI EXPRESS DESTINATION B

need to update Power Status and PM Lane 1 MINI CARD-1 WWAN


Table
Lane 2 MINI CARD-2 WLAN

Lane 3 Express card

Lane 4 E3 Module Bay (USB3)

UMA DP/HDMI Port Connetion Lane 5 1/2vMINI CARD-3 PCIE

Port B MB HDMI Conn Lane 6 MMI

Port C Dock DP port 2 Lane 7 10/100/1G LOM

A
Port D Dock DP port 1 Lane 8 None A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Index and Config.
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-7741
Date: Thursday, June 23, 2011 Sheet 3 of 56
5 4 3 2 1
5 4 3 2 1

MODC_EN
HDDC_EN
EN_INVPWR FDC654P
+BL_PWR_SRC
Q21
D D

ADAPTER
SI3456BDV SI3456BDV
(Q27) (Q30)

+PWR_SRC 1.05V_VTTPWRGD
BATTERY TPS51461RGER +VCC_SA +5V_HDD +5V_MOD
(PU13)

ALWON

+15V_ALW
C RT8205LZQW C
CHARGER +5V_ALW RUN_ON
(PU2)

TPS22966DPUR
+3.3V_ALW (U78)

AUX_EN_WOWL

PCH_ALW_ON
+5V_RUN

AUX_ON
SUS_ON

RUN_ON

M_ON
TPS51212DSCR
SN1003055
MAX17511 RT8207MZQW RT8207MZQW SY8033BDBC
TPS22966DPUR
(PU9) (PU16) (PU16) (PU15) (PU7) (PU17) SI3456 SI3456 S13456 SI3456 SI3456
(U78)
B (Q38) (Q49) (Q54) (Q34) (Q58) B
0.75V_DDR_VTT_ON
1.05V_0.8V_PWROK

CPU_VTT_ON

SIO_SLP_A#
DDR_ON

RUN_ON

+3.3V_WLAN +3.3V_ALW_PCH +3.3V_SUS +3.3V_LAN +3.3V_RUN +3.3V_M

+VCC_CORE +1.5V_MEM +0.75V_DDR_VTT +1.8V_RUN +1.05V_RUN_VTT +1.05V_M

Pop option
RUN_ON

CPU1.5V_S3_GATE RUN_ON
Pop option

+1.0V_LAN +3.3V_M

AO4728 NTGS4141N SI4164


A (QC3) (Q59) (Q63) A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
+1.05V_RUN BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Power Rail
+1.5V_CPU_VDDQ +1.5V_RUN NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.1
LA-7741
Date: Thursday, June 23, 2011 Sheet 4 of 56
5 4 3 2 1
5 4 3 2 1

@ 2.2K
SMBUS Address [0x9a]

@ 2.2K
+3.3V_ALW_PCH
H14 MEM_SMBCLK 202
2N7002
C9 MEM_SMBDATA 200 DIMMA SMBUS Address [A0]
2N7002
2.2K
202
PCH
D
2.2K
+3.3V_LAN 200 DIMMB
SMBUS Address [A4] D

C8 LAN_SMBCLK 28

G12 LAN_SMBDATA 31 LOM SMBUS Address [C8]


M16 E14 53
XDP1 SMBUS Address [TBD]
2.2K 51
SML1_SMBDATA

SML1_SMBCLK
+3.3V_ALW_PCH
2.2K 53
51 XDP2
A5 B6 2.2K SMBUS Address [TBD]

3A 3A
2.2K +3.3V_ALW SMBUS Address
2.2K
APR_EC: 0x48
B4 DOCK_SMB_CLK 127
1A SPR_EC: 0x70
129 MSLICE_EC: 0x72 2.2K
+3.3V_RUN
1A A3 DOCK_SMB_DAT DOCKING
USB: 0x59
AUDIO: 0x34 14
SLICE_BATTERY: 0x17 13 G Sensor
2.2K SMBUS Address [3B]
SLICE_CHARGER: 0x13
C
+3.3V_ALW C

2.2K
B5 LCD_SMBCLK 30
1B WWAN
A4 LCD_SMBDAT 32 SMBUS Address [TBD]
1B
2.2K

KBC 2.2K
+3.3V_ALW
100 ohm 7
1C A56 PBAT_SMBCLK
6 BATTERY SMBUS Address [0x16]
1C B59 PBAT_SMBDAT 100 ohm
CONN
2.2K

+3.3V_ALW
2.2K
A50 M9
1E USH_SMBCLK
B53 L9 USH SMBUS Address [0xa4]
1E USH_SMBDAT
B B
2.2K

+3.3V_SUS
2.2K
MEC 5065 7
2B A49 CARD_SMBCLK
8 Express card SMBUS Address [TBD]
2B B52 CARD_SMBDAT

2.2K
+3.3V_ALW
2.2K
B50 10
1G CHARGER_SMBCLK
A47 9 Charger
1G CHARGER_SMBDAT SMBUS Address [0x12]

2.2K
+3.3V_ALW
2.2K
B7 BAY_SMBDAT 29
2D
30 E3 Module Bay
A A7 BAY_SMBCLK SMBUS Address [0xd2] A
2D

Compal Electronics, Inc.


Title
SMBUS TOPOLOGY
Size Document Number Rev
0.1
LA-7741
Date: Thursday, June 23, 2011 Sheet 5 of 56
5 4 3 2 1
5 4 3 2 1

(1)PEG_RCOMPO (G4) use 4mil connect to PEG_ICOMPI, then use 4mil connect to RC2. U1I
(2)PEG_ICOMPO use 12mil connect to RC2

BG17 VSS[181] VSS[250] M4


BG21 VSS[182] VSS[251] M58
+1.05V_RUN_VTT BG24 M6
VSS[183] VSS[252]
BG28 VSS[184] VSS[253] N1
BG37 VSS[185] VSS[254] N17

1
BG41 N21
RC2 VSS[186] VSS[255]
BG45 N25
VSS[187] VSS[256]
24.9_0402_1%~D BG49 N28
D VSS[188] VSS[257] D
BG53 N33
U1A VSS[189] VSS[258]
BG9 N36

2
PEG_COMP VSS[190] VSS[259]
G3 C29 N40
PEG_ICOMPI VSS[191] VSS[260]
G1 C35 N43
DMI_CRX_PTX_N0 PEG_ICOMPO VSS[192] VSS[261]
<16> DMI_CRX_PTX_N0 M2 G4 C40 N47
DMI_CRX_PTX_N1 DMI_RX#[0] PEG_RCOMPO VSS[193] VSS[262]
<16> DMI_CRX_PTX_N1 P6
DMI_RX#[1] PEG Compensation D10
VSS[194] VSS[263]
N48
DMI_CRX_PTX_N2 P1 D14 N51
<16> DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 DMI_RX#[2] VSS[195] VSS[264]
<16> DMI_CRX_PTX_N3 P10 H22 D18 N52
DMI_RX#[3] PEG_RX#[0] VSS[196] VSS[265]
J21 D22 N56
DMI_CRX_PTX_P0 PEG_RX#[1] VSS[197] VSS[266]
<16> DMI_CRX_PTX_P0 N3 B22 D26 N61
DMI_CRX_PTX_P1 DMI_RX[0] PEG_RX#[2] PEG_ICOMPI and RCOMPO signals should be shorted and routed VSS[198] VSS[267]
<16> DMI_CRX_PTX_P1 P7 D21 D29 P14
DMI_RX[1] PEG_RX#[3] VSS[199] VSS[268]

DMI
DMI_CRX_PTX_P2 P3 A19 with - max length = 500 mils - typical impedance = 43 mohms D35 P16
<16> DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 DMI_RX[2] PEG_RX#[4] VSS[200] VSS[269]
<16> DMI_CRX_PTX_P3 P11 DMI_RX[3] PEG_RX#[5] D17 PEG_ICOMPO signals should be routed with - max length = 500 mils D4 VSS[201] VSS[270] P18
PEG_RX#[6] B14 - typical impedance = 14.5 mohms D40 VSS[202] VSS[271] P21
DMI_CTX_PRX_N0 K1 D13 D43 P58
<16>
<16>
<16>
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
M8
N4
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
A11
B10
D46
D50
VSS[203]
VSS[204]
VSS[205]
VSS VSS[272]
VSS[273]
VSS[274]
P59
P9
<16> DMI_CTX_PRX_N3 DMI_CTX_PRX_N3 R2 G8 D54 R17
DMI_TX#[3] PEG_RX#[10] VSS[206] VSS[275]
PEG_RX#[11] A8 D58 VSS[207] VSS[276] R20
<16> DMI_CTX_PRX_P0 DMI_CTX_PRX_P0 K3 B6 D6 R4
DMI_CTX_PRX_P1 DMI_TX[0] PEG_RX#[12] VSS[208] VSS[277]
<16> DMI_CTX_PRX_P1 M7 DMI_TX[1] PEG_RX#[13] H8 E25 VSS[209] VSS[278] R46
<16> DMI_CTX_PRX_P2 DMI_CTX_PRX_P2 P4 E5 E29 T1
DMI_CTX_PRX_P3 DMI_TX[2] PEG_RX#[14] VSS[210] VSS[279]
<16> DMI_CTX_PRX_P3 T3 DMI_TX[3] PEG_RX#[15] K7 E3 VSS[211] VSS[280] T47
E35 VSS[212] VSS[281] T50
PEG_RX[0] K22 E40 VSS[213] VSS[282] T51
PEG_RX[1] K19 F13 VSS[214] VSS[283] T52
PEG_RX[2] C21 F15 VSS[215] VSS[284] T53
<16> FDI_CTX_PRX_N0 FDI_CTX_PRX_N0 U7 D19 F19 T55
FDI_CTX_PRX_N1 FDI0_TX#[0] PEG_RX[3] VSS[216] VSS[285]
<16> FDI_CTX_PRX_N1 W11 FDI0_TX#[1] PEG_RX[4] C19 F29 VSS[217] VSS[286] T56
<16> FDI_CTX_PRX_N2 FDI_CTX_PRX_N2 W1 D16 F35 U13
FDI_CTX_PRX_N3 FDI0_TX#[2] PEG_RX[5] VSS[218] VSS[287]
<16> FDI_CTX_PRX_N3 AA6 FDI0_TX#[3] PEG_RX[6] C13 F40 VSS[219] VSS[288] U8
<16> FDI_CTX_PRX_N4 FDI_CTX_PRX_N4 W6 D12 F55 V20
C FDI_CTX_PRX_N5 FDI1_TX#[0] PEG_RX[7] VSS[220] VSS[289] C
<16> FDI_CTX_PRX_N5 V4 FDI1_TX#[1] PEG_RX[8] C11 G51 VSS[221] VSS[290] V61

PCI EXPRESS -- GRAPHICS


<16> FDI_CTX_PRX_N6 FDI_CTX_PRX_N6 Y2 C9 G6 W13
FDI_CTX_PRX_N7 FDI1_TX#[2] PEG_RX[9] VSS[222] VSS[291]
<16> FDI_CTX_PRX_N7 AC9 FDI1_TX#[3] PEG_RX[10] F8 G61 VSS[223] VSS[292] W15

Intel(R) FDI
PEG_RX[11] C8 H10 VSS[224] VSS[293] W18
PEG_RX[12] C5 H14 VSS[225] VSS[294] W21
<16> FDI_CTX_PRX_P0 FDI_CTX_PRX_P0 U6 H6 H17 W46
FDI_CTX_PRX_P1 FDI0_TX[0] PEG_RX[13] VSS[226] VSS[295]
<16> FDI_CTX_PRX_P1 W10 FDI0_TX[1] PEG_RX[14] F6 H21 VSS[227] VSS[296] W8
FDI_CTX_PRX_P2 T23 @
<16> FDI_CTX_PRX_P2 W3 K6 H4 Y4
FDI_CTX_PRX_P3 FDI0_TX[2] PEG_RX[15] VSS[228] VSS[297] PAD~D
<16> FDI_CTX_PRX_P3 AA7 H53 Y47
FDI_CTX_PRX_P4 FDI0_TX[3] VSS[229] VSS[298]
<16> FDI_CTX_PRX_P4 W7 G22 H58 Y58
FDI_CTX_PRX_P5 FDI1_TX[0] PEG_TX#[0] VSS[230] VSS[299]
<16> FDI_CTX_PRX_P5 T4 C23 J1 Y59
FDI_CTX_PRX_P6 FDI1_TX[1] PEG_TX#[1] VSS[231] VSS[300]
<16> FDI_CTX_PRX_P6 AA3 D23 J49 G48 TP_G48
FDI_CTX_PRX_P7 FDI1_TX[2] PEG_TX#[2] VSS[232] VSS[301]
<16> FDI_CTX_PRX_P7 AC8 F21 J55
FDI1_TX[3] PEG_TX#[3] VSS[233]
H19 K11
FDI_FSYNC0 PEG_TX#[4] VSS[234]
<16> FDI_FSYNC0 AA11 C17 K21
FDI_FSYNC1 FDI0_FSYNC PEG_TX#[5] VSS[235]
<16> FDI_FSYNC1 AC12 K15 K51
FDI1_FSYNC PEG_TX#[6] VSS[236]
F17 K8 A5
FDI_INT PEG_TX#[7] VSS[237] VSS_NCTF_1
<16> FDI_INT U11 F14 L16 A57
FDI_INT PEG_TX#[8] VSS[238] VSS_NCTF_2
A15 L20 BC61
FDI_LSYNC0 PEG_TX#[9] VSS[239] VSS_NCTF_3
<16> FDI_LSYNC0 AA10 J14 L22 BD3
FDI_LSYNC1 FDI0_LSYNC PEG_TX#[10] VSS[240] VSS_NCTF_4
<16> FDI_LSYNC1 AG8 H13 L26 BD59
FDI1_LSYNC PEG_TX#[11] VSS[241] VSS_NCTF_5
M10 L30 BE4

NCTF
PEG_TX#[12] VSS[242] VSS_NCTF_6
(1) EDP_COMPIO use 4mil trace to RC1 PEG_TX#[13]
F10 L34
VSS[243] VSS_NCTF_7
BE58
D9 L38 BG5
(2) EDP_ICOMPO use 12mil to RC1 PEG_TX#[14] VSS[244] VSS_NCTF_8
J4 L43 BG57
EDP_COMP PEG_TX#[15] VSS[245] VSS_NCTF_9
AF3 L48 C3
eDP_COMPIO VSS[246] VSS_NCTF_10
AD2 F22 L61 C58
eDP_ICOMPO PEG_TX[0] VSS[247] VSS_NCTF_11
AG11 A23 M11 D59
eDP_HPD# PEG_TX[1] VSS[248] VSS_NCTF_12
D24 M15 E1
PEG_TX[2] VSS[249] VSS_NCTF_13
E21 E61
PEG_TX[3] VSS_NCTF_14
AG4 G19
eDP_AUX# PEG_TX[4]
AF4 B18
B eDP_AUX PEG_TX[5] B
K17
PEG_TX[6]
eDP

G17
PEG_TX[7]
AC3 E14
eDP_TX#[0] PEG_TX[8] IVY-BRIDGE_BGA1023~D
AC4 C15
eDP_TX#[1] PEG_TX[9]
AE11 K13
eDP_TX#[2] PEG_TX[10]
AE7 G13
eDP_TX#[3] PEG_TX[11]
K10
PEG_TX[12]
AC1 G10
eDP_TX[0] PEG_TX[13]
AA4 D8
eDP_TX[1] PEG_TX[14]
AE10 K4
eDP_TX[2] PEG_TX[15]
AE6
eDP_TX[3]

IVY-BRIDGE_BGA1023~D

eDP Compensation

+1.05V_RUN_VTT
1

RC1
24.9_0402_1%~D
A A
2

EDP_COMP

DELL CONFIDENTIAL/PROPRIETARY
eDP_COMPIO and ICOMPO signals should be shorted near
balls and routed with typical impedance <25 mohms
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Sandy Bridge (1/6)
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-7741
Date: Thursday, June 23, 2011 Sheet 6 of 56
5 4 3 2 1
5 4 3 2 1

+1.05V_RUN_VTT +1.05V_RUN_VTT
+1.5V_CPU_VDDQ +3.3V_ALW_PCH

0.1U_0402_25V6K~D
+3.3V_ALW_PCH

1
CC156 0.1U_0402_25V6K~D 1

1
1 2 RC12 JXDP1 @

CC65
200_0402_1%~D XDP_PREQ# 1 OBSFN_A0

5
UC2 @ RC124 XDP_PRDY# 2
1K_0402_1%~D 2 OBSFN_A1
1 B 3

P
<39,40> RUNPWROK

2
RUNPWROK_AND GND
4 1 2 PM_DRAM_PWRGD_CPU 4

2
O RC28 130_0402_1%~D OBSDATA_A[0]
+3.3V_ALW_PCH 1 2 2 5
A OBSDATA_A[1]

2
RC18 200_0402_1%~D SYS_PWROK_XDP 6
74AHC1G09GW_TSSOP5~D RC64 @ GND
<16> PM_DRAM_PWRGD Place near JXDP1 7

3
39_0402_5%~D OBSDATA_A[2]
8
D OBSDATA_A[3] D
9
H_CPUPWRGD H_CPUPWRGD_XDP GND
1 2 10

1 1
HOOK0
<14,16> SIO_PWRBTN#_R
RC51 2 1K_0402_1%~D CFD_PWRBTN#_XDP 11
HOOK1
D
<9> CFG0
RC61 2 0_0402_5%~D XDP_HOOK2 12
HOOK2
<11,42> RUN_ON_CPU1.5VS3# 2 QC1 @
<16,39> SYS_PWROK
RC71 2 1K_0402_1%~D SYS_PWROK_XDP 13
G SSM3K7002FU_SC70-3~D @RC9
@ RC9 0_0402_5%~D CLK_XDP HOOK3
14
CLK_XDP# HOOK4
S 15

3
HOOK5
16
VCCOBS_AB
<17> PLTRST_XDP#
RC8 1 2 1K_0402_5%~D XDP_RST#_R 17
HOOK6
XDP_DBRESET# 18
HOOK7
19
XDP_TDO GND
20 TDO
INTEL suggest RC64 and QC1 NO stuff by default XDP_TRST# 21
XDP_TDI TRSTn
22 TDI
XDP_TMS 23 TMS
24 TCK1 GND 27
+1.05V_RUN_VTT 25 28
XDP_TCLK GND GND
26 TCK0
1 2 H_THERMTRIP# MOLEX_52435-2671
@ RC126 56_0402_5%~D
1 2 H_CATERR#
@ RC128 49.9_0402_1%~D
1 2 H_PROCHOT#
RC44 62_0402_5%~D U1B

J3 CPU_DMI 1 2
BCLK CPU_DMI# CLK_CPU_DMI <15>
H2 RC13 1 2 0_0402_5%~D
BCLK# CLK_CPU_DMI# <15>

MISC
Follow check list 0.5 RC15 0_0402_5%~D

CLOCKS
<18> H_SNB_IVB# F49 PROC_SELECT#
AG3 CPU_DPLL 1 2
DPLL_REF_CLK CPU_DPLL# RC16 1
DPLL_REF_CLK# AG1 2 1K_0402_5%~D
C RC17 1K_0402_5%~D C
<39> CPU_DETECT# C57 PROC_DETECT#
N59 CLK_XDP_ITP
BCLK_ITP CLK_XDP_ITP#
BCLK_ITP# N58 +1.05V_RUN_VTT
1 2 CLK_XDP 1 2
H_CATERR# CLK_CPU_ITP <15>
C49 @ RC48
@RC48 0_0402_5%~D RH107 0_0402_5%~D
CATERR# CLK_XDP#
THERMAL 1 2 CLK_CPU_ITP# <15>
RH106 0_0402_5%~D

D
A48 AT30 DDR3_DRAMRST#_CPU 3 1
<40> PECI_EC PECI SM_DRAMRST# DDR3_DRAMRST# <12>

VR1 TOPOLOGY Max 500mils QC2


SM_RCOMP0 BSS138W-7-F_SOT323-3~D CLK_XDP_ITP

G
BF44 1 2

2
SM_RCOMP[0]

1
DDR3
<40,51,53> H_PROCHOT# 1 2 H_PROCHOT#_R C45
PROCHOT#
MISC SM_RCOMP[1]
BE43 SM_RCOMP1
SM_RCOMP2 CLK_XDP_ITP#
@ RH109 0_0402_5%~D
RC57 56_0402_5%~D BG43 RC50 1 2
SM_RCOMP[2] DDR_HVREF_RST
place RC57 near CPU 300mils ~1530mils 4.99K_0402_1%~D @ RH108 0_0402_5%~D
SM_RCOMP2 --> 15mil
<22> H_THERMTRIP# 1 2 H_THERMTRIP#_R D45 1

2
RC129 0_0402_5%~D THERMTRIP# SM_RCOMP1/0 --> 20mil
CC177
place RC129 near CPU 250mils~2530 mils N53 XDP_PRDY# 0.047U_0402_16V4Z~D
PRDY# XDP_PREQ# 2
N55
PREQ#
L56 XDP_TCLK
TCK XDP_TMS
L55
TMS
PWR MANAGEMENT

J58 XDP_TRST# 1 2
TRST# <15> DDR_HVREF_RST_PCH
RC46 0_0402_5%~D
JTAG & BPM

H_PM_SYNC C48 M60 XDP_TDI_R 1 2


<16> H_PM_SYNC PM_SYNC TDI XDP_TDO_R <40> DDR_HVREF_RST_GATE DDR_HVREF_RST <12>
L59 @RC47
@ RC47 0_0402_5%~D
TDO
M3 control
<18> H_CPUPWRGD 1 2 VCCPWRGOOD_0_R B46
B RC25 0_0402_5%~D UNCOREPWRGOOD XDP_DBRESET#_R XDP_DBRESET# B
K58 2 1 XDP_DBRESET# <14,16>
DBR# RC26 0_0402_5%~D

PM_DRAM_PWRGD_CPUBE45 G58 @ T128 PAD~D


SM_DRAMPWROK BPM#[0] @ T131 PAD~D
E55
BPM#[1] @ T129 PAD~D
E59
BPM#[2] XDP_TDI_R XDP_TDI
BPM#[3]
G55 @ T130 PAD~D @ T133 PAD~D 1 2 PU/PD for JTAG signals
G59 @ T125 PAD~D RC23 0_0402_5%~D
PCH_PLTRST#_R BPM#[4] @ T126 PAD~D @ T134 PAD~D +3.3V_RUN
D44 H60
RESET# BPM#[5] BPM#6 @ T107 PAD~D
J59
BPM#[6] BPM#7 @ T127 PAD~D XDP_TDO_R XDP_TDO
J61 1 2
BPM#[7] RC24 0_0402_5%~D XDP_DBRESET#RC19 2 1 1K_0402_1%~D

+1.05V_RUN_VTT
T133 place near T107;T134 pleace near T127
XDP_TMS RC27 2 1 51_0402_1%~D
IVY-BRIDGE_BGA1023~D For ESD concern, please put near CPU XDP_TDI RC29 2 1 51_0402_1%~D

XDP_PREQ# @ RC32 2 1 51_0402_1%~D


Buffered reset to CPU +3.3V_RUN VCCPWRGOOD_0_R
+1.05V_RUN_VTT SM_RCOMP2 XDP_TDO RC35 2 1 51_0402_1%~D
SM_RCOMP1
1
0.1U_0402_25V6K~D

SM_RCOMP0
1 RC130
1

140_0402_1%~D

200_0402_1%~D
75_0402_1%~D

RC4

25.5_0402_1%~D
10K_0402_5%~D XDP_TCLK RC40 2 1

1
CC140

51_0402_1%~D

RC42

RC43

RC45
XDP_TRST# RC41 2 1
2

2 51_0402_1%~D
UC1
2

1 5

2
A NC VCC A
<14,17> PCH_PLTRST# 2 A
3 4 PCH_PLTRST#_BUF 1 2 PCH_PLTRST#_R
GND Y RC10 43_0402_5%~D Avoid stub in the PWRGD path
SN74LVC1G07DCKR_SC70-5~D while placing resistors RC25 & RC130
Open drain buffer
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Sandy Bridge (2/6)
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-7741
Date: Thursday, June 23, 2011 Sheet 7 of 56
5 4 3 2 1
5 4 3 2 1

U1D
U1C
D <13> DDR_B_D[0..63] D
<12> DDR_A_D[0..63] DDR_B_D0 AL4
DDR_A_D0 DDR_B_D1 SB_DQ[0] M_CLK_DDR2
AG6 AL1 BA34 M_CLK_DDR2 <13>
DDR_A_D1 SA_DQ[0] M_CLK_DDR0 DDR_B_D2 SB_DQ[1] SB_CK[0] M_CLK_DDR#2
AJ6 AU36 M_CLK_DDR0 <12> AN3 AY34 M_CLK_DDR#2 <13>
DDR_A_D2 SA_DQ[1] SA_CK[0] M_CLK_DDR#0 DDR_B_D3 SB_DQ[2] SB_CK#[0] DDR_CKE2_DIMMB
AP11 AV36 M_CLK_DDR#0 <12> AR4 AR22 DDR_CKE2_DIMMB <13>
DDR_A_D3 SA_DQ[2] SA_CK#[0] DDR_CKE0_DIMMA DDR_B_D4 SB_DQ[3] SB_CKE[0]
AL6 AY26 DDR_CKE0_DIMMA <12> AK4
DDR_A_D4 SA_DQ[3] SA_CKE[0] DDR_B_D5 SB_DQ[4]
AJ10 AK3
DDR_A_D5 SA_DQ[4] DDR_B_D6 SB_DQ[5]
AJ8 AN4
DDR_A_D6 SA_DQ[5] DDR_B_D7 SB_DQ[6]
AL8 AR1
DDR_A_D7 SA_DQ[6] DDR_B_D8 SB_DQ[7]
AL7 AU4
DDR_A_D8 SA_DQ[7] DDR_B_D9 SB_DQ[8] M_CLK_DDR3
AR11 AT2 BA36 M_CLK_DDR3 <13>
DDR_A_D9 SA_DQ[8] M_CLK_DDR1 DDR_B_D10 SB_DQ[9] SB_CK[1] M_CLK_DDR#3
AP6 SA_DQ[9] SA_CK[1] AT40 M_CLK_DDR1 <12> AV4 SB_DQ[10] SB_CK#[1] BB36 M_CLK_DDR#3 <13>
DDR_A_D10 AU6 AU40 M_CLK_DDR#1 DDR_B_D11 BA4 BF27 DDR_CKE3_DIMMB
SA_DQ[10] SA_CK#[1] M_CLK_DDR#1 <12> SB_DQ[11] SB_CKE[1] DDR_CKE3_DIMMB <13>
DDR_A_D11 AV9 BB26 DDR_CKE1_DIMMA DDR_B_D12 AU3
DDR_A_D12 SA_DQ[11] SA_CKE[1] DDR_CKE1_DIMMA <12> DDR_B_D13 SB_DQ[12]
AR6 SA_DQ[12] AR3 SB_DQ[13]
DDR_A_D13 AP8 DDR_B_D14 AY2
DDR_A_D14 SA_DQ[13] DDR_B_D15 SB_DQ[14]
AT13 SA_DQ[14] BA3 SB_DQ[15]
DDR_A_D15 AU13 DDR_B_D16 BE9
DDR_A_D16 SA_DQ[15] DDR_B_D17 SB_DQ[16] DDR_CS2_DIMMB#
BC7 SA_DQ[16] BD9 SB_DQ[17] SB_CS#[0] BE41 DDR_CS2_DIMMB# <13>
DDR_A_D17 BB7 BB40 DDR_CS0_DIMMA# DDR_B_D18 BD13 BE47 DDR_CS3_DIMMB#
SA_DQ[17] SA_CS#[0] DDR_CS0_DIMMA# <12> SB_DQ[18] SB_CS#[1] DDR_CS3_DIMMB# <13>
DDR_A_D18 BA13 BC41 DDR_CS1_DIMMA# DDR_B_D19 BF12
DDR_A_D19 SA_DQ[18] SA_CS#[1] DDR_CS1_DIMMA# <12> DDR_B_D20 SB_DQ[19]
BB11 SA_DQ[19] BF8 SB_DQ[20]
DDR_A_D20 BA7 DDR_B_D21 BD10
DDR_A_D21 SA_DQ[20] DDR_B_D22 SB_DQ[21]
BA9 SA_DQ[21] BD14 SB_DQ[22]
DDR_A_D22 BB9 DDR_B_D23 BE13
DDR_A_D23 SA_DQ[22] DDR_B_D24 SB_DQ[23] M_ODT2
AY13 SA_DQ[23] BF16 SB_DQ[24] SB_ODT[0] AT43 M_ODT2 <13>
DDR_A_D24 AV14 AY40 M_ODT0 DDR_B_D25 BE17 BG47 M_ODT3
DDR_A_D25 SA_DQ[24] SA_ODT[0] M_ODT1 M_ODT0 <12> DDR_B_D26 SB_DQ[25] SB_ODT[1] M_ODT3 <13>
AR14 SA_DQ[25] SA_ODT[1] BA41 M_ODT1 <12> BE18 SB_DQ[26]
DDR_A_D26 AY17 DDR_B_D27 BE21
DDR_A_D27 SA_DQ[26] DDR_B_D28 SB_DQ[27]
AR19 SA_DQ[27] BE14 SB_DQ[28]
DDR_A_D28 BA14 DDR_B_D29 BG14
DDR_A_D29 SA_DQ[28] DDR_B_D30 SB_DQ[29]
AU14 SA_DQ[29] BG18 SB_DQ[30] DDR_B_DQS#[0..7] <13>
C DDR_A_D30 DDR_B_D31 DDR_B_DQS#0 C
BB14 SA_DQ[30] DDR_A_DQS#[0..7] <12> BF19 SB_DQ[31] SB_DQS#[0] AL3
DDR_A_D31 BB17 AL11 DDR_A_DQS#0 DDR_B_D32 BD50 AV3 DDR_B_DQS#1
DDR_A_D32 SA_DQ[31] SA_DQS#[0] DDR_A_DQS#1 DDR_B_D33 SB_DQ[32] SB_DQS#[1] DDR_B_DQS#2
BA45 SA_DQ[32] SA_DQS#[1] AR8 BF48 SB_DQ[33] SB_DQS#[2] BG11
DDR_A_D33 AR43 AV11 DDR_A_DQS#2 DDR_B_D34 BD53 BD17 DDR_B_DQS#3
DDR_A_D34 SA_DQ[33] SA_DQS#[2] DDR_A_DQS#3 DDR_B_D35 SB_DQ[34] SB_DQS#[3] DDR_B_DQS#4
AW48 SA_DQ[34] SA_DQS#[3] AT17 BF52 SB_DQ[35] SB_DQS#[4] BG51
DDR_A_D35 BC48 AV45 DDR_A_DQS#4 DDR_B_D36 BD49 BA59 DDR_B_DQS#5
DDR_A_D36 SA_DQ[35] SA_DQS#[4] DDR_A_DQS#5 DDR_B_D37 SB_DQ[36] SB_DQS#[5] DDR_B_DQS#6
BC45 SA_DQ[36] SA_DQS#[5] AY51 BE49 SB_DQ[37] SB_DQS#[6] AT60

DDR SYSTEM MEMORY B


DDR_A_D37 AR45 AT55 DDR_A_DQS#6 DDR_B_D38 BD54 AK59 DDR_B_DQS#7
SA_DQ[37] SA_DQS#[6] SB_DQ[38] SB_DQS#[7]
DDR SYSTEM MEMORY A

DDR_A_D38 AT48 AK55 DDR_A_DQS#7 DDR_B_D39 BE53


DDR_A_D39 SA_DQ[38] SA_DQS#[7] DDR_B_D40 SB_DQ[39]
AY48 BF56
DDR_A_D40 SA_DQ[39] DDR_B_D41 SB_DQ[40]
BA49 BE57
DDR_A_D41 SA_DQ[40] DDR_B_D42 SB_DQ[41]
AV49 BC59
DDR_A_D42 SA_DQ[41] DDR_B_D43 SB_DQ[42]
BB51 AY60
DDR_A_D43 SA_DQ[42] DDR_B_D44 SB_DQ[43]
AY53 BE54
DDR_A_D44 SA_DQ[43] DDR_B_D45 SB_DQ[44]
BB49 DDR_A_DQS[0..7] <12> BG54 DDR_B_DQS[0..7] <13>
DDR_A_D45 SA_DQ[44] DDR_A_DQS0 DDR_B_D46 SB_DQ[45] DDR_B_DQS0
AU49 AJ11 BA58 AM2
DDR_A_D46 SA_DQ[45] SA_DQS[0] DDR_A_DQS1 DDR_B_D47 SB_DQ[46] SB_DQS[0] DDR_B_DQS1
BA53 AR10 AW59 AV1
DDR_A_D47 SA_DQ[46] SA_DQS[1] DDR_A_DQS2 DDR_B_D48 SB_DQ[47] SB_DQS[1] DDR_B_DQS2
BB55 AY11 AW58 BE11
DDR_A_D48 SA_DQ[47] SA_DQS[2] DDR_A_DQS3 DDR_B_D49 SB_DQ[48] SB_DQS[2] DDR_B_DQS3
BA55 AU17 AU58 BD18
DDR_A_D49 SA_DQ[48] SA_DQS[3] DDR_A_DQS4 DDR_B_D50 SB_DQ[49] SB_DQS[3] DDR_B_DQS4
AV56 AW45 AN61 BE51
DDR_A_D50 SA_DQ[49] SA_DQS[4] DDR_A_DQS5 DDR_B_D51 SB_DQ[50] SB_DQS[4] DDR_B_DQS5
AP50 AV51 AN59 BA61
DDR_A_D51 SA_DQ[50] SA_DQS[5] DDR_A_DQS6 DDR_B_D52 SB_DQ[51] SB_DQS[5] DDR_B_DQS6
AP53 AT56 AU59 AR59
DDR_A_D52 SA_DQ[51] SA_DQS[6] DDR_A_DQS7 DDR_B_D53 SB_DQ[52] SB_DQS[6] DDR_B_DQS7
AV54 AK54 AU61 AK61
DDR_A_D53 SA_DQ[52] SA_DQS[7] DDR_B_D54 SB_DQ[53] SB_DQS[7]
AT54 AN58
DDR_A_D54 SA_DQ[53] DDR_B_D55 SB_DQ[54]
AP56 AR58
DDR_A_D55 SA_DQ[54] DDR_B_D56 SB_DQ[55]
AP52 AK58
DDR_A_D56 SA_DQ[55] DDR_B_D57 SB_DQ[56]
AN57 AL58
DDR_A_D57 SA_DQ[56] DDR_B_D58 SB_DQ[57]
AN53 AG58
DDR_A_D58 SA_DQ[57] DDR_B_D59 SB_DQ[58]
AG56 AG59 DDR_B_MA[0..15] <13>
DDR_A_D59 SA_DQ[58] DDR_B_D60 SB_DQ[59]
AG53 DDR_A_MA[0..15] <12> AM60
DDR_A_D60 SA_DQ[59] DDR_B_D61 SB_DQ[60] DDR_B_MA0
AN55 AL59 BF32
DDR_A_D61 SA_DQ[60] DDR_A_MA0 DDR_B_D62 SB_DQ[61] SB_MA[0] DDR_B_MA1
AN52 BG35 AF61 BE33
B DDR_A_D62 SA_DQ[61] SA_MA[0] DDR_A_MA1 DDR_B_D63 SB_DQ[62] SB_MA[1] DDR_B_MA2 B
AG55 BB34 AH60 BD33
DDR_A_D63 SA_DQ[62] SA_MA[1] DDR_A_MA2 SB_DQ[63] SB_MA[2] DDR_B_MA3
AK56 BE35 AU30
SA_DQ[63] SA_MA[2] DDR_A_MA3 SB_MA[3] DDR_B_MA4
BD35 BD30
SA_MA[3] DDR_A_MA4 SB_MA[4] DDR_B_MA5
AT34 AV30
SA_MA[4] DDR_A_MA5 SB_MA[5] DDR_B_MA6
AU34 BG30
SA_MA[5] DDR_A_MA6 DDR_B_BS0 SB_MA[6] DDR_B_MA7
BB32 <13> DDR_B_BS0 BG39 BD29
DDR_A_BS0 SA_MA[6] DDR_A_MA7 DDR_B_BS1 SB_BS[0] SB_MA[7] DDR_B_MA8
<12> DDR_A_BS0 BD37 AT32 <13> DDR_B_BS1 BD42 BE30
DDR_A_BS1 SA_BS[0] SA_MA[7] DDR_A_MA8 DDR_B_BS2 SB_BS[1] SB_MA[8] DDR_B_MA9
<12> DDR_A_BS1 BF36 AY32 <13> DDR_B_BS2 AT22 BE28
DDR_A_BS2 SA_BS[1] SA_MA[8] DDR_A_MA9 SB_BS[2] SB_MA[9] DDR_B_MA10
<12> DDR_A_BS2 BA28 AV32 BD43
SA_BS[2] SA_MA[9] DDR_A_MA10 SB_MA[10] DDR_B_MA11
BE37 AT28
SA_MA[10] DDR_A_MA11 SB_MA[11] DDR_B_MA12
BA30 AV28
SA_MA[11] DDR_A_MA12 DDR_B_CAS# SB_MA[12] DDR_B_MA13
BC30 <13> DDR_B_CAS# AV43 BD46
DDR_A_CAS# SA_MA[12] DDR_A_MA13 DDR_B_RAS# SB_CAS# SB_MA[13] DDR_B_MA14
<12> DDR_A_CAS# BE39 AW41 <13> DDR_B_RAS# BF40 AT26
DDR_A_RAS# SA_CAS# SA_MA[13] DDR_A_MA14 DDR_B_WE# SB_RAS# SB_MA[14] DDR_B_MA15
<12> DDR_A_RAS# BD39 AY28 <13> DDR_B_WE# BD45 AU22
DDR_A_WE# SA_RAS# SA_MA[14] DDR_A_MA15 SB_WE# SB_MA[15]
<12> DDR_A_WE# AT41 AU26
SA_WE# SA_MA[15]

IVY-BRIDGE_BGA1023~D
IVY-BRIDGE_BGA1023~D

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Sandy Bridge (3/6)
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-7741
Date: Thursday, June 23, 2011 Sheet 8 of 56
5 4 3 2 1
5 4 3 2 1

CFG Straps for Processor

CFG2

1
@ RC51
1K_0402_1%~D

2
D D
U1E
+VCC_GFXCORE

1 2 VAXG_VAL_SENSE <7> CFG0


CFG0 B50
CFG[0] RSVD28
BE7 +DIMM0_1_VREF_CPU +DIMM0_1_VREF_CPU
@ RC122 49.9_0402_1%~D @ T11 PAD~D CFG1 C51 BG7 +DIMM0_1_CA_CPU PEG Static Lane Reversal - CFG2 is for the 16x
CFG[1] RSVD29 +DIMM0_1_CA_CPU
1

CFG2 B54
@ RC69 @ T13 PAD~D CFG3 CFG[2]
D53
CFG4 CFG[3]
100_0402_1%~D A51
CFG[4] RSVD30
N42 1:(Default) Normal Operation; Lane #
CFG5 C53 L42 CFG2
CFG6 C55
CFG[5] RSVD31
L45
definition matches socket pin map definition
2

CFG[6] RSVD32
1 2 VSSAXG_VAL_SENSE CFG7 H49 CFG[7] RSVD33 L47 0:Lane Reversed
@ RC123 49.9_0402_1%~D @ T17 PAD~D CFG8 A55
@ T18 PAD~D CFG9 CFG[8]
H51 CFG[9]
@ T15 PAD~D CFG10 K49 M13
@ T16 PAD~D CFG11 CFG[10] RSVD34 CFG4
K53 CFG[11] RSVD35 M14
@ T9 PAD~D CFG12 F53 U14
CFG[12] RSVD36

1
@ T10 PAD~D CFG13 G53 W14
@ T12 PAD~D CFG14 CFG[13] RSVD37 @ RC52
L51 CFG[14] RSVD38 P13
@ T14 PAD~D CFG15 F51 1K_0402_1%~D
@ T20 PAD~D CFG16 CFG[15]
D52 CFG[16]
@ T19 PAD~D CFG17 L53 AT49

2
CFG[17] RSVD39
RSVD40 K24

RESERVED
VCC_VAL_SNESE H43
VSS_VAL_SNESE VCC_VAL_SENSE
K43 VSS_VAL_SENSE RSVD41 AH2
+VCC_CORE AG13
RSVD42
RSVD43 AM14
1 2 VCC_VAL_SNESE VAXG_VAL_SENSE H45 VAXG_VAL_SENSE RSVD44 AM15 Display Port Presence Strap
@ RC120 49.9_0402_1%~D VSSAXG_VAL_SENSE K45 VSSAXG_VAL_SENSE
1

C EDS 1.0 RSVD_12 -> VCC_DIE_SENSE C


RSVD45 N50 1 : Disabled; No Physical Display Port
@ RC71 PAD~D T22 @ TP_VCC_DIESENSE F48 CFG4
VCC_DIE_SENSE attached to Embedded Display Port
100_0402_1%~D

H48 0 : Enabled; An external Display Port device is


2

RSVD6
1 2 VSS_VAL_SNESE K48 RSVD7 connected to the Embedded Display Port
@ RC121 49.9_0402_1%~D A4 TP_DC_TEST_A4 @ T121 PAD~D
DC_TEST_A4
C4
DC_TEST_C4 DC_TEST_C4_D3
BA19 D3
RSVD8 DC_TEST_D3 TP_DC_TEST_D1 @ T118 PAD~D
AV19 D1
RSVD9 DC_TEST_D1 TP_DC_TEST_A58 @ T119 PAD~D CFG6
AT21 A58
RSVD10 DC_TEST_A58
BB21 A59
RSVD11 DC_TEST_A59 DC_TEST_A59_C59 CFG5
BB19 C59
RSVD12 DC_TEST_C59
AY21 A61
RSVD13 DC_TEST_A61

1
BA22 C61 DC_TEST_A61_C61
RSVD14 DC_TEST_C61 TP_DC_TEST_D61 @ T120 PAD~D @ RC54 @ RC53
AY22 D61
RSVD15 DC_TEST_D61 TP_DC_TEST_BD61 @ T122 PAD~D 1K_0402_1%~D
AU19 BD61 1K_0402_1%~D
RSVD16 DC_TEST_BD61
AU21 BE61
RSVD17 DC_TEST_BE61 DC_TEST_BE59_BE61
BD21 BE59

2
RSVD18 DC_TEST_BE59
BD22 BG61
RSVD19 DC_TEST_BG61 DC_TEST_BG59_BG61
BD25 BG59
RSVD20 DC_TEST_BG59 TP_DC_TEST_BG58 @ T132 PAD~D
BD26 BG58
RSVD21 DC_TEST_BG58 TP_DC_TEST_BG4 @ T123 PAD~D
BG22 BG4
RSVD22 DC_TEST_BG4
BE22 BG3
RSVD23 DC_TEST_BG3 DC_TEST_BE3_BG3
BG26 BE3
RSVD24 DC_TEST_BE3
BE26 BG1
RSVD25 DC_TEST_BG1 DC_TEST_BE1_BG1
BF23 BE1
RSVD26 DC_TEST_BE1 TP_DC_TEST_BD1 @ T124 PAD~D
BE24
RSVD27 DC_TEST_BD1
BD1 PCIE Port Bifurcation Straps
1 2 +DIMM0_1_VREF_CPU
@ RC96 1K_0402_1%~D 11: (Default) x16 - Device 1 functions 1 and 2 disabled
1 2 +DIMM0_1_CA_CPU
B B
@ RC97 1K_0402_1%~D IVY-BRIDGE_BGA1023~D CFG[6:5] 10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

CFG7

1
@ RC56
1K_0402_1%~D

2
PEG DEFER TRAINING

1: (Default) PEG Train immediately


CFG7 following xxRESETB de assertion
0: PEG Wait for BIOS for training
A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Sandy Bridge (4/6)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.1
LA-7741
Date: Thursday, June 23, 2011 Sheet 9 of 56
5 4 3 2 1
5 4 3 2 1

U1F POWER +1.05V_RUN_VTT

+VCC_CORE
8.5A
VCCIO[1] AF46
53A VCCIO[3] AG48
AG50
VCCIO[4]
A26 VCC[1] VCCIO[5] AG51
A29 AJ17
VCC[2] VCCIO[6]
A31 AJ21
VCC[3] VCCIO[7]
A34 AJ25
D VCC[4] VCCIO[8] D
A35 AJ43
VCC[5] VCCIO[9]
A38 AJ47
VCC[6] VCCIO[10]
A39 AK50
VCC[7] VCCIO[11]
A42 AK51
VCC[8] VCCIO[12]
C26 AL14
VCC[9] VCCIO[13]
C27 AL15
VCC[10] VCCIO[14]
C32 AL16
VCC[11] VCCIO[15]
C34 AL20
VCC[12] VCCIO[16]
C37 AL22
VCC[13] VCCIO[17]
C39 AL26
VCC[14] VCCIO[18]
C42 AL45
VCC[15] VCCIO[19]
D27 VCC[16] VCCIO[20] AL48
D32 VCC[17] VCCIO[21] AM16
D34 VCC[18] VCCIO[22] AM17
D37 VCC[19] VCCIO[23] AM21
D39 AM43

PEG IO AND DDR IO


VCC[20] VCCIO[24]
D42 VCC[21] VCCIO[25] AM47
E26 VCC[22] VCCIO[26] AN20
E28 VCC[23] VCCIO[27] AN42
E32 VCC[24] VCCIO[28] AN45
E34 VCC[25] VCCIO[29] AN48
E37 VCC[26]
E38 VCC[27]

CORE SUPPLY
F25 VCC[28]
F26 VCC[29]
F28 VCC[30]
F32 +1.05V_RUN_VTT
VCC[31]
F34 VCC[32]
F37 VCC[33] VCCIO[30] AA14
F38 VCC[34] VCCIO[31] AA15
F42 VCC[35] VCCIO[32] AB17
G42 VCC[36] VCCIO[33] AB20
C C
H25 VCC[37] VCCIO[34] AC13
H26 VCC[38] VCCIO[35] AD16
H28 VCC[39] VCCIO[36] AD18
H29 VCC[40] VCCIO[37] AD21
H32 AE14 +1.05V_RUN_VTT
VCC[41] VCCIO[38]
H34 VCC[42] VCCIO[39] AE15
H35 VCC[43] VCCIO[40] AF16

1
H37 AF18
VCC[44] VCCIO[41]
H38 AF20 Note: Place the PU resistors close to CPU RC60
VCC[45] VCCIO[42] 75_0402_1%~D
H40 AG15 RC61 close to CPU 300 - 1500mils
VCC[46] VCCIO[43]
J25 AG16
VCC[47] VCCIO[44]
J26 AG17

2
VCC[48] VCCIO[45]
J28 AG20
VCC[49] VCCIO[46] H_CPU_SVIDALRT#
J29 AG21 1 2 VIDALERT_N <51>
VCC[50] VCCIO[47] RC61 43_0402_5%~D
J32 AJ14
VCC[51] VCCIO[48]
J34 AJ15
VCC[52] VCCIO[49]
J35
VCC[53]
J37
VCC[54] +3.3V_RUN
J38
VCC[55]
J40
VCC[56]
J42
VCC[57] CAD Note: Place the PU
K26 W16
VCC[58] VCCIO50

2
K27 W17 @ resistors close to CPU
VCC[59] VCCIO51 RC141
K29 RC63 close to CPU 300 - 1500mils
VCC[60]
K32 10K_0402_5%~D
VCC[61]
K34
VCC[62]
K35 Iccmax current changed for PDDG Rev0.7

1
VCC[63]
K37
VCC[64]
K39
K42
VCC[66]
BC22 1 2
CPU Power Rail Table
VCC[67] VCCIO_SEL VCCP_PWRCTRL <50>
L25
VCC[68]
RC140 0_0402_5%~D S0 Iccmax
L28
VCC[69]
Voltage Rail Voltage Current (A)
B B
L33
VCC[70]
L36
VCC[71] +1.05V_RUN_VTT
H_CPU_SVIDALRT# must be routed between the
L40 VCC 0.65-1.3 53
N26
VCC[72] VIDSOUT and VIDSCLK lines to reduce cross
VCC[73]

1U_0402_6.3V6K~D
talk. 18 mils spacing to others.
QUIET
RAILS

N30 AM25
VCC[74] VCCPQE[1]
N34
VCC[75] VCCPQE[2]
AN22 VCCIO 1.05/1 8.5
N38 1
VCC[76] +1.05V_RUN_VTT

CC573
VAXG 0.0-1.1 33

1
2
RC63 VCCPLL 1.8 1.2
130_0402_1%~D
A44 H_CPU_SVIDALRT#
VIDALERT# VIDSCLK
B43 VIDSCLK <51> VDDQ 1.5 5

2
VIDSCLK
SVID

C44 VIDSOUT
VIDSOUT VIDSOUT <51>
+VCC_CORE VCCSA 0.65-0.9 6

1
@ RC75 +1.5V_MEM 1.5 12-16 *
100_0402_1%~D RC66
Place RC66, RC70 ,RC133near CPU 1 2 100_0402_1%~D

2
VCCSENSE_R Description
VCC_SENSE
F43 1 2 VCCSENSE <51> *
SENSE LINES

G43 VSSSENSE_R RC67 1 2 0_0402_5%~D


VSS_SENSE VSSSENSE <51>
RC68 0_0402_5%~D 5A to Mem controller(+1.5V_CPU_VDDQ)
5-6A to 2 DIMMs/channel

1
2 1 +1.05V_RUN_VTT 2-5A to +1.5V_RUN & +0.75V_DDR_VTT
RC98 10_0402_1%~D RC70
VCCIO_SENSE AN16 VTT_SENSE <50> 100_0402_1%~D
A A
VSS_SENSE_VCCIO AN17 VTT_GND <50>

2
1 2
RC133 10_0402_1%~D

IVY-BRIDGE_BGA1023~D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Sandy Bridge (5/6)
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-7741
Date: Thursday, June 23, 2011 Sheet 10 of 56
5 4 3 2 1
5 4 3 2 1

+3.3V_ALW2 +PWR_SRC_S +1.5V_MEM QC3 +1.5V_CPU_VDDQ


AO4728L_SO8~D
8 1

10U_0603_6.3V6M~D
7 2

1
@

20K_0402_5%~D
6 3 1

CC135

RC73
RC74 RC72 5
100K_0402_5%~D 100K_0402_5%~D U1H
+1.5V_CPU_VDDQ Source

4
RUN_ON_CPU1.5VS3 2

2
3
+1.5V_CPU_VDDQ

DMN66D0LDW-7_SOT363-6~D

330K_0402_1%~D

0.1U_0603_50V7K~D
DMN66D0LDW-7_SOT363-6~D
A13 AM38
VSS[1] VSS[91]

1
QC4B

1K_0402_1%~D
1 A17 AM4
VSS[2] VSS[92]

1
RC143
1 2 QC4A 5 A21 AM42
<16,27,35,39,42,48> SIO_SLP_S3# VSS[3] VSS[93]

CC136
D RC82 0_0402_5%~D D
A25 AM45

RC84
VSS[4] VSS[94]
A28 AM48

4
2 VSS[5] VSS[95]
<40> CPU1.5V_S3_GATE 1 2 2 A33 AM58

2
@ RC79 0_0402_5%~D VSS[6] VSS[96]
A37 AN1

2
VSS[7] VSS[97]
+V_SM_VREF_CNT A40 AN21

1
VSS[8] VSS[98]
A45 AN25
POWER VSS[9] VSS[99]

1K_0402_1%~D
A49 AN28
VSS[10] VSS[100]

1
U1G A53 AN33
RUN_ON_CPU1.5VS3# <7,42> +V_SM_VREF_CNT VSS[11] VSS[101]
33A A9 AN36

RC78
VSS[12] VSS[102]
AA1 AN40
+VCC_GFXCORE VSS[13] VSS[103]
AA13 AN43
VSS[14] VSS[104]
AY43 AA50 AN47

2
SM_VREF VSS[15] VSS[105]
AA46 AA51 AN50

VREF
VAXG[1] VSS[16] VSS[106]
AB47 VAXG[2] AA52 VSS[17] VSS[107] AN54
AB50 +V_SM_VREF should AA53 AP10
VAXG[3] VSS[18] VSS[108]
AB51 VAXG[4] have 20 mil trace width AA55 VSS[19] VSS[109] AP51
AB52 VAXG[5] AA56 VSS[20] VSS[110] AP55
AB53 VAXG[6] AA8 VSS[21] VSS[111] AP7
AB55 VAXG[7] AB16 VSS[22] VSS[112] AR13
AB56
AB58
VAXG[8] 5A AB18
AB21
VSS[23] VSS[113] AR17
AR21
VAXG[9] VSS[24] VSS[114]
AB59 VAXG[10] AB48 VSS[25] VSS[115] AR41
AC61 +1.5V_CPU_VDDQ CC178 2 1 0.1U_0402_10V7K~D AB61 AR48
VAXG[11] VSS[26] VSS[116]
AD47 VAXG[12] AC10 VSS[27] VSS[117] AR61
AD48 VAXG[13] AC14 VSS[28] VSS[118] AR7
AD50 CC179 2 1 0.1U_0402_10V7K~D AC46 AT14
VAXG[14] VSS[29] VSS[119]
AD51 VAXG[15] VDDQ[1] AJ28 AC6 VSS[30] VSS[120] AT19

- 1.5V RAILS
AD52 VAXG[16] VDDQ[2] AJ33 AD17 VSS[31] VSS[121] AT36
AD53 AJ36 CC149 2 1 0.1U_0402_10V7K~D AD20 AT4
VAXG[17] VDDQ[3] VSS[32] VSS[122]
AD55 AJ40 AD4 AT45

C
AD56
AD58
VAXG[18]
VAXG[19]
VAXG[20]
VDDQ[4]
VDDQ[5]
VDDQ[6]
AL30
AL34 +1.5V_CPU_VDDQ CC150 2 1 0.1U_0402_10V7K~D +1.5V_MEM
AD61
AE13
VSS[33]
VSS[34]
VSS[35]
VSS VSS[123]
VSS[124]
VSS[125]
AT52
AT58
C
AD59 VAXG[21] VDDQ[7] AL38 AE8 VSS[36] VSS[126] AU1
AE46 VAXG[22] VDDQ[8] AL42 AF1 VSS[37] VSS[127] AU11
N45 VAXG[23] VDDQ[9] AM33 AF17 VSS[38] VSS[128] AU28
P47 VAXG[24] VDDQ[10] AM36 AF21 VSS[39] VSS[129] AU32
P48 VAXG[25] VDDQ[11] AM40 AF47 VSS[40] VSS[130] AU51
P50 VAXG[26] VDDQ[12] AN30 AF48 VSS[41] VSS[131] AU7

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

330U_D2_2VM_R6M~D
P51 VAXG[27] VDDQ[13] AN34 1 1 1 1 1 1 1 1 1 AF50 VSS[42] VSS[132] AV17
P52 AN38 AF51 AV21
VAXG[28] VDDQ[14] VSS[43] VSS[133]

CC181

CC180

CC161

CC162

CC163

CC164

CC165

CC166

CC167
P53 AR26 + AF52 AV22

DDR3
VAXG[29] VDDQ[15] VSS[44] VSS[134]
P55 AR28 AF53 AV34

GRAPHICS
VAXG[30] VDDQ[16] 2 2 2 2 2 2 2 2 VSS[45] VSS[135]
P56 AR30 AF55 AV40
VAXG[31] VDDQ[17] 2 VSS[46] VSS[136]
P61 AR32 AF56 AV48
VAXG[32] VDDQ[18] VSS[47] VSS[137]
T48 AR34 AF58 AV55
VAXG[33] VDDQ[19] VSS[48] VSS[138]
T58 AR36 AF59 AW13
VAXG[34] VDDQ[20] VSS[49] VSS[139]
T59 AR40 AG10 AW43
VAXG[35] VDDQ[21] VSS[50] VSS[140]
T61 AV41 AG14 AW61
VAXG[36] VDDQ[22] VSS[51] VSS[141]
U46 AW26 AG18 AW7
VAXG[37] VDDQ[23] VSS[52] VSS[142]
V47 BA40 AG47 AY14
VAXG[38] VDDQ[24] VSS[53] VSS[143]
V48 BB28 AG52 AY19
VAXG[39] VDDQ[25] VSS[54] VSS[144]
V50 BG33 AG61 AY30
VAXG[40] VDDQ[26] VSS[55] VSS[145]
V51 AG7 AY36
VAXG[41] VSS[56] VSS[146]

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D
V52 AH4 AY4
VAXG[42] VSS[57] VSS[147]
V53 1 1 1 1 1 1 1 1 1 1 AH58 AY41
VAXG[43] VSS[58] VSS[148]

CC250

CC251

CC252

CC253

CC254

CC255

CC256

CC257

CC258

CC259
V55 AJ13 AY45
VAXG[44] VSS[59] VSS[149]
V56 AJ16 AY49
VAXG[45] VSS[60] VSS[150]
V58 AJ20 AY55
VAXG[46] 2 2 2 2 2 2 2 2 2 2 VSS[61] VSS[151]
V59 AJ22 AY58
VAXG[47] VSS[62] VSS[152]
W50 AJ26 AY9
VAXG[48] VSS[63] VSS[153]
W51 AJ30 BA1
VAXG[49] VSS[64] VSS[154]
W52 AJ34 BA11
VAXG[50] VSS[65] VSS[155]
W53 AJ38 BA17
VAXG[51] VSS[66] VSS[156]
W55 AJ42 BA21
B VAXG[52] VSS[67] VSS[157] B
W56 AJ45 BA26
+VCC_GFXCORE VAXG[53] VSS[68] VSS[158]
W61 AJ48 BA32
VAXG[54] VSS[69] VSS[159]
Y48 AJ7 BA48
VAXG[55] VSS[70] VSS[160]
Y61 AK1 BA51
VAXG[56] VSS[71] VSS[161]
1

AK52 BB53
RC99 @RC76
@ RC76 VSS[72] VSS[162]
AL10 BC13
100_0402_1%~D +1.5V_CPU_VDDQ VSS[73] VSS[163]
100_0402_1%~D AL13 BC5
VSS[74] VSS[164]
1 2 AL17 BC57
VSS[75] VSS[165]
AL21 BD12
2

VSS[76] VSS[166]
QUIET RAILS

AM28 AL25 BD16


SENSE
LINES

VCCDQ[1] VSS[77] VSS[167]

1U_0402_6.3V6K~D
<51> VCC_AXG_SENSE F45 AN26 AL28 BD19
VAXG_SENSE VCCDQ[2] VSS[78] VSS[168]
<51> VSS_AXG_SENSE G45 1 AL33 BD23
VSSAXG_SENSE VSS[79] VSS[169]
AL36 BD27
VSS[80] VSS[170]

CC574
AL40 BD32
VSS[81] VSS[171]
1

AL43 BD36
RC100 2 VSS[82] VSS[172]
AL47 BD40
+1.8V_RUN VSS[83] VSS[173]
1.2A AL61 BD44
1.8V RAIL

100_0402_1%~D VSS[84] VSS[174]


AM13 BD48
VSS[85] VSS[175]
BB3 AM20 BD52
2

VCCPLL[1] VSS[86] VSS[176]


330U_D2_2.5VM_R6M~D

1 BC1 AM22 BD56


VCCPLL[2] VSS[87] VSS[177]
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1 1 BC4 AM26 BD8


VCCPLL[3] VSS[88] VSS[178]
CC176

+ AM30 BE5
VSS[89] VSS[179]
CC174

CC175

AM34 BG13
VSS[90] VSS[180]
2 2 2 BC43
+VCC_SA VDDQ_SENSE
BA43
VSS_SENSE_VDDQ
SENSE LINES

6A L17
VCCSA[1] IVY-BRIDGE_BGA1023~D
L21
VCCSA[2]
N16
VCCSA[3]
330U_D2_2VM_R6M~D

N20
VCCSA[4]
10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

N22
SA RAIL

A VCCSA[5] A
1 1 1 1 1 1 1 1 1 1 1 P17 VCCSA[6]
CC264

CC263

CC262

CC261

CC260

P20 VCCSA[7] VCCSA_SENSE U10 +VCCSA_SENSE <54>


CC172

CC171

CC170

CC169

CC168

CC183

+ R16 VCCSA[8]
R18 VCCSA[9]
2 2 2 2 2 2 2 2 2 2
R21
2 U15
VCCSA[10] DELL CONFIDENTIAL/PROPRIETARY
VCCSA VID

VCCSA[11] RC139 0_0402_5%~D


V16 VCCSA[12]
V17 VCCSA[13] VCCSA_VID[0] D48 1 2 VCCSA_VID_0 <54> Compal Electronics, Inc.
lines

V18 VCCSA[14] VCCSA_VID[1] D49 1 2 VCCSA_VID_1 <54>


V21 RC138 0_0402_5%~D Title
VCCSA[15]
W20 VCCSA[16] Sandy Bridge (6/6)
Size Document Number Rev
0.1
LA-7741
IVY-BRIDGE_BGA1023~D Date: Thursday, June 23, 2011 Sheet 11 of 56
5 4 3 2 1
5 4 3 2 1

+V_DDR_REFA_M3 1
RD7
2
0_0402_5%~D +DIMM1_VREF_DQ JDIMM1 H=4
+V_DDR_REF 1 2 +1.5V_MEM +1.5V_MEM 2-3A to 1 DIMMs/channel
RD1 0_0402_5%~D JDIMM1
1 VREF_DQ VSS 2
3 4 DDR_A_D4
VSS DQ4

2.2U_0603_6.3V6K~D

0.1U_0402_25V6K~D
DDR_A_D0 5 6 DDR_A_D5
DDR_A_D1 DQ0 DQ5 +1.5V_MEM
7 DQ1 VSS 8
1 1 9 10 DDR_A_DQS#0
VSS DQS0#

CD2
11 12 DDR_A_DQS0
DM0 DQS0

CD1
13 14
VSS VSS

1
DDR_A_D2 15 16 DDR_A_D6
2 2 DDR_A_D3 DQ2 DQ6 DDR_A_D7 RD27
17 18
D DQ3 DQ7 1K_0402_1%~D D
19 20
DDR_A_D8 VSS VSS DDR_A_D12
21 22
DDR_A_D9 DQ8 DQ12 DDR_A_D13
23 24

2
DQ9 DQ13
25 26
DDR_A_DQS#1 VSS VSS DDR3_DRAMRST#_R 1
27 28 <13> DDR3_DRAMRST#_R 2 DDR3_DRAMRST# <7>
DDR_A_DQS1 DQS1# DM1 DDR3_DRAMRST#_R RD28 1K_0402_1%~D
29 30
DQS1 RESET#
31 32
DDR_A_D10 VSS VSS DDR_A_D14
33 34
DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 36
DQ11 DQ15
Populate RD1, De-Populate RD7 for Intel DDR3 37
VSS VSS
38
DDR_A_D16 39 40 DDR_A_D20
VREFDQ multiple methods M1 DDR_A_D17 41
DQ16 DQ20
42 DDR_A_D21
Populate RD7, De-Populate RD1 for Intel DDR3 DQ17 DQ21
43 VSS VSS 44
VREFDQ multiple methods M3 DDR_A_DQS#2 45 46
DDR_A_DQS2 DQS2# DM2 @ RD29 1
47 DQS2 VSS 48 2 0_0402_5%~D
49 50 DDR_A_D22
DDR_A_D18 VSS DQ22 DDR_A_D23
51 DQ18 DQ23 52
DDR_A_D19 53 54 QD1
DQ19 VSS

D
All VREF traces should 55 56 DDR_A_D28 +DIMM0_1_VREF_CPU 3 1 BSS138_NL_SOT23-3 +V_DDR_REFA_M3
DDR_A_D24 VSS DQ28 DDR_A_D29
have 10 mil trace width 57 DQ24 DQ29 58
DDR_A_D25 59 60
DQ25 VSS DDR_A_DQS#3
61 62

G
2
VSS DQS3# DDR_A_DQS3
<8> DDR_A_DQS#[0..7] 63 DM3 DQS3 64
65 66 DDR_HVREF_RST
DDR_A_D26 VSS VSS DDR_A_D30 <7> DDR_HVREF_RST
<8> DDR_A_D[0..63] 67 DQ26 DQ30 68
DDR_A_D27 69 70 DDR_A_D31
DQ27 DQ31
<8> DDR_A_DQS[0..7] 71 VSS VSS 72

@ RD30 1 2 0_0402_5%~D
<8> DDR_A_MA[0..15]
DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA
<8> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <8>
75 VDD VDD 76
77 78 DDR_A_MA15 QD2
C NC A15 C

D
DDR_A_BS2 79 80 DDR_A_MA14 3 1 BSS138_NL_SOT23-3
<8> DDR_A_BS2 BA2 A14 +DIMM0_1_CA_CPU +V_DDR_REFB_M3
81 VDD VDD 82
DDR_A_MA12 83 84 DDR_A_MA11
DDR_A_MA9 A12/BC# A11 DDR_A_MA7
Layout Note: Note:

G
85 86

2
A9 A7
87 88
Place near JDIMM1 Check voltage tolerance of DDR_A_MA8 89
VDD VDD
90 DDR_A_MA6 DDR_HVREF_RST
A8 A6
VREF_DQ at the DIMM socket DDR_A_MA5 91 A5 A4 92 DDR_A_MA4
93 94
DDR_A_MA3 VDD VDD DDR_A_MA2
95
A3 A2
96 M3 Circuit (Processor Generated SO-DIMM VREF_DQ)
DDR_A_MA1 97 98 DDR_A_MA0
A1 A0
99 100
+1.5V_MEM M_CLK_DDR0 VDD VDD M_CLK_DDR1
<8> M_CLK_DDR0 101 102 M_CLK_DDR1 <8>
M_CLK_DDR#0 CK0 CK1 M_CLK_DDR#1
<8> M_CLK_DDR#0 103 104 M_CLK_DDR#1 <8>
CK0# CK1#
105 106
DDR_A_MA10 VDD VDD DDR_A_BS1
107 108 DDR_A_BS1 <8>
A10/AP BA1
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

DDR_A_BS0 109 110 DDR_A_RAS#


<8> DDR_A_BS0 BA0 RAS# DDR_A_RAS# <8>
1 1 1 1 111 112
DDR_A_WE# VDD VDD DDR_CS0_DIMMA#
<8> DDR_A_WE# 113 114 DDR_CS0_DIMMA# <8>
WE# S0#
CD3

CD4

CD5

CD6

DDR_A_CAS# 115 116 M_ODT0


<8> DDR_A_CAS# CAS# ODT0 M_ODT0 <8>
117 118
2 2 2 2 DDR_A_MA13 VDD VDD M_ODT1 +DIMM1_VREF_CA
119 120 M_ODT1 <8>
DDR_CS1_DIMMA# A13 ODT1
<8> DDR_CS1_DIMMA# 121 122
S1# NC
123 124
VDD VDD
125 126 2 1 +V_DDR_REF
TEST VREF_CA RD11 0_0402_5%~D
127 128
VSS VSS

2.2U_0603_6.3V6K~D

0.1U_0402_25V6K~D
DDR_A_D32 129 130 DDR_A_D36
DDR_A_D33 DQ32 DQ36 DDR_A_D37
131 132
DQ33 DQ37
133 134 1 1
VSS VSS

CD15

CD16
DDR_A_DQS#4 135 136
+1.5V_MEM DDR_A_DQS4 DQS4# DM4
137 138
DQS4 VSS DDR_A_D38
139 140
DDR_A_D34 VSS DQ38 DDR_A_D39 2 2
141 142
B DDR_A_D35 DQ34 DQ39 B
143 144
DQ35 VSS
10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

145 146 DDR_A_D44


DDR_A_D40 VSS DQ44 DDR_A_D45
147 148
DQ40 DQ45
330U_SX_2VY~D

1 DDR_A_D41 149 150


DQ41 VSS
@ CD13

1 1 1 1 1 1 1 151 152 DDR_A_DQS#5


VSS DQS5#
CD7

CD8

CD9

CD10

CD11

CD51

CD14

+ 153 154 DDR_A_DQS5


DM5 DQS5
155 156
DDR_A_D42 VSS VSS DDR_A_D46
157 158
2 2 2 2 2 2 2 2 DDR_A_D43 DQ42 DQ46 DDR_A_D47
159 160
DQ43 DQ47
161 162
DDR_A_D48 VSS VSS DDR_A_D52
163 164
DDR_A_D49 DQ48 DQ52 DDR_A_D53
165 166
DQ49 DQ53
167 168
DDR_A_DQS#6 VSS VSS
169 170
DDR_A_DQS6 DQS6# DM6
171 172
DQS6 VSS DDR_A_D54
173 174
DDR_A_D50 VSS DQ54 DDR_A_D55
175 176
DDR_A_D51 DQ50 DQ55
177 178
DQ51 VSS DDR_A_D60
Layout Note: 179
VSS DQ60
180
DDR_A_D56 181 182 DDR_A_D61
Place near JDIMM1.203,204 DDR_A_D57 183
DQ56 DQ61
184
DQ57 VSS DDR_A_DQS#7
185 186
VSS DQS7# DDR_A_DQS7
187 188
DM7 DQS7
189 190
DDR_A_D58 VSS VSS DDR_A_D62
191 192
DDR_A_D59 DQ58 DQ62 DDR_A_D63
193 194
DQ59 DQ63
195 196
RD21 VSS VSS
2 10K_0402_5%~D 197 198
+0.75V_DDR_VTT SA0 EVENT#
+3.3V_RUN 199 200 DDR_XDP_WAN_SMBDAT <13,15,27,34>
VDDSPD SDA
1 2 201 202 DDR_XDP_WAN_SMBCLK <13,15,27,34>
RD3 10K_0402_5%~D SA1 SCL
1 1 203 204 +0.75V_DDR_VTT
VTT VTT
0.1U_0402_25V6K~D

2.2U_0603_6.3V6K~D

+0.75V_DDR_VTT
CD22

A A
205 GND1 GND1 206
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD21

2 2
1 1 1 1
CD17

CD18

CD19

CD20

TYCO_2-2013022-2~D
2 2 2 2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DDRIII-SODIMM SLOT1
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-7741
Date: Thursday, June 23, 2011 Sheet 12 of 56
5 4 3 2 1
5 4 3 2 1

2-3A to 1 DIMMs/channel
+DIMM2_VREF_DQ +1.5V_MEM +1.5V_MEM
JDIMM2 CONN@
+V_DDR_REFB_M3 1 2 1 2
RD8 0_0402_5%~D VREF_DQ VSS DDR_B_D4
3 4
VSS DQ4
JDIMMB H=8

2.2U_0603_6.3V6K~D

0.1U_0402_25V6K~D
DDR_B_D0 5 6 DDR_B_D5
DDR_B_D1 DQ0 DQ5
+V_DDR_REF 1 2 7 DQ1 VSS 8
RD4 0_0402_5%~D 1 1 9 10 DDR_B_DQS#0
VSS DQS0#

CD24
11 12 DDR_B_DQS0
DM0 DQS0

CD23
13 VSS VSS 14
DDR_B_D2 15 16 DDR_B_D6
2 2 DDR_B_D3 DQ2 DQ6 DDR_B_D7
17 18
DQ3 DQ7
19 20
DDR_B_D8 VSS VSS DDR_B_D12
21 22
D DDR_B_D9 DQ8 DQ12 DDR_B_D13 D
23 24
DQ9 DQ13
25 26
DDR_B_DQS#1 VSS VSS
27 28
DDR_B_DQS1 DQS1# DM1 DDR3_DRAMRST#_R
29 30 DDR3_DRAMRST#_R <12>
DQS1 RESET#
Note: 31
VSS VSS
32
DDR_B_D10 33 34 DDR_B_D14
Check voltage tolerance of DDR_B_D11 35
DQ10 DQ14
36 DDR_B_D15
DQ11 DQ15
VREF_DQ at the DIMM socket 37
VSS VSS
38
DDR_B_D16 39 40 DDR_B_D20
DDR_B_D17 DQ16 DQ20 DDR_B_D21
41 42
DQ17 DQ21
43 44
DDR_B_DQS#2 VSS VSS
45 DQS2# DM2 46
DDR_B_DQS2 47 48
DQS2 VSS DDR_B_D22
49 VSS DQ22 50
Populate RD4, De-Populate RD8 for Intel DDR3 DDR_B_D18 51 52 DDR_B_D23
DDR_B_D19 DQ18 DQ23
VREFDQ multiple methods M1 53 DQ19 VSS 54
55 56 DDR_B_D28
Populate RD8, De-Populate RD4 for Intel DDR3 DDR_B_D24 VSS DQ28 DDR_B_D29
57 DQ24 DQ29 58
VREFDQ multiple methods M3 DDR_B_D25 59 60
DQ25 VSS DDR_B_DQS#3
61 VSS DQS3# 62
63 64 DDR_B_DQS3
DM3 DQS3
65 VSS VSS 66
DDR_B_D26 67 68 DDR_B_D30
DDR_B_D27 DQ26 DQ30 DDR_B_D31
<8> DDR_B_DQS#[0..7] 69 DQ27 DQ31 70
71 VSS VSS 72
<8> DDR_B_D[0..63]
All VREF traces should
have 10 mil trace width
DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB
<8> DDR_B_DQS[0..7] <8> DDR_CKE2_DIMMB CKE0 CKE1 DDR_CKE3_DIMMB <8>
75 VDD VDD 76
77 78 DDR_B_MA15
<8> DDR_B_MA[0..15] DDR_B_BS2 NC A15 DDR_B_MA14
<8> DDR_B_BS2 79 BA2 A14 80
81 VDD VDD 82
C DDR_B_MA12 DDR_B_MA11 C
83 A12/BC# A11 84
Layout Note: DDR_B_MA9 85 86 DDR_B_MA7
A9 A7
87 88
Place near JDIMM2 DDR_B_MA8 89
VDD VDD
90 DDR_B_MA6
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92
93 VDD VDD 94
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 98
A1 A0
99 100
M_CLK_DDR2 VDD VDD M_CLK_DDR3
<8> M_CLK_DDR2 101 102 M_CLK_DDR3 <8>
M_CLK_DDR#2 CK0 CK1 M_CLK_DDR#3
<8> M_CLK_DDR#2 103 104 M_CLK_DDR#3 <8>
+1.5V_MEM CK0# CK1#
105 106
DDR_B_MA10 VDD VDD DDR_B_BS1
107 108 DDR_B_BS1 <8>
DDR_B_BS0 A10/AP BA1 DDR_B_RAS#
<8> DDR_B_BS0 109 110
BA0 RAS# DDR_B_RAS# <8>
111 112
VDD VDD
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

DDR_B_WE# 113 114 DDR_CS2_DIMMB#


<8> DDR_B_WE# WE# S0# DDR_CS2_DIMMB# <8>
1 1 1 1 DDR_B_CAS# 115 116 M_ODT2
<8> DDR_B_CAS# CAS# ODT0 M_ODT2 <8>
117 118
VDD VDD +DIMM2_VREF_CA
CD25

CD26

CD27

CD28

DDR_B_MA13 119 120 M_ODT3


DDR_CS3_DIMMB# A13 ODT1 M_ODT3 <8>
<8> DDR_CS3_DIMMB# 121 122
2 2 2 2 S1# NC
123 124
VDD VDD
125 126 2 1 +V_DDR_REF
TEST VREF_CA RD15 0_0402_5%~D
127 128
VSS VSS

2.2U_0603_6.3V6K~D

0.1U_0402_25V6K~D
DDR_B_D32 129 130 DDR_B_D36
DDR_B_D33 DQ32 DQ36 DDR_B_D37
131 132
DQ33 DQ37
133 134 1 1
VSS VSS

CD38
DDR_B_DQS#4 135 136
DQS4# DM4

CD37
DDR_B_DQS4 137 138
+1.5V_MEM DQS4 VSS DDR_B_D38
139 140
DDR_B_D34 VSS DQ38 DDR_B_D39 2 2
141 142
DDR_B_D35 DQ34 DQ39
143 144
DQ35 VSS DDR_B_D44
145 146
VSS DQ44
10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

330U_SX_2VY~D

B DDR_B_D40 DDR_B_D45 B
147 148
DDR_B_D41 DQ40 DQ45
149 150
DQ41 VSS DDR_B_DQS#5
1 151 152
VSS DQS5#
@ CD35

1 1 1 1 1 1 1 153 154 DDR_B_DQS5


DM5 DQS5
CD29

CD30

CD31

CD32

CD33

CD34

CD36

+ 155 156
DDR_B_D42 VSS VSS DDR_B_D46
157 158
DDR_B_D43 DQ42 DQ46 DDR_B_D47
159 160
2 2 2 2 2 2 2 2 DQ43 DQ47
161 162
DDR_B_D48 VSS VSS DDR_B_D52
163 164
DDR_B_D49 DQ48 DQ52 DDR_B_D53
165 166
DQ49 DQ53
167 168
DDR_B_DQS#6 VSS VSS
169 170
DDR_B_DQS6 DQS6# DM6
171 172
DQS6 VSS DDR_B_D54
173 174
DDR_B_D50 VSS DQ54 DDR_B_D55
175 176
DDR_B_D51 DQ50 DQ55
177 178
DQ51 VSS DDR_B_D60
179 180
DDR_B_D56 VSS DQ60 DDR_B_D61
181 182
DDR_B_D57 DQ56 DQ61
Layout Note: 183
DQ57 VSS
184
185 186 DDR_B_DQS#7
Place near JDIMM2.203,204 187
VSS DQS7#
188 DDR_B_DQS7
DM7 DQS7
189 190
DDR_B_D58 VSS VSS DDR_B_D62
191 192
DDR_B_D59 DQ58 DQ62 DDR_B_D63
193 194
DQ59 DQ63
195 196
+3.3V_RUN VSS VSS
197 198
SA0 EVENT#
+3.3V_RUN 199 200 DDR_XDP_WAN_SMBDAT <12,15,27,34>
VDDSPD SDA
2 1 201 202 DDR_XDP_WAN_SMBCLK <12,15,27,34>
+0.75V_DDR_VTT RD5 10K_0402_5%~D SA1 SCL
+0.75V_DDR_VTT 203 204 +0.75V_DDR_VTT
VTT VTT
1
10K_0402_5%~D

0.1U_0402_25V6K~D
RD6

205 206
GND1 GND1
2.2U_0603_6.3V6K~D

1 1
CD43

A A
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD44
2

1 1 1 1 TYCO_2-2013297-2~D
2 2
CD39

CD40

CD41

CD42

2 2 2 2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DDRIII-SODIMM SLOT2
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.1
LA-7741
Date: Thursday, June 23, 2011 Sheet 13 of 56
5 4 3 2 1
5 4 3 2 1

CMOS_CLR1 CMOS setting PCH_AZ_SYNC is sampled


at the rising edge of RSMRST# pin. +1.05V_RUN +3.3V_ALW_PCH JXDP2 @

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
So signal should be PU to the ALWAYS rail. +1.05V_RUN
Shunt Clear CMOS 1 OBSFN_A0
1 1 2 OBSFN_A1

PXDP@

CH6

PXDP@

CH1
Open Keep CMOS +3.3V_ALW_PCH
3 GND
4 OBSDATA_A[0]
PXDP@ 5
2 2 RH284 0_0402_5%~D OBSDATA_A[1]
ME_CLR1 TPM setting 6 GND

D
PCH_AZ_SYNC_Q 3 1 PCH_AZ_SYNC RSMRST#_XDP 1 2 7
RH66 OBSDATA_A[2]
Shunt Clear ME RTC Registers 8 OBSDATA_A[3]
1K_0402_1%~D 1 2 QH7 CH1 clsoe to JXDP2 @ RH283 1K_0402_5%~D 9 GND
Open Keep ME RTC Registers RH31 1M_0402_5%~D SSM3K7002FU_SC70-3~D CH6 clsoe to JXDP2 2 1.05V_0.8V_PWROK_R

G
1 10

2
<40,51> 1.05V_0.8V_PWROK HOOK0
+5V_RUN 1 2 PCH_PWRBTN#_XDP 11

2
<7,16> SIO_PWRBTN#_R HOOK1
INTEL HDA_SYNC RH21 0_0402_5%~D 12 HOOK2
PXDP@ 13
+RTC_CELL PCH_AZ_SYNC isolation circuit +3.3V_ALW_PCH 14
HOOK3
HOOK4
15
HOOK5

1
+3.3V_ALW_PCH 16
VCCOBS_AB
1

RH282 @ SIO_PWRBTN#_R 2 1 RSMRST#_XDP 17


D
RH38 100K_0402_5%~D PXDP@ RH41 10K_0402_5%~D XDP_DBRESET# HOOK6 D
18
330K_0402_1%~D <7,16> XDP_DBRESET# HOOK7
19
PCH_JTAG_TDO GND
20

2
TDO
21
2

PCH_INTVRMEN PCH_JTAG_TDI TRSTn


22
PCH_RSMRST#_Q RSMRST#_XDP PCH_JTAG_TMS TDI
<16,41> PCH_RSMRST#_Q 1 2 23
TMS
1

PXDP@ RH24 1K_0402_1%~D 24 27


@ RH39
@RH39 TCK1 GND
On Die PLL VR is supplied by 25
GND GND
28
330K_0402_1%~D CH2 PCH_JTAG_TCK 26
1.5V when sampled high, 1.8 V 15P_0402_50V8J~D TCK0
when sampled low 2 1 PCH_RTCX1 MOLEX_52435-2671
2

1
1
INTVRMEN- Integrated SUS RH2
YH1 10M_0402_5%~D UH4A
1.1V VRM Enable 32.768KHZ_12.5PF_Q13FC1350000~D
* High - Enable Internal VRs CH3 A20 C38 LPC_LAD0

2
RTCX1 FWH0 / LAD0 LPC_LAD1 LPC_LAD0 <32,34,39,40>
15P_0402_50V8J~D A38
Low - Enable External VRs FWH1 / LAD1 LPC_LAD1 <32,34,39,40> +3.3V_RUN
2 1 PCH_RTCX2_R 1 2 PCH_RTCX2 C20 B37 LPC_LAD2

LPC
RTCX2 FWH2 / LAD2 LPC_LAD2 <32,34,39,40>
RH286 0_0402_5%~D C37 LPC_LAD3
FWH3 / LAD3 LPC_LAD3 <32,34,39,40>
1 2 PCH_RTCRST# D20
+RTC_CELL RTCRST#
RH22 20K_0402_5%~D D36 LPC_LFRAME# PCH_GPIO33 2 1
SRTCRST# FWH4 / LFRAME# LPC_LFRAME# <32,34,39,40>
1 2 G22 RH355 100K_0402_5%~D
RH23 20K_0402_5%~D SRTCRST# LPC_LDRQ0#
LDRQ0# E36 LPC_LDRQ0# <39>
1 2 INTRUDER# K22 K36 LPC_LDRQ1# IRQ_SERIRQ 2 1

RTC
INTRUDER# LDRQ1# / GPIO23 LPC_LDRQ1# <39>
RH11 1M_0402_5%~D RH28 8.2K_0402_5%~D
PCH_INTVRMEN C17 V5 IRQ_SERIRQ
INTVRMEN SERIRQ IRQ_SERIRQ <32,39,40>

1 1 2 2 1 1 2 2 SATA0RXN AM3 PSATA_PRX_DTX_N0_C <27>


PCH_AZ_BITCLK N34 AM1 BBS_BIT0_R 1 2
HDA_BCLK SATA0RXP PSATA_PRX_DTX_P0_C <27>
AP7 HDD RH52 4.7K_0402_5%~D

SATA 6G
PCH_AZ_SYNC SATA0TXN PSATA_PTX_DRX_N0_C <27> INTEL feedback 0302
L34 HDA_SYNC SATA0TXP AP5
@ @ PSATA_PTX_DRX_P0_C <27>
ME1 SHORT PADS~D CMOS1 SHORT PADS~D T10 AM10
<29> SPKR SPKR SATA1RXN SATA_ODD_PRX_DTX_N1_C <28>
1 2 1 2 SATA1RXP AM8 SATA_ODD_PRX_DTX_P1_C <28>
CH5 1U_0402_6.3V6K~D CH4 1U_0402_6.3V6K~D PCH_AZ_RST# K34 AP11 ODD/ E Module Bay
HDA_RST# SATA1TXN SATA_ODD_PTX_DRX_N1_C <28>
CMOS place near DIMM SATA1TXP AP10
SATA_ODD_PTX_DRX_P1_C <28>
C C
PCH_AZ_CODEC_SDIN0 E34 AD7 +3.3V_RUN
<29> PCH_AZ_CODEC_SDIN0 HDA_SDIN0 SATA2RXN
SATA2RXP AD5
<29> PCH_AZ_CODEC_SDOUT 1 2 PCH_AZ_SDOUT G34 HDA_SDIN1 SATA2TXN AH5
RH29 33_0402_5%~D AH4 SPKR 2 1
+3.3V_ALW_PCH SATA2TXP
<29> PCH_AZ_CODEC_SYNC 1 2 PCH_AZ_SYNC_Q C34 @ RH35 10K_0402_5%~D
RH26 33_0402_5%~D HDA_SDIN2
1 2 AB8

IHDA
SATA3RXN
<29> PCH_AZ_CODEC_RST# 1 2 PCH_AZ_RST# @ RH287 1K_0402_1%~D A34 AB10 No Reboot Strap
RH27 33_0402_5%~D HDA_SDIN3 SATA3RXP
SATA3TXN AF3
<29> PCH_AZ_CODEC_BITCLK 1 2 PCH_AZ_BITCLK AF1 Low = Default
PCH_AZ_SDOUT SATA3TXP
1 RH25 33_0402_5%~D <39> ME_FWP 1 2 A36 SPKR
HDA_SDO
RH50 1K_0402_1%~D Y7 ESATA_PRX_DTX_N4_C <37>
High = No Reboot

SATA
@CH101
@ CH101 SATA4RXN
SATA4RXP Y5 ESATA_PRX_DTX_P4_C <37>
27P_0402_50V8J~D +3.3V_ALW_PCH PCH_GPIO33
2
C36 HDA_DOCK_EN# / GPIO33 SATA4TXN AD3
ESATA_PTX_DRX_N4_C <37> E-SATA
SATA4TXP AD1
ESATA_PTX_DRX_P4_C <37>
1

USB30_SMI# N32
<28> USB30_SMI# HDA_DOCK_RST# / GPIO13
SATA5RXN Y3 SATA_PRX_DKTX_N5_C <38>
RH288 Y1
SATA5RXP SATA_PRX_DKTX_P5_C <38>
0_0603_5%~D AB3 DOCK
RH59 2 PCH_JTAG_TCK SATA5TXN SATA_PTX_DKRX_N5_C <38>
1 51_0402_1%~D J3 AB1
2

JTAG_TCK SATA5TXP SATA_PTX_DKRX_P5_C <38>


+3.3V_ALW_PCH_JTAG RH44 2 1 200_0402_1%~D PCH_JTAG_TMS H7 Y11 +1.05V_RUN
JTAG_TMS SATAICOMPO

JTAG
RH45 2 1 200_0402_1%~D PCH_JTAG_TDI K5 Y10 SATA_COMP 1 2
JTAG_TDI SATAICOMPI RH40 37.4_0402_1%~D
RH43 2 1 200_0402_1%~D PCH_JTAG_TDO H1 JTAG_TDO +1.05V_RUN
SATA3RCOMPO AB12
100_0402_1%~D

100_0402_1%~D

100_0402_1%~D

AB13 SATA3_COMP 1 2
SATA3COMPI
1

RH42 49.9_0402_1%~D
+3.3V_RUN
RH48

RH49

RH47

PCH_SPI_CLK T3 AH1 RBIAS_SATA3 1 2


SPI_CLK SATA3RBIAS RH46 750_0402_1%~D

1
PCH_SPI_CS0# Y14
2

SPI_CS0# RH30
PCH_SPI_CS1# T1 10K_0402_5%~D
SPI_CS1# SATA_ACT#
P3

SPI
SATALED# SATA_ACT# <43>

2
PCH_SPI_DO V4 V14 HDD_DET#_R 1 2
SPI_MOSI SATA0GP / GPIO21 HDD_DET# <27>
RH290 0_0402_5%~D
B B
PCH_SPI_DIN U3 P1 BBS_BIT0_R 1 3

S
SPI_MISO SATA1GP / GPIO19 PCH_SATA_MOD_EN# <40>

BD82PPSM-QNHN-A0_BGA989~D QH1 BSS138W-7-F_SOT323-3~D

G
2
<7,17> PCH_PLTRST#
BBS_BIT0 - BIOS BOOT STRAP BIT 0

+3.3V_M C746 @SPI +3.3V_M C745


0.1U_0402_25V6K~D 0.1U_0402_25V6K~D
1 2 1 2
1

200 MIL SO8 200 MIL SO8


1

@SPI R890
3.3K_0402_5%~D R891 @SPI
64Mb Flash ROM 3.3K_0402_5%~D 32Mb Flash ROM
U52 @SPI U53 @SPI
2

PCH_SPI_CS0# 1 2 PCH_SPI_CS0_R# 1 8 PCH_SPI_CS1# 1 2 PCH_SPI_CS1_R# 1 8


2

@SPI R935 0_0402_5%~D /CS VCC R936 0_0402_5%~D CS# VCC SPI_HOLD#
2 DO HOLD# 7
PCH_SPI_DIN 1 2 SPI_DIN64 2 7 SPI_HOLD# PCH_SPI_DIN 1 2 SPI_DIN32 3 6 SPI_CLK32 1 2 PCH_SPI_CLK
@SPI R894 33_0402_5%~D DO /HOLD R895 33_0402_5%~D WP# CLK SPI_DO32 R897 33_0402_5%~D
4 GND DI 5
SPI_WP#_SEL 1 2 SPI_WP#_SEL_R 3 6 SPI_CLK64 1 2 PCH_SPI_CLK
<39> SPI_WP#_SEL /WP CLK
@R898
@ R898 0_0402_5%~D @SPI R899 33_0402_5%~D W25Q32BVSSIG_SO8~D
4 5 SPI_DO64 1 2 PCH_SPI_DO
GND DIO @SPI R901 33_0402_5%~D SPI_WP#_SEL_R
1 2 PCH_SPI_DO
W25Q64CVSSIG_SO8~D R900 33_0402_5%~D

JTAA1 CONN@
SPI_DO32 1 1 2 2
3 4 4
SPI_CLK32 5
3 SPI_DIN32 TAA config R895,R897,R900 need change to 0 ohm SD02800008L
PCH_SPI_CLK PCH_SPI_CS0# 5 6 6
7 7 8 8
9 PCH_SPI_CS1_R#
10 10
A A
9
12P_0402_50V8J~D

1 +3.3V_M 11 11 12 12
C1204

13 G1 G2 14
15 G3 G4 16
2
RF team request 17 G5 G6 18
@
TYCO_5-1775013-4~D

Link Done DELL CONFIDENTIAL/PROPRIETARY


Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, PCH (1/8)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.1
LA-7741
Date: Thursday, June 23, 2011 Sheet 14 of 56
5 4 3 2 1
5 4 3 2 1

+3.3V_RUN

QH5A

2
DMN66D0LDW-7_SOT363-6~D

MEM_SMBCLK 6 1 DDR_XDP_WAN_SMBCLK <12,13,27,34>

5
MEM_SMBDATA 3 4
Follow DG0.9 Device DDR_XDP_WAN_SMBDAT <12,13,27,34>
QH5B
D down & Express/Mini UH4B DMN66D0LDW-7_SOT363-6~D D

card topology
PCIE_PRX_WANTX_N1 BG34
<34> PCIE_PRX_WANTX_N1 PCIE_PRX_WANTX_P1 PERN1 PCH_SMB_ALERT#
<34> PCIE_PRX_WANTX_P1 BJ34 E12
PCIE_PTX_WANRX_N1 PERP1 SMBALERT# / GPIO11 +3.3V_ALW_PCH
MiniWWAN (Mini Card 1)---> <34> PCIE_PTX_WANRX_N1
AV32
PETN1
PCIE_PTX_WANRX_P1 AU32 H14 MEM_SMBCLK
<34> PCIE_PTX_WANRX_P1 PETP1 SMBCLK
PCIE_PRX_WLANTX_N2 BE34 C9 MEM_SMBDATA SML1_SMBCLK 1 2
<34> PCIE_PRX_WLANTX_N2 PERN2 SMBDATA
PCIE_PRX_WLANTX_P2 BF34 RH298 2.2K_0402_5%~D
<34> PCIE_PRX_WLANTX_P2 PCIE_PTX_WLANRX_N2 PERP2 SML1_SMBDATA
MiniWLAN (Mini Card 2)---> <34> PCIE_PTX_WLANRX_N2
BB32
PETN2 1 2
PCIE_PTX_WLANRX_P2 AY32 RH299 2.2K_0402_5%~D
<34> PCIE_PTX_WLANRX_P2 PETP2 DDR_HVREF_RST_PCH
A12

SMBUS
PCIE_PRX_EXPTX_N3 SML0ALERT# / GPIO60 DDR_HVREF_RST_PCH <7> +3.3V_ALW_PCH
<35> PCIE_PRX_EXPTX_N3 BG36 PERN3
PCIE_PRX_EXPTX_P3 BJ36 C8 LAN_SMBCLK
<35> PCIE_PRX_EXPTX_P3 PERP3 SML0CLK LAN_SMBCLK <31>
EXPRESS Card---> PCIE_PTX_EXPRX_N3 AV34
<35> PCIE_PTX_EXPRX_N3 PCIE_PTX_EXPRX_P3 PETN3 LAN_SMBDATA DDR_HVREF_RST_PCH 2
AU34 PETP3 SML0DATA G12 LAN_SMBDATA <31> 1
<35> PCIE_PTX_EXPRX_P3 RH300 1K_0402_1%~D
PCIE_PRX_EMBTX_N4 BF36 PCH_GPIO74 2 1
<28> PCIE_PRX_EMBTX_N4 PCIE_PRX_EMBTX_P4 PERN4
BE36 RH301 10K_0402_5%~D
<28> PCIE_PRX_EMBTX_P4 PERP4
E3 Module Bay---> PCIE_PTX_EMBRX_N4 AY34 C13 PCH_GPIO74 MEM_SMBCLK 2 1
<28> PCIE_PTX_EMBRX_N4 PCIE_PTX_EMBRX_P4 PETN4 SML1ALERT# / PCHHOT# / GPIO74 RH302 2.2K_0402_5%~D
BB34 PETP4
<28> PCIE_PTX_EMBRX_P4 SML1_SMBCLK MEM_SMBDATA
SML1CLK / GPIO58 E14 2 1
PCIE_PRX_WPANTX_N5 SML1_SMBCLK <40> RH303 2.2K_0402_5%~D
BG37

PCI-E*
<34> PCIE_PRX_WPANTX_N5 PCIE_PRX_WPANTX_P5 PERN5 SML1_SMBDATA PCH_SMB_ALERT#
1/2vMINI CARD-3 PCIE <34> PCIE_PRX_WPANTX_P5 BH37 PERP5 SML1DATA / GPIO75 M16 SML1_SMBDATA <40> 2 1
PCIE_PTX_WPANRX_N5 AY36 RH304 10K_0402_5%~D
(Mini Card 3)---> <34> PCIE_PTX_WPANRX_N5 PCIE_PTX_WPANRX_P5 BB36
PETN5 PEG_A_CLKRQ# 2 1
<34> PCIE_PTX_WPANRX_P5 PETP5 RH80 10K_0402_5%~D
PCIE_PRX_MMITX_N6 BJ38
<33> PCIE_PRX_MMITX_N6 PERN6
PCIE_PRX_MMITX_P6 BG38
<33> PCIE_PRX_MMITX_P6 PCIE_PTX_MMIRX_N6 PERP6 PCH_CL_CLK1 +3.3V_LAN
MMI ---> AU36 M7 PCH_CL_CLK1 <34>

Controller
<33> PCIE_PTX_MMIRX_N6 PCIE_PTX_MMIRX_P6 PETN6 CL_CLK1
AV36 PETP6
C <33> PCIE_PTX_MMIRX_P6 C
PCIE_PRX_GLANTX_N7 BG40 T11 PCH_CL_DATA1 LAN_SMBCLK 2 1

Link
<31> PCIE_PRX_GLANTX_N7 PCIE_PRX_GLANTX_P7 PERN7 CL_DATA1 PCH_CL_DATA1 <34>
BJ40 RH305 2.2K_0402_5%~D
<31> PCIE_PRX_GLANTX_P7 PCIE_PTX_GLANRX_N7 PERP7 LAN_SMBDATA
10/100/1G LAN ---> <31> PCIE_PTX_GLANRX_N7 AY40 PETN7 2 1
PCIE_PTX_GLANRX_P7 BB40 P10 PCH_CL_RST1# RH306 2.2K_0402_5%~D
<31> PCIE_PTX_GLANRX_P7 PETP7 CL_RST1# PCH_CL_RST1# <34>
BE38 PERN8
BC38
PERP8 CLK_BUF_DMI#
AW38 1 2
PETN8 CLK_BUF_DMI RH74 1
AY38 2 10K_0402_5%~D
PETP8 RH75 10K_0402_5%~D
M10 PEG_A_CLKRQ#
PEG_A_CLKRQ# / GPIO47 CLK_BUF_BCLK
Y40 1 2
<34> CLK_PCIE_MINI1# CLKOUT_PCIE0N RH91 10K_0402_5%~D
Y39
<34> CLK_PCIE_MINI1 CLKOUT_PCIE0P
MiniWWAN (Mini Card 1)---> +3.3V_ALW_PCH 2 1 CLKOUT_PEG_A_N
AB37
RH81 10K_0402_5%~D MINI1CLK_REQ# J2 AB38
<34> MINI1CLK_REQ# PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P

CLOCKS
CLK_BUF_DOT96# 1 2
CLK_BUF_DOT96 RH76 1 2 10K_0402_5%~D
AB49 AV22 CLK_CPU_DMI# RH77 10K_0402_5%~D
<31> CLK_PCIE_LAN# CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI CLK_CPU_DMI# <7>
AB47 AU22
<31> CLK_PCIE_LAN CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI <7> CLK_BUF_CKSSCD#
10/100/1G LAN ---> 1 2
LANCLK_REQ# M1 CLK_BUF_CKSSCD RH78 1 2 10K_0402_5%~D
<31> LANCLK_REQ# PCIECLKRQ1# / GPIO18
AM12 RH79 10K_0402_5%~D
CLKOUT_DP_N
AM13
CLKOUT_DP_P CLK_PCH_14M
AA48 1 2
<33> CLK_PCIE_MMI# CLKOUT_PCIE2N
MMI Card---> <33> CLK_PCIE_MMI
AA47
CLKOUT_PCIE2P
RH183 10K_0402_5%~D
1 2 BF18 CLK_BUF_DMI#
+3.3V_RUN CLKIN_DMI_N
RH87 10K_0402_5%~D MMICLK_REQ# V10 BE18 CLK_BUF_DMI
<33> MMICLK_REQ# PCIECLKRQ2# / GPIO20 CLKIN_DMI_P

Y37 BJ30 CLK_BUF_BCLK CLOCK TERMINATION for FCIM and need close to PCH
<34> CLK_PCIE_MINI3# CLKOUT_PCIE3N CLKIN_GND1_N CLK_BUF_BCLK
B
MiniWPAN (Mini Card 3)---> <34> CLK_PCIE_MINI3 Y36
CLKOUT_PCIE3P CLKIN_GND1_P
BG30
B
+3.3V_ALW_PCH 2 1
RH152 10K_0402_5%~D MINI3CLK_REQ# A8 CLK_PCI_TPM_TCM
<34> MINI3CLK_REQ# PCIECLKRQ3# / GPIO25 CLK_BUF_DOT96# CLK_SIO_14M
G24
CLKIN_DOT_96N CLK_BUF_DOT96 PCLK_80H
E24
CLKIN_DOT_96P
<35> CLK_PCIE_EXP# Y43 1 1 1
CLKOUT_PCIE4N

27P_0402_50V8J~D

27P_0402_50V8J~D

27P_0402_50V8J~D
Express card---> <35> CLK_PCIE_EXP Y45
CLKOUT_PCIE4P

CH113 @

CH111 @

CH112 @
2 1 AK7 CLK_BUF_CKSSCD# RF request
+3.3V_ALW_PCH CLKIN_SATA_N
RH94 10K_0402_5%~D EXPCLK_REQ# L12 AK5 CLK_BUF_CKSSCD
<35> EXPCLK_REQ# PCIECLKRQ4# / GPIO26 CLKIN_SATA_P 2 2 2

V45 K45 CLK_PCH_14M


<34> CLK_PCIE_MINI2# CLKOUT_PCIE5N REFCLK14IN
<34> CLK_PCIE_MINI2 V46
CLKOUT_PCIE5P
MiniWLAN (Mini Card 2)---> +3.3V_ALW_PCH 2 1
RH97 10K_0402_5%~D MINI2CLK_REQ# L14 H45 CLK_PCI_LOOPBACK
<34> MINI2CLK_REQ# PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_LOOPBACK <17>

AB42 V47 XTAL25_IN 2 1


CLKOUT_PEG_B_N XTAL25_IN XTAL25_OUT RH309 0_0402_5%~D
AB40 V49
CLKOUT_PEG_B_P XTAL25_OUT

1
1 2 PEG_B_CLKRQ# E6 RH99
+3.3V_ALW_PCH PEG_B_CLKRQ# / GPIO56
RH98 10K_0402_5%~D 1M_0402_5%~D
Y47 +XCLK_RCOMP 1 2
XCLK_RCOMP +1.05V_RUN
V40 RH100 90.9_0402_1%~D YH2

2
CLKOUT_PCIE6N
V42 3 1
CLKOUT_PCIE6P OUT IN

12P_0402_50V8J~D

12P_0402_50V8J~D
T13 4 2
PCIECLKRQ6# / GPIO45 GND GND
2 2
V38 K43 PCI_TPM_TCM RH311 2 1 22_0402_5%~D 25MHZ_10PF_Q22FA2380049900~D

CH18

CH19
<28> CLK_PCIE_EMB# CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64 CLK_PCI_TPM_TCM <32>
eModule Bay---> V37
FLEX CLOCKS

<28> CLK_PCIE_EMB CLKOUT_PCIE7P


2 1 F47 SIO_14M RH313 2 1 22_0402_5%~D
+3.3V_ALW_PCH CLKOUTFLEX1 / GPIO65 CLK_SIO_14M <39> 1 1
RH104 10K_0402_5%~D EMBCLK_REQ# K12
<28> EMBCLK_REQ# PCIECLKRQ7# / GPIO46 CLK_80H
H47 RH314 2 1 22_0402_5%~D
A CLKOUTFLEX2 / GPIO66 PCLK_80H <34> A
<7> CLK_CPU_ITP# AK14 CLKOUT_ITPXDP_N
AK13 K49 JETWAY_14M @ RH315 2 1 22_0402_5%~D
<7> CLK_CPU_ITP CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67 JETWAY_CLK14M <32>

BD82PPSM-QNHN-A0_BGA989~D
DELL CONFIDENTIAL/PROPRIETARY
PCIE REQ power rail:
Compal Electronics, Inc.
suspend: 0 3 4 5 6 7 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
core: 1 2 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, PCH (2/8)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.1
LA-7741
Date: Thursday, June 23, 2011 Sheet 15 of 56
5 4 3 2 1
5 4 3 2 1

1 2 PCH_CRT_BLU
+3.3V_ALW_PCH RH131 150_0402_1%~D +3.3V_RUN
1 2 PCH_CRT_GRN
RH132 150_0402_1%~D

2.2K_0402_5%~D

2.2K_0402_5%~D
1 2 PCH_CRT_RED

1
RH133 150_0402_1%~D

RH316

RH317
1 2 SUS_STAT#/LPCPD# 1 2 ENVDD_PCH
@ RH318 10K_0402_5%~D RH134 100K_0402_5%~D

1 2 ME_SUS_PWR_ACK

2
RH144 10K_0402_5%~D PCH_DPWROK 1 2 PCH_RSMRST#_R
RH113 0_0402_5%~D
1 2 PCH_PCIE_WAKE# PCH_CRT_DDC_CLK
D PCH_CRT_DDC_CLK <24> D
RH142 10K_0402_5%~D DSWODVREN - On Die DSW VR Enable
1 2 SIO_SLP_LAN# RESET_OUT# 1 2 SYS_PWROK Enabled (DEFAULT) PCH_CRT_DDC_DAT
PCH_CRT_DDC_DAT <24>
@ RH319 10K_0402_5%~D @ RH321 0_0402_5%~D
HIGH: RH127 STUFFED,
1 2 PCH_RI# RH129 UNSTUFFED
RH140 10K_0402_5%~D

ME_SUS_PWR_ACK_R 1 2 SUSACK#_R Disabled


RH323 0_0402_5%~D
LOW: RH129 STUFFED,
RH127 UNSTUFFED
+3.3V_RUN
+3.3V_RUN
PCH_RSMRST#_Q 1 2
1 2 CLKRUN# @ RH322 10K_0402_5%~D PCH_SDVO_CTRLCLK 2 1
RH137 8.2K_0402_5%~D RH351 2.2K_0402_5%~D
PCH_SDVO_CTRLDATA 2 1
RH352 2.2K_0402_5%~D

UH4C

UH4D
DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0
<6> DMI_CTX_PRX_N0 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N0 <6>
DMI_CTX_PRX_N1 BE20 AY14 FDI_CTX_PRX_N1 PANEL_BKEN_PCH J47 AP43
<6> DMI_CTX_PRX_N1 DMI1RXN FDI_RXN1 FDI_CTX_PRX_N1 <6> <23> PANEL_BKEN_PCH L_BKLTEN SDVO_TVCLKINN
DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2 ENVDD_PCH M45 AP45
<6> DMI_CTX_PRX_N2 DMI2RXN FDI_RXN2 FDI_CTX_PRX_N2 <6> <23,39> ENVDD_PCH L_VDD_EN SDVO_TVCLKINP
DMI_CTX_PRX_N3 BG20 BH13 FDI_CTX_PRX_N3
<6> DMI_CTX_PRX_N3 DMI3RXN FDI_RXN3 FDI_CTX_PRX_N3 <6>
BC12 FDI_CTX_PRX_N4 BIA_PWM_PCH P45 AM42
FDI_RXN4 FDI_CTX_PRX_N4 <6> <23> BIA_PWM_PCH L_BKLTCTL SDVO_STALLN
DMI_CTX_PRX_P0 BE24 BJ12 FDI_CTX_PRX_N5 AM40
<6> DMI_CTX_PRX_P0 DMI0RXP FDI_RXN5 FDI_CTX_PRX_N5 <6> SDVO_STALLP
DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6 LDDC_CLK_PCH T40
C <6> DMI_CTX_PRX_P1 DMI1RXP FDI_RXN6 FDI_CTX_PRX_N6 <6> <23> LDDC_CLK_PCH L_DDC_CLK C
DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7 LDDC_DATA_PCH K47 AP39
<6> DMI_CTX_PRX_P2 DMI2RXP FDI_RXN7 FDI_CTX_PRX_N7 <6> <23> LDDC_DATA_PCH L_DDC_DATA SDVO_INTN
DMI_CTX_PRX_P3 BJ20 AP40
<6> DMI_CTX_PRX_P3 DMI3RXP SDVO_INTP
BG14 FDI_CTX_PRX_P0 T45
FDI_RXP0 FDI_CTX_PRX_P0 <6> L_CTRL_CLK
DMI_CRX_PTX_N0 AW24 BB14 FDI_CTX_PRX_P1 P39
<6> DMI_CRX_PTX_N0 DMI0TXN FDI_RXP1 FDI_CTX_PRX_P1 <6> L_CTRL_DATA
DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2
<6> DMI_CRX_PTX_N1 DMI1TXN FDI_RXP2 FDI_CTX_PRX_P2 <6>
DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3 1 2 LVD_IBG AF37 P38 PCH_SDVO_CTRLCLK PCH_SDVO_CTRLCLK <25>
<6> DMI_CRX_PTX_N2 DMI2TXN FDI_RXP3 FDI_CTX_PRX_P3 <6> LVD_IBG SDVO_CTRLCLK
DMI_CRX_PTX_N3 AV18 BE12 FDI_CTX_PRX_P4 RH344 2.37K_0402_1%~D AF36 M39 PCH_SDVO_CTRLDATA
<6> DMI_CRX_PTX_N3 DMI3TXN FDI_RXP4 FDI_CTX_PRX_P4 <6> LVD_VBG SDVO_CTRLDATA PCH_SDVO_CTRLDATA <25>
BG12 FDI_CTX_PRX_P5 Minimum speacing of 20mils for LVD_IBG
DMI

DMI_CRX_PTX_P0 AY24
FDI FDI_RXP5
BJ10 FDI_CTX_PRX_P6
FDI_CTX_PRX_P5 <6>
AE48
<6> DMI_CRX_PTX_P0 DMI0TXP FDI_RXP6 FDI_CTX_PRX_P6 <6> LVD_VREFH
DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7 AE47 AT49
<6> DMI_CRX_PTX_P1 DMI1TXP FDI_RXP7 FDI_CTX_PRX_P7 <6> LVD_VREFL DDPB_AUXN
DMI_CRX_PTX_P2 AY18 AT47
<6> DMI_CRX_PTX_P2 DMI2TXP DDPB_AUXP
DMI_CRX_PTX_P3 AU18 AT40
<6> DMI_CRX_PTX_P3 DMI3TXP DDPB_HPD HDMIB_PCH_HPD <25>
AW16 FDI_INT LCD_ACLK-_PCH AK39
+1.05V_RUN FDI_INT FDI_INT <6> <23> LCD_ACLK-_PCH LVDSA_CLK#
LCD_ACLK+_PCH AK40 AV42

LVDS
<23> LCD_ACLK+_PCH LVDSA_CLK DDPB_0N TMDSB_PCH_N2 <25>
BJ24 AV12 FDI_FSYNC0 AV40
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 <6> DDPB_0P TMDSB_PCH_P2 <25>
LCD_A0-_PCH AN48 AV45
<23> LCD_A0-_PCH LVDSA_DATA#0 DDPB_1N TMDSB_PCH_N1 <25>
1 2 DMI_COMP_R BG25 BC10 FDI_FSYNC1 LCD_A1-_PCH AM47 AV46
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 <6> <23> LCD_A1-_PCH LVDSA_DATA#1 DDPB_1P TMDSB_PCH_P1 <25>
RH111 49.9_0402_1%~D LCD_A2-_PCH AK47 AU48

Digital Display Interface