IES IPS ACADEMY

DEPARTMENT OF ELECTRONICS & COMMUNICATION

Name: Branch: EC Year: IV
Subject: VLSI Design Course: BE Semester: VII
Subject Code: EC705
EXPERIMENT- 5

Aim: - Design CMOS logic using EDA for 3 input NAND and NOR gate.

Theory: -

NAND gate:

This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The
outputs of all NAND gates are high if any of the inputs are low. The symbol is an AND
gate with a small circle on the output. The small circle represents inversion.

Fig5.1

here is the schematic diagram for a CMOS NAND gate:

Fig5.2

Notice how transistors Q1 and Q3 resemble the series-connected complementary pair from
the inverter circuit. Both are controlled by the same input signal (input A), the upper
transistor turning off and the lower transistor turning on when the input is "high" (1), and
vice versa. Notice also how transistors Q 2 and Q4 are similarly controlled by the same
input signal (input B), and how they will also exhibit the same on/off behavior for the
same input logic levels. The upper transistors of both pairs (Q 1 and Q2) have their source
and drain terminals paralleled, while the lower transistors (Q 3 and Q4) are series-
connected. What this means is that the output will go "high" (1) if either top transistor
saturates, and will go "low" (0) only if both lower transistors saturate. The following
sequence of illustrations shows the behavior of this NAND gate for all four possibilities
of input logic levels (00, 01, 10, and 11):

Fig5.3
NOR gate:

This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The
outputs of all NOR gates are low if any of the inputs are high.
The symbol is an OR gate with a small circle on the output. The small circle represents
inversion.

Fig5.4

A CMOS NOR gate circuit uses four MOSFETs just like the NAND gate, except that its
transistors are differently arranged. Instead of two paralleled sourcing (upper) transistors
connected to Vdd and two series-connected sinking (lower) transistors connected to
ground, the NOR gate uses two series-connected sourcing transistors and two parallel-
connected sinking transistors like this:

Fig5.5

As with the NAND gate, transistors Q 1 and Q3 work as a complementary pair, as do

transistors Q2 and Q4. Each pair is controlled by a single input signal. If either input A or
input B are "high" (1), at least one of the lower transistors (Q 3 or Q4) will be saturated,
thus making the output "low" (0). Only in the event of both inputs being "low" (0) will
both lower transistors be in cutoff mode and both upper transistors be saturated, the
conditions necessary for the output to go "high" (1). This behavior, of course, defines the
NOR logic function.
Steps to perform experiment:-

1. Draw the schematic of NOR and NAND GATE in S-edit window.

2. Generate the T-spice code for the Schematic drawn, by clicking on T button.
3. Insert the necessary commands like File, Analysis, Output etc.
4. Run the code using Run Simulation button.
5. Analyse the generated waveform

SCHEMATIC FOR 3 INPUTS NOR GATE:

T-SPICE CODE

* SPICE netlist written by S-Edit Win32 Demo 9.12

* Written on Feb 15, 2014 at 10:35:04
* Waveform probing commands
.probe
.options probefilename="nor.dat"
+ probesdbfile="C:\Program Files\Tanner EDA\Demo\T-Spice\tutorial\schematic\nor.sdb"
+ probetopmodule="Module0"

* Main circuit: Module0

M1 out B Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M2 out A Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M3 out C Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M4 N9 B N20 N20 PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M5 N20 A Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M6 out C N9 N9 PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
v7 Vdd Gnd 5.0
v8 B Gnd pulse(0.0 5.0 0 10n 10n 100n 200n)
v9 A Gnd pulse(0.0 5.0 0 10n 10n 100n 200n)
v10 C Gnd pulse(0.0 5.0 0 10n 10n 100n 200n)
.include "C:\Program Files\Tanner EDA\Demo\T-Spice\tutorial\schematic\ml5_20.md"
.tran 50n 1000n start=0
.print tran v(A) v(B) v(C) v(OUT)
* End of main circuit: Module0

TSPICE SIMULATION STATUS

T-Spice - Tanner SPICE

Version Demo 9.12
Product Release ID: T-Spice Win32 Demo 9.12.20040112.04:26:10
Copyright (c) 1993-2004 Tanner Research, Inc.
Parsing "C:\Program Files\Tanner EDA\Demo\T-Spice\tutorial\schematic\Module0.sp"
Including "C:\Program Files\Tanner EDA\Demo\T-Spice\tutorial\schematic\ml5_20.md"
Probing options:
probefilename = nor.dat
probesdbname = C:\Program Files\Tanner EDA\Demo\T-Spice\tutorial\schematic\nor.sdb
probetopmodule = Module0

Device and node counts:

MOSFETs - 6 MOSFET geometries - 2
BJTs - 0 JFETs - 0
MESFETs - 0 Diodes - 0
Capacitors - 0 Resistors - 0
 Inductors - 0 Mutual inductors - 0
Transmission lines - 0 Coupled transmission lines - 0
Voltage sources - 4 Current sources - 0
VCVS - 0 VCCS - 0
CCVS - 0 CCCS - 0
V-control switch - 0 I-control switch - 0
Macro devices - 0 External C model instances - 0
Subcircuits - 0 Subcircuit instances - 0
Independent nodes - 3 Boundary nodes - 5
Total nodes - 8

Warning : Negative mos conductance for device M1

v(d), v(g), v(s), v(b) = 0.000000e+000 0.000000e+000 0.000000e+000
0.000000e+000
vds, vgs, vbs = 0.000000e+000 -0.000000e+000 -0.000000e+000
gds, gm, gmbs = -1.137440e-001 9.489429e-013 -9.489493e-013
ids = -1.137440e-013

Warning : Negative mos conductance for device M2

v(d), v(g), v(s), v(b) = 0.000000e+000 0.000000e+000 0.000000e+000
0.000000e+000
vds, vgs, vbs = 0.000000e+000 -0.000000e+000 -0.000000e+000
gds, gm, gmbs = -1.137440e-001 9.489429e-013 -9.489493e-013
ids = -1.137440e-013

Warning : Negative mos conductance for device M3

v(d), v(g), v(s), v(b) = 0.000000e+000 0.000000e+000 0.000000e+000
0.000000e+000
vds, vgs, vbs = 0.000000e+000 -0.000000e+000 -0.000000e+000
gds, gm, gmbs = -1.137440e-001 9.489429e-013 -9.489493e-013
ids = -1.137440e-013

Warning : Negative mos conductance for device M6

v(d), v(g), v(s), v(b) = 4.975022e+000 0.000000e+000 4.977408e+000
4.977408e+000
vds, vgs, vbs = -2.386422e-003 -4.977408e+000 0.000000e+000
gds, gm, gmbs = 8.276671e-001 -0.000000e+000 -8.276671e-001
ids = -0.000000e+000

Warning : Negative mos conductance for device M5

v(d), v(g), v(s), v(b) = 4.978223e+000 0.000000e+000 5.000000e+000
5.000000e+000
vds, vgs, vbs = -2.177651e-002 -5.000000e+000 0.000000e+000
gds, gm, gmbs = 7.530319e+000 -0.000000e+000 -7.530319e+000
ids = -0.000000e+000
Warning : Disabling printout of duplicate warning messages.
: Use '.options maxmsg=0' to view all warnings,
: or increase maxmsg from 5 to view more messages.

Conventional DC operating point computation failed.

Gmin stepping failed
Final gmin value = 1e-006
Pseudotransient analysis succeeded

* SIMULATION STATISTICS:
* DC operating point
* Total DC operating points =1
* Total Newton iterations = 341
* Total Current evaluations = 3831
* Transient analysis
* Transient timesteps = 158
* Successful timesteps = 148
* Failed timesteps = 10
* Newton non-convergence failures = 10
* Delta voltage (dv) failures =0
* Newton iterations = 525
* Successful Newton iterations = 415
* Failed Newton iterations = 110
* Average Newton iterations/timestep = 3.323
* Average Newton iterations/success = 2.804
* Current evaluations = 1475
* Matrix statistics: OP TRAN
* Matrix factors 341 525
* Matrix solves 341 525
* Size 3 3
* Initial elements 7 7
* Final elements 7 7
* Fill-ins 0 0
* Initial density 77.78% 77.78%
* Final density 77.78% 77.78%
* Total matrix factorizations = 866
* Total matrix-vector solves = 866
* Total matrix solve time (seconds) = 0
* T-Spice process times
* Newton solver 1.31 seconds
* Current evaluations 0.75 seconds
* Jacobian construction 0.56 seconds
* Linear solver 0.00 seconds
Parsing 0.02 seconds
Setup 0.00 seconds
DC operating point 0.86 seconds
Transient Analysis 0.47 seconds
Overhead 0.00 seconds
-----------------------------------------
Total 1.34 seconds

Simulation completed with 6 Warnings

W –EDIT WAVEFORM VIEWER

SCHEMATIC FOR 3 INPUT NAND GATE

T-SPICE CODE

* SPICE netlist written by S-Edit Win32 Demo 9.12

* Written on Feb 15, 2014 at 11:03:19
* Waveform probing commands
.probe
.options probefilename="nand.dat"
+ probesdbfile="C:\Program Files\Tanner EDA\Demo\T-Spice\tutorial\schematic\nand.sdb"
+ probetopmodule="Module0"

* Main circuit: Module0

M1 out A N4 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M2 N4 B N5 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M3 N5 C Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M4 out C Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M5 out B Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M6 out A Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
v7 Vdd Gnd 5.0
v8 A Gnd pulse(0.0 5.0 0 10n 10n 100n 200n)
v9 B Gnd pulse(0.0 5.0 0 10n 10n 100n 200n)
v10 C Gnd pulse(0.0 5.0 0 10n 10n 100n 200n)
.include "C:\Program Files\Tanner EDA\Demo\T-Spice\tutorial\schematic\ml5_20.md"
.tran 50N 1000N start=0
.print tran v(A) v(B) v(C) v(OUT)
* End of main circuit: Module0
TSPICE SIMULATION STATUS

T-Spice - Tanner SPICE

Version Demo 9.12
Product Release ID: T-Spice Win32 Demo 9.12.20040112.04:26:10
Copyright (c) 1993-2004 Tanner Research, Inc.
Parsing "C:\Program Files\Tanner EDA\Demo\T-Spice\tutorial\schematic\Module0.sp"
Including "C:\Program Files\Tanner EDA\Demo\T-Spice\tutorial\schematic\ml5_20.md"
Probing options:
probefilename = nand.dat
probesdbname = C:\Program Files\Tanner EDA\Demo\T-Spice\tutorial\schematic\nand.sdb
probetopmodule = Module0
Device and node counts:
MOSFETs - 6 MOSFET geometries - 2
BJTs - 0 JFETs - 0
MESFETs - 0 Diodes - 0
Capacitors - 0 Resistors - 0
Inductors - 0 Mutual inductors - 0
Transmission lines - 0 Coupled transmission lines - 0
Voltage sources - 4 Current sources - 0
VCVS - 0 VCCS - 0
CCVS - 0 CCCS - 0
V-control switch - 0 I-control switch - 0
Macro devices - 0 External C model instances - 0
Subcircuits - 0 Subcircuit instances - 0
Independent nodes - 3 Boundary nodes - 5
Total nodes - 8
Warning : Negative mos conductance for device M2
v(d), v(g), v(s), v(b) = 0.000000e+000 0.000000e+000 0.000000e+000
0.000000e+000
vds, vgs, vbs = 0.000000e+000 -0.000000e+000 -0.000000e+000
gds, gm, gmbs = -1.137440e-001 9.489429e-013 -9.489493e-013
ids = -1.137440e-013
Warning : Negative mos conductance for device M3
v(d), v(g), v(s), v(b) = 0.000000e+000 0.000000e+000 0.000000e+000
0.000000e+000
vds, vgs, vbs = 0.000000e+000 -0.000000e+000 -0.000000e+000
gds, gm, gmbs = -1.137440e-001 9.489429e-013 -9.489493e-013
ids = -1.137440e-013
Conventional DC operating point computation failed.
Gmin stepping failed
Final gmin value = 1e-006
Warning : Negative mos conductance for device M1
v(d), v(g), v(s), v(b) = 0.000000e+000 0.000000e+000 0.000000e+000
0.000000e+000
vds, vgs, vbs = 0.000000e+000 -0.000000e+000 -0.000000e+000
 gds, gm, gmbs = -1.137440e-001 9.489429e-013 -9.489493e-013
ids = -1.137440e-013
Pseudotransient analysis succeeded
Warning : Negative mos conductance for device M4
v(d), v(g), v(s), v(b) = 7.057633e+000 1.075000e+000 5.000000e+000
5.000000e+000
vds, vgs, vbs = 2.057633e+000 3.925000e+000 -0.000000e+000
gds, gm, gmbs = 4.964028e-004 1.481314e-004 -2.128912e-004
ids = 8.348474e-004
Warning : Negative mos conductance for device M5
v(d), v(g), v(s), v(b) = 7.057633e+000 1.075000e+000 5.000000e+000
5.000000e+000
vds, vgs, vbs = 2.057633e+000 3.925000e+000 -0.000000e+000
gds, gm, gmbs = 4.964028e-004 1.481314e-004 -2.128912e-004
ids = 8.348474e-004
Warning : Disabling printout of duplicate warning messages.
: Use '.options maxmsg=0' to view all warnings,
: or increase maxmsg from 5 to view more messages.

* SIMULATION STATISTICS:
* DC operating point
* Total DC operating points =1
* Total Newton iterations = 385
* Total Current evaluations = 5354
* Transient analysis
* Transient timesteps = 145
* Successful timesteps = 140
* Failed timesteps =5
* Newton non-convergence failures = 5
* Delta voltage (dv) failures =0
* Newton iterations = 390
* Successful Newton iterations = 335
* Failed Newton iterations = 55
* Average Newton iterations/timestep = 2.690
* Average Newton iterations/success = 2.393
* Current evaluations = 680
* Matrix statistics: OP TRAN
* Matrix factors 385 390
* Matrix solves 385 390
* Size 3 3
* Initial elements 7 7
* Final elements 7 7
* Fill-ins 0 0
* Initial density 82.57% 77.78%
* Final density 82.57% 77.78%
* Total matrix factorizations = 775
* Total matrix-vector solves = 775
* Total matrix solve time (seconds) = 0
* T-Spice process times
* Newton solver 1.40 seconds
* Current evaluations 0.95 seconds
* Jacobian construction 0.45 seconds
* Linear solver 0.00 seconds
*
Parsing 0.01 seconds
Setup 0.00 seconds
DC operating point 1.19 seconds
Transient Analysis 0.22 seconds
Overhead 0.00 seconds
-----------------------------------------
Total 1.42 seconds
Simulation completed with 6 Warnings

W –EDIT WAVEFORM VIEWER:

Viva Questions:-

Q.1 NAND and NOR gates are universal gates, why?

Q.2 Which one is the basic gate using CMOS?
Q.3 Implement following function using NAND gate only:
F= A+BC’+AC’+ABC
Q.4 Implement above function using NOR also.