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3 nV/√Hz Ultralow Distortion,

High Speed Op Amp


AD8045
FEATURES APPLICATIONS
Ultralow distortion Instrumentation
SFDR IF and baseband amplifiers
−101 dB @ 5 MHz Active filters
−90 dB @ 20 MHz ADC drivers
−63 dB @ 70 MHz DAC buffers
Third-order intercept CONNECTION DIAGRAMS
43 dBm @ 10 MHz
Low noise
NC 1 8 +VS
3 nV/√Hz FEEDBACK 2 7 OUTPUT
3 pA/√Hz –IN 3 6 NC

04814-0-001
High speed +IN 4 5 –VS

1 GHz, −3 dB bandwidth (G = +1)


1350 V/µs slew rate
Figure 1. 8-Lead AD8045 LFCSP (CP-8)
7.5 ns settling time to 0.1%
Standard and low distortion pinout FEEDBACK 1 8 NC
Supply current: 15 mA
–IN 2 7 + VS
Offset voltage: 1.0 mV max
Wide supply voltage range: 3.3 V to 12 V +IN 3 6 OUTPUT

04814-0-001
–VS 4 5 NC

Figure 2. 8-Lead AD8045 SOIC/EP (RD-8)


GENERAL DESCRIPTION
The AD8045 is a unity gain stable voltage feedback amplifier The AD8045 amplifier is available in a 3 mm × 3 mm LFCSP
with ultralow distortion, low noise, and high slew rate. With a and the standard 8-lead SOIC. Both packages feature an
spurious-free dynamic range of −90 dBc @ 20 MHz, the exposed paddle that provides a low thermal resistance path to
AD8045 is an ideal solution in a variety of applications, the PCB. This enables more efficient heat transfer, and increases
including ultrasound, ATE, active filters, and ADC drivers. reliability. The AD8045 works over the extended industrial
ADI’s proprietary next generation XFCB process and innovative temperature range (−40°C to +125°C).
architecture enables such high performance amplifiers. –20
G = +1
–30 VS = ±5V
The AD8045 features a low distortion pinout for the LFCSP, VOUT = 2V p-p
which improves second harmonic distortion and simplifies the –40 RL = 1kΩ
RS = 100Ω
HARMONIC DISTORTION (dBc)

layout of the circuit board. –50

The AD8045 has 1 GHz bandwidth, 1350 V/µs slew rate, and –60

settles to 0.1% in 7.5 ns. With a wide supply voltage range (3.3 V –70
to 12 V) and low offset voltage (200 µV), the AD8045 is an ideal –80
candidate for systems that require high dynamic range, preci- HD3 LFCSP
–90
sion, and high speed. HD2 LFCSP
–100

–110
04814-0-079

–120
0.1 1 10 100
FREQUENCY (MHz)

Figure 3. Harmonic Distortion vs. Frequency for Various Packages

Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
or otherwise under any patent or patent rights of Analog Devices. Trademarks and Tel: 781.329.4700 www.analog.com
registered trademarks are the property of their respective owners. Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
AD8045

TABLE OF CONTENTS
Specifications with ±5 V Supply ..................................................... 3 Applications..................................................................................... 19

Specifications with +5 V Supply ..................................................... 4 Low Distortion Pinout............................................................... 19

Absolute Maximum Ratings............................................................ 5 High Speed ADC Driver ........................................................... 19

Thermal Resistance ...................................................................... 5 90 MHz Active Low-Pass Filter ................................................ 20

ESD Caution.................................................................................. 5 Printed Circuit Board Layout ....................................................... 22

Pin Configuration and Function Description .............................. 6 Signal Routing............................................................................. 22

Typical Performance Characteristics ............................................. 7 Power Supply Bypassing ............................................................ 22

Circuit Configurations................................................................... 16 Grounding ................................................................................... 22

Wideband Operation ................................................................. 16 Exposed Paddle........................................................................... 22

Theory of Operation ...................................................................... 17 Driving Capacitive Loads.......................................................... 23

Frequency Response................................................................... 17 Outline Dimensions ....................................................................... 24

DC Errors .................................................................................... 17 Ordering Guide .......................................................................... 24

Output Noise............................................................................... 18

REVISION HISTORY
7/04—Revision 0: Initial Version

Rev. 0 | Page 2 of 24
AD8045

SPECIFICATIONS WITH ±5 V SUPPLY


TA = 25°C, G = +1, RS = 100 Ω, RL = 1 kΩ to ground, unless noted otherwise. Exposed paddle must be floating or connected to −VS.
Table 1.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth G = +1, VOUT = 0.2 V p-p 1000 MHz
G = +1, VOUT = 2 V p-p 300 350
G = +2, VOUT = 0.2 V p-p 320 400 MHz
Bandwidth for 0.1 dB Flatness G = +2, VOUT = 2 V p-p, RL = 150 Ω 55 MHz
Slew Rate G = +1, VOUT = 4 V step 1000 1350 V/µs
Settling Time to 0.1% G = +2, VOUT = 2 V step 7.5 ns
NOISE/HARMONIC PERFORMANCE
Harmonic Distortion (dBc) HD2/HD3 fC = 5 MHz, VOUT = 2 V p-p
LFCSP −102/−101 dBc
SOIC −106/−101 dBc
fC = 20 MHz, VOUT = 2 V p-p
LFCSP −98/−90 dBc
SOIC −97/−90 dBc
fC = 70 MHz, VOUT = 2 V p-p
LFCSP −71/−71 dBc
SOIC −60/−71 dBc
Input Voltage Noise f = 100 kHz 3 nV/√Hz
Input Current Noise f = 100 kHz 3 pA/√Hz
Differential Gain Error NTSC, G = +2, RL = 150 Ω 0.01 %
Differential Phase Error NTSC, G = +2, RL = 150 Ω 0.01 Degrees
DC PERFORMANCE
Input Offset Voltage 0.2 1.0 mV
Input Offset Voltage Drift See Figure 54 8 µV/°C
Input Bias Current 2 6.3 µA
Input Bias Current Drift 8 nA/°C
Input Bias Offset Current 0.2 1.3 µA
Open-Loop Gain VOUT = −3 V to +3 V 62 64 dB
INPUT CHARACTERISTICS
Input Resistance Common-mode/differential 3.6/1.0 MΩ
Input Capacitance Common-mode 1.3 pF
Input Common-Mode Voltage Range ±3.8 V
Common-Mode Rejection VCM = ±1 V −83 −91 dB
OUTPUT CHARACTERISTICS
Output Overdrive Recovery Time VIN = ±3 V, G = +2 8 ns
Output Voltage Swing RL = 1 kΩ −3.8 to +3.8 −3.9 to +3.9 V
RL = 100 Ω −3.4 to +3.5 −3.6 to +3.6 V
Output Current 70 mA
Short-Circuit Current Sinking/sourcing 90/170 mA
Capacitive Load Drive 30% overshoot, G = +2 18 pF
POWER SUPPLY
Operating Range ±1.65 ±5 ±6 V
Quiescent Current 16 19 mA
Positive Power Supply Rejection +VS = +5 V to +6 V, −VS = −5 V −61 −68 dB
Negative Power Supply Rejection +VS = +5 V, −VS = −5 V to −6 V −66 −73 dB

Rev. 0 | Page 3 of 24
AD8045

SPECIFICATIONS WITH +5 V SUPPLY


TA = 25°C, G = +1, RS = 100 Ω, RL = 1 kΩ to midsupply, unless otherwise noted. Exposed paddle must be floating or connected to −VS.
Table 2.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth G = +1, VOUT = 0.2 V p-p 900 MHz
G = +1, VOUT = 2 V p-p 160 200 MHz
G = +2, VOUT = 0.2 V p-p 320 395 MHz
Bandwidth for 0.1 dB Flatness G = +2, VOUT = 2 V p-p, RL = 150 Ω 60 MHz
Slew Rate G = +1, VOUT = 2 V step 480 1060 V/µs
Settling Time to 0.1% G = +2, VOUT = 2 V step 10 ns
NOISE/HARMONIC PERFORMANCE
Harmonic Distortion (dBc) HD2/HD3 fC = 5 MHz, VOUT = 2 V p-p
LFCSP −89/−83 dBc
SOIC −92/−83 dBc
fC = 20 MHz, VOUT = 2 V p-p
LFCSP −81/−70 dBc
SOIC −83/−70 dBc
fC = 70 MHz, VOUT = 2 V p-p
LFCSP −57/−46 dBc
SOIC −57/−46 dBc
Input Voltage Noise f = 100 kHz 3 nV/√Hz
Input Current Noise f = 100 kHz 3 pA/√Hz
Differential Gain Error NTSC, G = +2, RL = 150 Ω 0.01 %
Differential Phase Error NTSC, G = +2, RL = 150 Ω 0.01 Degrees
DC PERFORMANCE
Input Offset Voltage 0.5 1.4 mV
Input Offset Voltage Drift See Figure 54 7 µV/°C
Input Bias Current 2 6.6 µA
Input Bias Current Drift 7 nA/°C
Input Bias Offset Current 0.2 1.3 µA
Open-Loop Gain VOUT = 2 V to 3 V 61 63 dB
INPUT CHARACTERISTICS
Input Resistance Common-mode/differential 3/0.9 MΩ
Input Capacitance Common-mode 1.3 pF
Input Common-Mode Voltage Range 1.2 to 3.8 V
Common-Mode Rejection VCM = 2 V to 3 V −78 −94 dB
OUTPUT CHARACTERISTICS
Output Overdrive Recovery Time VIN = −0.5 V to +3 V, G = +2 10 ns
Output Voltage Swing RL = 1 kΩ 2.2 to 3.7 1.1 to 4.0 V
RL = 100 Ω 2.5 to 3.5 1.2 to 3.8 V
Output Current 55 mA
Short-Circuit Current Sinking/sourcing 70/140 mA
Capacitive Load Drive 30% overshoot, G = +2 15 pF
POWER SUPPLY
Operating Range 3.3 5 12 V
Quiescent Current 15 18 mA
Positive Power Supply Rejection +VS = +5 V to +6 V, −VS = 0 V −65 −67 dB
Negative Power Supply Rejection +VS = +5 V, −VS = 0 V to −6 V −70 −73 dB

Rev. 0 | Page 4 of 24
AD8045

ABSOLUTE MAXIMUM RATINGS


Table 3. The power dissipated in the package (PD) is the sum of the qui-
Parameter Rating escent power dissipation and the power dissipated in the die
Supply Voltage 12.6 V due to the AD8045 drive at the output. The quiescent power is
Power Dissipation See Figure 4 the voltage between the supply pins (VS) times the quiescent
Common-Mode Input Voltage −VS − 0.7 V to +VS + 0.7 V current (IS).
Differential Input Voltage ±VS
Exposed Paddle Voltage −VS PD = Quiescent Power + (Total Drive Power – Load Power)
Storage Temperature −65°C to +125°C
⎛V V ⎞ VOUT 2
Operating Temperature Range −40°C to +125°C PD = (VS × I S ) + ⎜⎜ S × OUT ⎟–

Lead Temperature Range 300°C ⎝ 2 RL ⎠ RL
(Soldering 10 sec)
Junction Temperature 150°C RMS output voltages should be considered. If RL is referenced to
−VS, as in single-supply operation, the total drive power is VS ×
Stresses above those listed under Absolute Maximum Ratings IOUT. If the rms signal levels are indeterminate, consider the
may cause permanent damage to the device. This is a stress worst case, when VOUT = VS/4 for RL to midsupply.
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational (VS / 4 )2
section of this specification is not implied. Exposure to absolute PD = (VS × I S ) +
RL
maximum rating conditions for extended periods may affect
device reliability. In single-supply operation with RL referenced to −VS, worst case
is VOUT = VS/2.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, i.e., θJA is specified Airflow increases heat dissipation, effectively reducing θJA.
for device soldered in circuit board for surface-mount packages. Also, more metal directly in contact with the package leads and
exposed paddle from metal traces, through holes, ground, and
Table 4. Thermal Resistance
power planes reduce θJA.
Package Type θJA θJC Unit
SOIC 80 30 °C/W Figure 4 shows the maximum safe power dissipation in the
LFCSP 93 35 °C/W package versus the ambient temperature for the exposed paddle
SOIC (80°C/W) and LFCSP (93°C/W) package on a JEDEC
standard 4-layer board. θJA values are approximations.
Maximum Power Dissipation
4.0
The maximum safe power dissipation for the AD8045 is limited
by the associated rise in junction temperature (TJ) on the die. At 3.5
MAXIMUM POWER DISSIPATION (Watts)

approximately 150°C, which is the glass transition temperature, 3.0


the plastic changes its properties. Even temporarily exceeding
this temperature limit may change the stresses that the package 2.5

exerts on the die, permanently shifting the parametric perform- 2.0


ance of the AD8045. Exceeding a junction temperature of
1.5
175°C for an extended period of time can result in changes in SOIC
silicon devices, potentially causing degradation or loss of 1.0
LFCSP
functionality.
0.5
04814-0-080

0.0
–40 –20 0 20 40 60 80 100 120
AMBIENT TEMPERATURE (°C)

Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board

ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy elec-
trostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation
and loss of functionality.

Rev. 0 | Page 5 of 24
AD8045

PIN CONFIGURATION AND FUNCTION DESCRIPTION

NC 8 AD8045 1 FEEDBACK

+VS 7 2 –IN +VS 8 1 NC


OUTPUT 7 BOTTOM 2 FEEDBACK
OUTPUT 6 3 +IN VIEW
NC 6 3 –IN
(Not to Scale)
NC 5 BOTTOM VIEW 4 –VS –VS +IN

04814-0-003
5 4

04814-0-004
(Not to Scale)

NC = NO CONNECT NC = NO CONNECT

Figure 5. SOIC Pin Configuration Figure 6 . 8-Lead LFCSP Pin Configuration

Note: The exposed paddle must be connected to −VS or electrically isolated (floating).

Table 5. 8-Lead SOIC Pin Configuration Table 6. 8-Lead LFCSP Pin Configuration
Pin No. Mnemonic Description Pin No. Mnemonic Description
1 FEEDBACK Feedback Pin 1 NC No Connect
2 −IN Inverting Input 2 FEEDBACK Feedback Pin
3 +IN Noninverting Input 3 −IN Inverting Input
4 −VS Negative Supply 4 +IN Noninverting Input
5 NC NC 5 −VS Negative Supply
6 OUTPUT Output 6 NC No Connect
7 +VS Positive Supply 7 OUTPUT Output
8 NC NC 8 +VS Positive Supply
9 Exposed Paddle Must Be Connected to −VS or 9 Exposed Paddle Must Be Connected to −VS or
Electrically Isolated Electrically Isolated

Rev. 0 | Page 6 of 24
AD8045

TYPICAL PERFORMANCE CHARACTERISTICS


1 12
VS = ±5V G = +2
RL = 1kΩ 11 VS = ±5V
0 RL = 1kΩ 18pF
NORMALIZED CLOSED-LOOP GAIN (dB)

G = +2 10 R = 499Ω
F
10pF
–1 9

CLOSED-LOOP GAIN (dB)


8
–2
G = +10 G = –1 7

–3 6
5
–4 5pF
4
0pF
–5 3
2
–6
1

04814-0-049

04814-0-048
–7 0
1 10 100 1000 10 100 1000
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 7. Small Signal Frequency Response for Various Gains Figure 10. Small Signal Frequency Response for Various Capacitive Loads

4 4
G = +1 RL = 1kΩ G = +1
3 VS = ±5V 3 VS = ±5V
RS = 100Ω RL = 1kΩ
2 2
RL = 500Ω
CLOSED-LOOP GAIN (dB)

CLOSED-LOOP GAIN (dB)

1 1

0 0
RL = 100Ω
–1 –1 –40°C

–2 –2
+125°C
–3 –3

–4 –4

–5 –5
+25°C
04814-0-050

04814-0-052
–6 –6
10 100 1000 10 100 1000
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 8. Small Signal Frequency Response for Various Loads Figure 11. Small Signal Frequency Response for Various Temperatures

5 6.3
G = +1 G = +2
4 RL = 1kΩ VS = ±5V
RS = 100Ω RF = 499Ω
VS = ±2.5V 6.2 R = 150Ω
3 L
CLOSED-LOOP GAIN (dB)

CLOSED-LOOP GAIN (dB)

2
VS = ±5V 6.1
VOUT = 2V p-p
1

0 6.0
VOUT = 200mV p-p
–1
5.9
–2

–3
5.8
–4
04814-0-051

04814-0-039

–5 5.7
10 100 1000 1 10 100
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 9. Small Signal Frequency Response for Various Supplies Figure 12. 0.1 dB Flatness vs. Frequency for Various Output Voltages

Rev. 0 | Page 7 of 24
AD8045
2 70 0
G = +1 VS = ±5V
1 RL = 1kΩ RL = 1kΩ
RS = 100Ω 60 –45
0 VOUT = 2V p-p

OPEN-LOOP PHASE (Degrees)


–1 50 –90
CLOSED-LOOP GAIN (dB)

VS = ±5V

OPEN-LOOP GAIN (dB)


–2
40 –135
–3

–4 30 –180
VS = ±2.5V
–5
20 –225
–6
–7 10 –270

–8
0 –315
–9

04814-0-043

04814-0-064
–10 –10 –360
10 100 1000 0.01 0.1 1 10 100 1000
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 13. Large Signal Frequency Response for Various Supplies Figure 16. Open-Loop Gain and Phase vs. Frequency

2 –20
G = +1 G = +1
1 VS = ±5V –30 VS = ±5V
RS = 100Ω VOUT = 2V p-p
–40 RL = 1kΩ
0 VOUT = 2V p-p
RS = 100Ω
HARMONIC DISTORTION (dBc)
–1
RL = 1kΩ
CLOSED-LOOP GAIN (dB)

–50
–2
–60
–3

–4 –70
RL = 100Ω
–5 –80
–6 HD3 SOIC AND LFCSP
–90
–7
–100 HD2 LFCSP
–8
HD2 SOIC
–110
–9

04814-0-030
04814-0-042

–10 –120
10 100 1000 0.1 1 10 100
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 14. Large Signal Frequency Response for Various Loads Figure 17. Harmonic Distortion vs. Frequency for Various Packages

2 –30
G = +2 G = +1
V = ±5V
1 –40 VS = 4V p-p
NORMALIZED CLOSED-LOOP GAIN (dB)

OUT HD2 SOIC


0 RL = 1kΩ
–50
HARMONIC DISTORTION (dBc)

–1 HD2 LFCSP
–60
–2
G = +10 G = –1 –70
HD3 LFCSP AND SOIC
–3
–80
–4
–90
–5
–100
–6 V = ±5V
S
RF = 499Ω
–7 R = 1kΩ –110
L
VOUT = 2V p-p
04814-0-041

04814-0-028

–8 –120
1 10 100 1000 0.1 1 10 100
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 15. Large Signal Frequency Response for Various Gains Figure 18. Harmonic Distortion vs. Frequency for Various Packages

Rev. 0 | Page 8 of 24
AD8045
–20 –30
G = +1 G = +2
V = ±5V VS = ±5V
–30 S –40 VOUT = 2V p-p
VOUT = 2V p-p
RL = 100Ω RL = 150Ω
–40 RS = 100Ω R = 499Ω
HARMONIC DISTORTION (dBc)

HARMONIC DISTORTION (dBc)


–50 F
–50
–60
–60 HD2 SOIC
–70
–70
HD2 SOIC –80
–80
HD2 LFCSP
–90
–90
HD2 LFCSP –100
–100

HD3 SOIC AND LFCSP HD3 SOIC AND LFCSP

04814-0-032

04814-0-033
–110 –110
0.1 1 10 100 0.1 1 10 100
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 19. Harmonic Distortion vs. Frequency for Various Packages Figure 22. Harmonic Distortion vs. Frequency for Various Packages

–20 –40
G = –1 G = +10
V = ±5V VS = ±5V
–30 S
VOUT = 2V p-p –50 VOUT = 2V p-p
RL = 1kΩ RL = 1kΩ HD2 SOIC
–40 SOIC AND LFCSP

HARMONIC DISTORTION (dBc)


HARMONIC DISTORTION (dBc)

–60
–50
HD2 LFCSP
–70
–60

–70 –80

–80
HD2 –90
–90
HD3 HD3 SOIC AND LFCSP
–100
–100

04814-0-034
04814-0-036

–110 –110
0.1 1 10 100 0.1 1 10 100
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 20. Harmonic Distortion vs. Frequency for Various Packages Figure 23. Harmonic Distortion vs. Frequency for Various Packages

–30 –50
G = –1 G = +1
VS = ±5V VS = ±5V
–40 RL = 150Ω
–60 RL = 1kΩ
VOUT = 2V p-p RS = 100Ω
HARMONIC DISTORTION (dBc)

HARMONIC DISTORTION (dBc)

–50 f = 10MHz
–70
HD2 LFCSP HD3 SOIC AND LFCSP
–60
–80
HD2 SOIC
–70
–90
–80

–100
–90
HD2 SOIC

–100 –110
HD2 LFCSP
HD3 SOIC AND LFCSP
04814-0-037

04814-0-025

–110 –120
0.1 1 10 100 0 1 2 3 4 5 6 7 8
FREQUENCY (MHz) OUTPUT AMPLITUDE (V p-p)

Figure 21. Harmonic Distortion vs. Frequency for Various Packages Figure 24. Harmonic Distortion vs. Output Voltage for Various Packages

Rev. 0 | Page 9 of 24
AD8045
–40 –30
G = +1 G = +1
VS = ±5V VS = ±2.5
–50 R L = 150Ω –40 VOUT = 2V p-p
RS = 100Ω RL = 1kΩ
RS = 100Ω
HARMONIC DISTORTION (dBc)

HARMONIC DISTORTION (dBc)


f = 10MHz
–60 –50

HD2 LFCSP
–70 –60
HD2 SOIC
HD3 SOIC AND LFCSP
–80 –70

–90 –80
HD2 LFCSP
–100 –90
HD3 SOIC AND LFCSP HD2 SOIC

04814-0-024

04814-0-029
–110 –100
0 1 2 3 4 5 6 7 8 1 10 100
OUTPUT AMPLITUDE (V p-p) FREQUENCY (MHz)

Figure 25. Harmonic Distortion vs. Output Voltage for Various Packages Figure 28. Harmonic Distortion vs. Frequency for Various Packages

–40 –20
G = –1 G = +1
VS = ±5V VS = ±2.5V
–50 RL = 1kΩ –30 VOUT = 2V p-p
f = 10MHz RL = 100Ω
–40 RS = 100Ω
SOIC AND LFCSP

HARMONIC DISTORTION (dBc)


HARMONIC DISTORTION (dBc)

–60

–70 –50

–80 –60
HD3 SOIC AND LFCSP
HD2
–90 –70
HD3
–100 –80
HD2 LFCSP
–110 –90
HD2 SOIC

04814-0-031
04814-0-026

–120 –100
0 1 2 3 4 5 6 7 8 1 10 100
OUTPUT VOLTAGE (V p-p) FREQUENCY (MHz)

Figure 26. Harmonic Distortion vs. Output Voltage Figure 29. Harmonic Distortion vs. Frequency for Various Packages

–40 –20
G = –1
G = –1
VS = ±2.5V
VS = ±5V
–50 R = 150Ω –30 VOUT = 2V p-p
L RL = 1kΩ
f = 10MHz
SOIC AND LFCSP
HARMONIC DISTORTION (dBc)

–60 –40
DISTORTION (dBc)

–70 –50
HD2 SOIC HD2 LFCSP
–80 –60

HD3
–90 –70

HD3 SOIC AND LFCSP


–100 –80
HD2
–110 –90
04814-0-035
04814-0-027

–120 –100
0 1 2 3 4 5 6 7 8 0.1 1 10 100
OUTPUT VOLTAGE (V p-p) FREQUENCY (MHz)

Figure 27. Harmonic Distortion vs. Output Voltage Figure 30. Harmonic Distortion vs. Frequency for Various Packages

Rev. 0 | Page 10 of 24
AD8045
–40 0.15
G = +1 RS = 100Ω
VS = +5V RL = 150Ω
–50 RL = 1kΩ G = +1
RS = 100Ω 0.10 V = ±2.5
S
OR VS = ±5V
HARMONIC DISTORTION (dBc)

f = 10MHz
–60

OUTPUT VOLTAGE (V)


0.05
HD3 SOIC AND LFCSP
–70
0
–80

–0.05
–90
HD2 SOIC

–0.10
–100
HD2 LFCSP

04814-0-022

04814-0-012
–110 –0.15
0.5 1.0 1.5 2.0 2.5 3.0 0 5 10 15 20 25
OUTPUT VOLTAGE (V p-p) TIME (ns)

Figure 31. Harmonic Distortion vs. Output Voltage for Various Packages Figure 34. Small Signal Transient Response for Various Supplies and Loads

–40 0.15
G = +1 RL = 1kΩ
VS = +5V CL = 10pF
–50 RL = 150Ω RSNUB = 30Ω
0.10 V = ±5V
RS = 100Ω S
G = +1
HARMONIC DISTORTION (dBc)

f = 10MHz
–60

OUTPUT VOLTAGE (V)


0.05

–70
HD3 SOIC AND LFCSP
0
–80

–0.05
–90 RSNUB
30Ω

–0.10 CL RL
–100
HD2 SOIC 10pF 1kΩ
HD2 LFCSP
04814-0-023

04814-0-013
–110 –0.15
0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 0 5 10 15 20 25
OUTPUT VOLTAGE (V p-p) TIME (ns)

Figure 32. Harmonic Distortion vs. Output Voltage for Various Packages Figure 35. Small Signal Transient Response for Various Supplies and Loads

1600 0.15
RL = 1kΩ POSITIVE SLEW RATE VS = ±2.5V
VS = ±5V G = +2
1400 RC = 1kΩ
0.10 OR RC = 150kΩ
1200
NEGATIVE SLEW RATE
OUTPUT VOLTAGE (V)

0.05
SLEW RATE (V/µs)

1000

800 0

600
–0.05
400
–0.10
200
04814-0-076

04814-0-014

0 –0.15
0 1 2 3 4 5 0 5 10 15 20 25
OUTPUT VOLTAGE STEP (V) TIME (ns)

Figure 33. Slew Rate vs. Output Voltage Figure 36. Small Signal Transient Response for Various Loads G = +2

Rev. 0 | Page 11 of 24
AD8045
0.20 3
VS = ±5V
18pF
RL = 1kΩ
0.15 2 G = +2

0.10
1
OUTPUT VOLTAGE (V)

0pF

OUTPUT VOLTAGE (V)


0.05
0
0
–1
–0.05
0pF
–2
–0.10
10pF
–0.15 G = +2 –3
VS = ±5V
RL = 1kΩ 18pF

04814-0-015

04814-0-018
–0.20 –4
0 5 10 15 20 25 0 5 10 15 20 25
TIME (ns) TIME (ns)

Figure 37. Small Signal Transient Response with Capacitive Load Figure 40. Large Signal Transient Response with Capacitive Load

3 3
VS = ±5V
RS = 100Ω
G = +2
2 2

LOAD = 1kΩ OR 150Ω


OUTPUT VOLTAGE (V)

1 OUTPUT VOLTAGE (V) 1

0 0

–1 –1

–2 –2
G = –1
VS = ±5V
RL = 1kΩ
04814-0-016

04814-0-019
–3 –3
0 5 10 15 20 25 0 5 10 15 20 25
TIME (ns) TIME (ns)

Figure 38. Large Signal Transient Response for Various Loads Figure 41. Large Signal Transient Response, Inverting

3 6
RL = 1kΩ G = +1 INPUT
RS = 100Ω 5 VS = ±5V
G = +1 f = 5MHz
2 VS = ±5V 4
INPUT AND OUTPUT VOLTAGE (V)

3
OUTPUT VOLTAGE (V)

1 2 OUTPUT
VS = ±2.5V 1
0 0
–1
–1 –2
–3
–2 –4

–5
04814-0-017

04814-0-061

–3 –6
0 5 10 15 20 25 0 20 40 60 80 100 120 140 160 180 200
TIME (ns) TIME (ns)

Figure 39. Large Signal Transient Response for Various Supplies Figure 42. Input Overdrive Recovery

Rev. 0 | Page 12 of 24
AD8045
6 0
G = +2 2 × INPUT VS = ±5V
5 VS = ±5V
f = 5MHz –10
4
INPUT AND OUTPUT VOLTAGE (V)

POWER SUPPLY REJECTION (dB)


3 –20
2 OUTPUT
–30
1 –PSR
0 –40
+PSR
–1
–50
–2
–3 –60
–4
–70
–5

04814-0-062

04814-0-045
–6 –80
0 20 40 60 80 100 120 140 160 180 200 0.01 0.1 1 10 100 1000
TIME (ns) FREQUENCY (MHz)

Figure 43. Output Overdrive Recovery Figure 46. Power Supply Rejection vs. Frequency

100 –30
VS = ±5V
RF = 499Ω
–40

COMMON-MODE REJECTION (dB)


VOLTAGE NOISE (nV/ Hz)

–50

10 –60

–70

–80
04814-0-053

04814-0-020
1 –90
10 100 1k 10k 100k 1M 10M 100M 1G 0.1 1 10 100 1000
FREQUENCY (Hz) FREQUENCY (MHz)

Figure 44. Voltage Noise vs. Frequency Figure 47. Common-Mode Rejection vs. Frequency

100 100k
VS = ±5V
G = +1
CLOSED-LOOP INPUT IMPEDANCE (Ω)

10k
CURRENT NOISE (pA/ Hz)

10 1000

100
04814-0-054
04814-0-078

1 10
100 1k 10k 100k 1M 10M 100M 1 10 100 1000
FREQUENCY (Hz) FREQUENCY (MHz)

Figure 45. Current Noise vs. Frequency Figure 48. Input Impedance vs. Frequency

Rev. 0 | Page 13 of 24
AD8045
1000 VS = ±5V
G = +1
100 N = 450
VS = ±5V
X = 50µV
CLOSED-LOOP OUTPUT IMPEDANCE (Ω)

σ = 180µV
100
80

10
60

COUNT
1 40

0.1 20

04814-0-063
0

04814-0-055
0.01
–900 –600 –300 0 300 600 900
1 10 100 1000
VOFFSET (µV)
FREQUENCY (MHz)

Figure 49. Output Impedance vs. Frequency Figure 52. VOS Distribution for VS = ±5 V

50 VS = +5V
G = +10 N = 450
48 VS = ±5V 80 X = 540µV
RL = 1kΩ σ = 195µV
46
THIRD-ORDER INTERCEPT (dBm)

44
60
42
COUNT

40
40
38

36
20
34

32

04814-0-077
0
04814-0-040

30
5 10 20 30 40 –300 0 300 600 900 1200 1500
FREQUENCY (MHz) VOFFSET (µV)

Figure 50. Third-Order Intercept vs. Frequency Figure 53. VOS Distribution for VS = +5 V

0 0.25 500

–0.02
GAIN 300
G = +2
–0.04 0.20
DIFFERENTIAL PHASE (Degrees)

VS = ±5V 100 VS = +5V


DIFFERENTIAL GAIN (%)

–0.06
OFFSET VOLTAGE (µV)

–100
–0.08 0.15

–0.10 –300

–0.12 0.10
–500
–0.14 VS = ±5V
–700
–0.16 0.05
PHASE
–900
–0.18
04814-0-058
04814-0-021

–0.20 0 –1100
1 10 –40 –25 –10 5 20 35 50 65 80 95 110 125
NUMBER OF 150Ω LOADS TEMPERATURE (°C)

Figure 51. Differential Gain and Phase vs. Number of 150 Ω Loads Figure 54. Offset vs. Temperature for Various Supplies

Rev. 0 | Page 14 of 24
AD8045
–1.0 1.5

–1.2 +VS – VOUT


1.0

OUTPUT SATURATION VOLTAGE (V)


–1.4

–1.6 IB–, VS = ±5V


0.5
BIAS CURRENT (µA)

–1.8 IB+, VS = ±5V VS = ±5V VS = ±5V


–2.0 0

–2.2 IB–, VS = 5V
–0.5
–2.4
IB+, VS = 5V
–2.6
–1.0
–2.8 –VS – VOUT

04814-0-044
04814-0-059
–3.0 –1.5
–40 –25 –10 5 20 35 50 65 80 95 110 125 0.1 1 10
TEMPERATURE (°C) LOAD (kΩ)

Figure 55. Input Bias Current vs. Temperature for Various Supplies Figure 58. Output Saturation Voltage vs. Load for Various Supplies

1.20 4
RL = 1kΩ
VS = ±5V
3
1.15
OUTPUT SATURATION VOLTAGE (V)

2
–VS + VOUT
1.10
1
VOS (mV)
1.05 0
RL = 1kΩ
VS = 5V –1
1.00 +VS – VOUT

–2
+VS – VOUT –VS + VOUT
0.95 RL = 150Ω
–3
04814-0-057

04814-0-047
0.90 –4
–40 –25 –10 5 20 35 50 65 80 95 110 125 –4 –3 –2 –1 0 1 2 3 4
TEMPERATURE (°C) VOUT (V)

Figure 56. Output Saturation vs. Temperature for Various Supplies


Figure 59. Input Offset Voltage vs. Output Voltage for Various Loads

17.0 0.30
G = +2
VS = ±5V
VOUT = 2V p-p
0.20 RL = 150Ω
16.5
RF = 499Ω
SUPPLY CURRENT (mA)

VS = ±5V 0.10
SETTLING (%)

16.0

0
VS = 5V
15.5
–0.10

15.0
–0.20
04814-0-046
04814-0-056

14.5 –0.30
–40 –25 –10 5 20 35 50 65 80 95 110 125 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5
TEMPERATURE (°C) TIME (ns)

Figure 60. Short Term 0.1% Settling Time


Figure 57. Supply Current vs. Temperature for Various Supplies

Rev. 0 | Page 15 of 24
AD8045

CIRCUIT CONFIGURATIONS
WIDEBAND OPERATION
RF
Figure 61 and Figure 62 show the recommended circuit
configurations for noninverting and inverting amplifiers. In +VS 10µF
+
unity gain (G = +1) applications, RS helps to reduce high
frequency peaking. It is not needed for any other configurations. 0.1µF

For more information on layout, see the Printed Circuit Board VIN
RG

Layout section. RSNUB


AD8045 VOUT

The resistor at the output of the amplifier, labeled RSNUB, is only 0.1µF

used when driving large capacitive loads. Using RSNUB improves R = RG||RF

04814-0-075
10µF
stability and minimizes ringing at the output. For more infor- +
mation, see the Driving Capacitive Loads section. –VS

RF Figure 62. Inverting Configuration

+VS 10µF
+

0.1µF

RG

RSNUB
AD8045 VOUT
RS
VIN
0.1µF
04814-0-074

10µF
+
–VS

Figure 61. Noninverting Configuration

Rev. 0 | Page 16 of 24
AD8045

THEORY OF OPERATION
The AD8045 is a high speed voltage feedback amplifier fabri- RS

cated on ADI’s second generation eXtra Fast Complementary + VO –


VIN
Bipolar (XFCB) process. An H-bridge input stage is used to
attain a 1400 V/µs slew rate and low distortion in addition to a
low 3 nV/√Hz input voltage noise. Supply current and offset
RF
voltage are laser trimmed for optimum performance.

04814-0-009
RG
FREQUENCY RESPONSE
The AD8045’s open-loop response over frequency can be
Figure 64. Noninverting Configuration
approximated by the integrator response shown in Figure 63.
DC ERRORS
Vi Vo Figure 65 shows the dc error contributions. The total output
error voltage is

⎛R +R ⎞ ⎛R +R ⎞
Vo/Vi (dB)

Vo (error)= −I B+ RS ⎜ G F ⎟ + I B− RF + VOS⎜ G F ⎟
⎝ RG ⎠ ⎝ RG ⎠
VOS
RS
fCROSS_OVER
Vo/Vi = IB+
f + VO –
fCROSS_OVER = 400MHz
IB–
04814-0-008

0
1 10 100 1000
FREQUENCY (MHz) RF

04814-0-010
Figure 63. Open-Loop Response RG

The closed-loop transfer function for the noninverting configu-


ration is shown in Figure 64 and is written as Figure 65. Amplifier DC Errors

The voltage error due to IB+ and IB− is minimized if RS = RF||RG.


Vo 2 π × fCROSSOVER × (RG + RF )
= To include the effects of common-mode and power supply
Vi (RF + RG )s + 2 π × fCROSSOVER × RG
rejection, model VOS as
where: ∆VS ∆VCM
VOS = VOS nom + +
s is (2 πj)f. PSR CMR

fCROSSOVER is the frequency where the amplifier’s open-loop gain where:


equals 1 (0 dB).
Vos nom is the offset voltage at nominal conditions.
DC gain is therefore
ΔVS is the change in the power supply voltage from nominal
Vo (RG + RF ) conditions.
=
Vi RG
PSR is the power supply rejection.
Closed-loop −3 dB bandwidth equals
CMR is the common-mode rejection.
Vo RG
= f CROSSOVER ×
Vi (RG + RF ) ΔVCM is the change in common-mode voltage from nominal
conditions.
The closed-loop bandwidth is inversely proportional to the
noise gain of the op amp circuit, (RF + RG)/RG. This simple
model can be used to predict the −3 dB bandwidth for noise
gains above +2. The actual bandwidth of circuits with noise
gains at or below +2 is higher due to the influence of other poles
present in the real op amp.

Rev. 0 | Page 17 of 24
AD8045
OUTPUT NOISE Ven , IN+, and IN− are due to the amplifier. VR F , VRG , and
Figure 66 shows the contributors to the noise at the output of a VR S are due to the feedback network resistors. RG and RF, and
noninverting configuration.
source resistor, RS. Total output voltage noise, Vo _ en , is the rms
VRS VEN
RS sum of all the contributions.
IEN+
+ VO –
Voen =
(Gn × Ven)2 + (IN + × RS × Gn )2 + (IN − × RF||RG × Gn )2 + 4kTR f + 4kTRG (Gn )2 + 4kTRS (Gn )2
IEN–

VRF
RF where:
RG Gn is the noise gain, (RF + RG/RG).

04814-0-011
VRG

Ven is the op amp input voltage noise.


Figure 66. Amplifier DC Errors
IN is the op amp input current noise.

Table 7 lists the expected output voltage noise spectral density


for several gain configurations.
Table 7. Noise and Bandwidth for Various Gains
Output
−3 dB Noise
Gain RF RG RS Bandwidth1 (nV/√Hz)
+1 0 − 100 1 GHz 3.3
+2 499 499 0 400 MHz 7.4
+5 499 124 0 90 MHz 16.4
+10 499 56 0 40 MHz 31
−1 499 499 N/A 300 MHz 7.4

1
RL = 1 kΩ.

Rev. 0 | Page 18 of 24
AD8045

APPLICATIONS
LOW DISTORTION PINOUT This dc-coupled differential driver is best suited for ±5 V
The AD8045 LFCSP package features Analog Devices new low operation in which optimum distortion performance is required
distortion pinout. The new pinout provides two advantages and the input signal is ground referenced.
over the traditional pinout. First, improved second harmonic 511Ω
distortion performance, which is accomplished by the physical VCML – VIN
AD8045
separation of the noninverting input pin and the negative power 511Ω
33Ω
supply pin. Second, the simplification of the layout due to the VINA

dedicated feedback pin and easy routing of the gain set resistor
511Ω 511Ω
back to the inverting input pin. This allows a compact layout, VIN
which helps to minimize parasitics and increase stability. 511Ω 511Ω
20pF AD9244

VCML + VIN
The traditional SOIC pin out has been slightly modified as well AD8045
to incorporate a dedicated feedback pin. Pin 1, previously a no 33Ω
VINB
connect pin on the amplifier, is now a dedicated feedback pin. The
new pinout reduces parasitics and simplifies the board layout. 511Ω 511Ω 2.5kΩ

0.1µF
Existing applications that use the traditional SOIC pinout can
take full advantage of the outstanding performance offered by 100Ω

the AD8045. An electrical insulator may be required if the SOIC CML

04814-0-066
0.1µF 1µF OP27
rests on the ground plane or other metal trace. This is covered
in more detail in the Exposed Paddle section of this data sheet.
Figure 67. High Speed ADC Driver
In existing designs, which have Pin 1 tied to ground or another
potential, simply lift Pin 1 of the AD8045 or remove the poten- The outputs of the AD8045s are centered about the AD9244’s
tial on the Pin 1 solder pad. The designer does not need to use common-mode range of 2.5 V. The common-mode reference
the dedicated feedback pin to provide feedback for the AD8045. voltage from the AD9244 is buffered and filtered via the OP27
The output pin of the AD8045 can still be used to provide and fed to the noninverting resistor network used in the level
feedback to the inverting input of the AD8045. shifting circuit.

HIGH SPEED ADC DRIVER The spurious-free dynamic range (SFDR) performance is
When used as an ADC driver, the AD8045 offers results compa- shown in Figure 68. Figure 69 shows a 50 MHz single-tone FFT
rable to transformers in distortion performance. Many ADC performance.
applications require that the analog input signal be dc-coupled 120
and operate over a wide frequency range. Under these require-
ments, operational amplifiers are very effective interfaces to 100
ADCs. An op amp interface provides the ability to amplify and
AD8045
level shift the input signal to be compatible with the input range 80
of the ADC. Unlike transformers, operational amplifiers can be
SFDR (dBc)

operated over a wide frequency range down to and including dc. 60

Figure 67 shows the AD8045 as a dc-coupled differential driver 40


for the AD9244, a 14-bit 65 MSPS ADC. The two
amplifiers are configured in noninverting and inverting mode. 20
Both amplifiers are set with a noise gain of +2 to provide better
bandwidth matching. The inverting amplifier is set for a gain of
04814-0-067

0
–1, while the noninverting is set for a gain of +2. The noninvert- 1 10 100
INPUT FREQUENCY (MHz)
ing input is divided by 2 in order to normalize its output and
make it equal to the inverting output. Figure 68. SFDR vs. Frequency

Rev. 0 | Page 19 of 24
AD8045
0
AIN = –1dBFS Setting the resistors and capacitors equal to each other greatly
SNR = 69.9dBc
SFDR = 65.3dBc simplifies the design equations for the Sallen-Key filter. The
–20
corner frequency, or −3 dB frequency, can be described by the
–40
equation
DISTORTION (dBc)

1
–60 fc =
2πRC

–80 The quality factor, or Q, is shown in the equation below

1
–100 Q=
3−K

04814-0-068
–120
0 5 10 15 20 25 30 The gain, or K, of the circuits are
FREQUENCY (MHz)
R3 R8
Figure 69. Single-Tone FFT, FIN = 50 MHz, Sample Rate = 65 MSPS First Stage K = + 1, Second Stage K = +1
Shown in the First Nyquist Zone R4 R7

90 MHZ ACTIVE LOW-PASS FILTER Resistor values are kept low for minimal noise contribution,
Active filters are used in many applications such as antialiasing offset voltage, and optimal frequency response. Due to the low
filters or in high frequency communication IF strips. capacitance values used in the filter circuit, the PCB layout and
minimization of parasitics is critical. A few picofarads can detune
With a 400 MHz gain bandwidth product and high slew rate, the filters corner frequency, fc. The capacitor values shown in
the AD8045 is an ideal candidate for active filters. Figure 70 Figure 73 actually incorporate some stray PCB capacitance.
shows the frequency response of the 90 MHz LPF. In addition to
the bandwidth requirements, the slew rate must be capable of Capacitor selection is critical for optimal filter performance.
supporting the full power bandwidth of the filter. In this case, a Capacitors with low temperature coefficients, such as NPO
90 MHz bandwidth with a 2 V p-p output swing requires at least ceramic capacitors and silver mica, are good choices for filter
1200 V/µs. This performance is achievable only at 90 MHz elements.
because of the AD8045’s wide bandwidth and high slew rate. 20

10
The circuit shown in Figure 73 is a 90 MHz, 4-pole, Sallen-Key,
0
low-pass filter (LPF). The filter is comprised of two identical
–10
cascaded Sallen-Key LPF sections, each with a fixed gain of G =
–20
+2. The net gain of the filter is equal to G = +4 or 12 dB. The
GAIN (dB)

–30
actual gain shown in Figure 70 is only 6 dB. This is due to the
output voltage being divided in half by the series matching –40

termination resistor, RT, and the load resistor. –50

–60

–70

–80 04814-0-006

–90
0.1 1 10 100 1000
FREQUENCY (MHz)

Figure 70. 90 MHz Low-Pass Filter Response

Rev. 0 | Page 20 of 24
AD8045

1 1

04814-0-069

04814-0-070
CH1 50.0mV M4.00ns A CH1 0.00V CH1 500mV M4.00ns A CH1 0.00V

Figure 71. Small Signal Transient Response of 90 MHz LPF Figure 72. Large Signal Transient Response of 90 MHz LPF

C1
7.1pF C3
7.1pF

+5V 10µF
+5V 10µF

0.1µF
R1 R2 U1
249Ω 249Ω 0.1µF
R6 U1
INPUT 249Ω RT
RT C2 49.9Ω
49.9Ω 7.1pF 10µF R5 C4 OUTPUT
249Ω 7.1pF 10µF
R9
0.1µF 24.9Ω
0.1µF C5
–5V 5pF
–5V
R4 R3

04814-0-005
499Ω 499Ω R7 R8
499Ω 499Ω

Figure 73. 4-Pole, 90 MHz, Sallen-Key Low-Pass Filter

Rev. 0 | Page 21 of 24
AD8045

PRINTED CIRCUIT BOARD LAYOUT


Laying out the printed circuit board (PCB) is usually the last provide a low impedance path for unwanted noise out to higher
step in the design process and often proves to be one of the frequencies but are not always necessary.
most critical. A brilliant design can be rendered useless because
of a poor or sloppy layout. Since the AD8045 can operate into Placement of the capacitor returns (grounds), where the capaci-
the RF frequency spectrum, high frequency board layout con- tors enter into the ground plane, is also important. Returning
siderations must be taken into account. The PCB layout, signal the capacitors grounds close to the amplifier load is critical for
routing, power supply bypassing, and grounding all must be distortion performance. Keeping the capacitors distance short,
addressed to ensure optimal performance. but equal from the load, is optimal for performance.

SIGNAL ROUTING In some cases, bypassing between the two supplies can help
improve PSRR and maintain distortion performance in
The AD8045 LFCSP features the new low distortion pinout that crowded or difficult layouts. It is brought to the designer’s
features a dedicated feedback pin and allows a compact layout. attention here as another option to improve performance.
The dedicated feedback pin reduces the distance from the out-
put to the inverting input, which greatly simplifies the routing Minimizing the trace length and widening the trace from the
of the feedback network. capacitors to the amplifier reduces the trace inductance. A series
inductance with the parallel capacitance can form a tank circuit,
When laying out the AD8045 as a unity gain amplifier, it is rec- which can introduce high frequency ringing at the output. This
ommended that a short, but wide, trace between the dedicated additional inductance can also contribute to increased distor-
feedback pin and the inverting input to the amplifier be used to tion due to high frequency compression at the output. The use
minimize stray parasitic inductance. of vias should be minimized in the direct path to the amplifier
To minimize parasitic inductances, ground planes should be power supply pins since vias can introduce parasitic inductance,
used under high frequency signal traces. However, the ground which can lead to instability. When required, use multiple large
plane should be removed from under the input and output pins diameter vias as this lowers the equivalent parasitic
to minimize the formation of parasitic capacitors, which inductance.
degrades phase margin. Signals that are susceptible to noise GROUNDING
pickup should be run on the internal layers of the PCB, which
can provide maximum shielding. The use of ground and power planes is encouraged as a method
of proving low impedance returns for power supply and signal
POWER SUPPLY BYPASSING currents. Ground and power planes can also help to reduce stray
Power supply bypassing is a critical aspect of the PCB design trace inductance and provide a low thermal path for the ampli-
process. For best performance, the AD8045 power supply pins fier. Ground and power planes should not be used under any of
need to be properly bypassed. the pins of the AD8045. The mounting pads and the ground or
power planes can form a parasitic capacitance at the amplifiers
A parallel connection of capacitors from each of the power sup- input. Stray capacitance on the inverting input and the feedback
ply pins to ground works best. Paralleling different values and resistor form a pole, which degrades the phase margin, leading
sizes of capacitors helps to ensure that the power supply pins to instability. Excessive stray capacitance on the output also
“see” a low ac impedance across a wide band of frequencies. forms a pole, which degrades phase margin.
This is important for minimizing the coupling of noise into the
amplifier. Starting directly at the power supply pins, the smallest EXPOSED PADDLE
value and physical-sized component should be placed on the The AD8045 features an exposed paddle, which lowers the
same side of the board as the amplifier, and as close as possible thermal resistance by 25% compared to a standard SOIC plastic
to the amplifier, and connected to the ground plane. This proc- package. The exposed paddle of the AD8045 is internally con-
ess should be repeated for the next larger value capacitor. It is nected to the negative power supply pin. Therefore, when laying
recommended for the AD8045 that a 0.1 µF ceramic 0508 case out the board, the exposed paddle must either be connected to
be used. The 0508 offers low series inductance and excellent the negative power supply or left floating (electrically isolated).
high frequency performance. The 0.1 µF case provides low Soldering the exposed paddle to the negative power supply metal
impedance at high frequencies. A 10 µF electrolytic capacitor ensures maximum thermal transfer. Figure 74 and Figure 75 show
should be placed in parallel with the 0.1 µF. The 10 µf capacitor the proper layout for connecting the SOIC and LFCSP exposed
provides low ac impedance at low frequencies. Smaller values of paddle to the negative supply.
electrolytic capacitors may be used depending on the circuit
requirements. Additional smaller value capacitors help to

Rev. 0 | Page 22 of 24
AD8045
The thermal pad provides high thermal conductivity but
isolates the exposed paddle from ground or other potential. It is
recommended, when possible, to solder the paddle to the nega-
tive power supply plane or trace for maximum thermal transfer.

04814-0-071
Note that soldering the paddle to ground shorts the negative
Figure 74. SOIC Exposed Paddle Layout power supply to ground and can cause irreparable damage to
the AD8045.
The use of thermal vias or “heat pipes” can also be incorporated
into the design of the mounting pad for the exposed paddle. DRIVING CAPACITIVE LOADS
These additional vias help to lower the overall theta junction to In general, high speed amplifiers have a difficult time driving
ambient (θJA). Using a heavier weight copper on the surface to capacitive loads. This is particularly true in low closed-loop
which the amplifier’s exposed paddle is soldered can greatly gains, where the phase margin is the lowest. The difficulty arises
reduce the overall thermal resistance “seen” by the AD8045. because the load capacitance, CL, forms a pole with the output
resistance RO of the amplifier. The pole can be described by the
equation shown below.

1
fP =
04814-0-073

2πRO C L

Figure 75. LFCSP Exposed Paddle Layout If this pole occurs too close to the unity gain crossover point,
For existing designs that want to incorporate the AD8045, the phase margin degrades. This is due to the additional phase
electrically isolating the exposed paddle is another option. If the loss associated with the pole.
exposed paddle is electrically isolated, the thermal dissipation is The AD8045 output can drive 18 pF of load capacitance directly,
primarily through the leads, and the thermal resistance of the in a gain of +2 with 30% overshoot, as shown in Figure 37.
package now approaches 125°C/W; the standard SOIC θJA. Larger capacitance values can be driven but must use a snub-
However, a thermally conductive and electrically isolated pad bing resistor (RSNUB) at the output of the amplifier, as shown in
material may be used. A thermally conductive spacer, such as Figure 61 and Figure 62. Adding a small series resistor RSNUB
the Bergquist Company’s Sil-Pad, is an excellent solution to this creates a zero that cancels the pole introduced by the load
problem. Figure 76 shows a typical implementation using a capacitance. Typical values for RSNUB can range from 25 Ω to
thermal pad material. 50 Ω. The value is typically arrived at empirically and based on
the circuit requirements.
04814-0-072

THERMAL CONDUCTIVE INSULATOR

Figure 76. SOIC with Thermal Conductive Pad Material

Rev. 0 | Page 23 of 24
AD8045

OUTLINE DIMENSIONS
5.00 (0.197) BOTTOM VIEW
4.90 (0.193) (PINS UP)
4.00 (0.157) 4.80 (0.189) 2.29 (0.092)
3.90 (0.154)
3.80 (0.150) 8 5 6.20 (0.244) 2.29 (0.092)
TOP VIEW 6.00 (0.236)
1 4 5.80 (0.228)

1.27 (0.05) 0.50 (0.020)


BSC × 45°
0.25 (0.010)
1.75 (0.069)
0.25 (0.0098) 1.35 (0.053)
0.10 (0.0039) 8°
0.51 (0.020) 0.25 (0.0098) 0° 1.27 (0.050)
COPLANARITY 0.40 (0.016)
0.10 SEATING 0.31 (0.012) 0.17 (0.0068)
PLANE

COMPLIANT TO JEDEC STANDARDS MS-012


CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

Figure 77. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP]
Narrow Body (RD-8-1)—Dimensions shown in millimeters and (inches)
0.50
0.40
3.00 0.30
0.60 MAX PIN 1
BSC SQ INDICATOR
0.45
1
8
PIN 1 2.75 1.90
TOP BOTTOM 1.50
INDICATOR BSC SQ REF 1.75
VIEW 0.50 VIEW 1.60
BSC 5 4

0.25 1.60
0.90 12° MAX 0.80 MAX MIN 1.45
0.85 0.65 TYP 1.30
0.80
0.05 MAX
0.02 NOM

SEATING 0.30 0.20 REF


PLANE 0.23
0.18

Figure 78. 8-Lead Lead Frame Chip Scale Package [LFCSP]


3 mm × 3 mm Body (CP-8-2)—Dimensions shown in millimeters

ORDERING GUIDE
Model Minimum Ordering Quantity Temperature Range Package Description Branding Package Option
AD8045ARD 1 –40°C to +125°C 8-Lead SOIC/EP RD-8-1
AD8045ARD-REEL 2,500 –40°C to +125°C 8-Lead SOIC/EP RD-8-1
AD8045ARD-REEL7 1,000 –40°C to +125°C 8-Lead SOIC/EP RD-8-1
AD8045ARDZ1 1 –40°C to +125°C 8-Lead SOIC/EP RD-8-1
AD8045ARDZ-REEL1 2,500 –40°C to +125°C 8-Lead SOIC/EP RD-8-1
AD8045ARDZ-REEL71 1,000 –40°C to +125°C 8-Lead SOIC/EP RD-8-1
AD8045ACP-R2 250 –40°C to +125°C 8-Lead LFCSP HDB CP-8-2
AD8045ACP-REEL 5,000 –40°C to +125°C 8-Lead LFCSP HDB CP-8-2
AD8045ACP-REEL7 1,500 –40°C to +125°C 8-Lead LFCSP HDB CP-8-2
AD8045ACPZ-R21 250 –40°C to +125°C 8-Lead LFCSP HDB CP-8-2
AD8045ACPZ-REEL1 5,000 –40°C to +125°C 8-Lead LFCSP HDB CP-8-2
AD8045ACPZ-REEL71 1,500 –40°C to +125°C 8-Lead LFCSP HDB CP-8-2

1
Z = Pb-free part.

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and regis-
tered trademarks are the property of their respective owners
D04814–0–7/04(0)

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