FPGA Lab 3

Steven Spohrer and Ryan Hensley

(Dated: February 19, 2018)
In this lab we focused on using and creating counters within the FPGA software. We learned how
to utilize binary counters in the Quartus IP catalog to do things such as create timers or convert
binary and hexadecimal to decimal. We also created our own counter using many simple gates and
D flip-flops (turned into T flip-flops). Lastly, we familiarized ourselves with the Quartus simulator
and realized how it is a powerful tool for debugging our circuits and checking our logic.

I. LAB 3 50.37MHz ± 0.56MHz. If we had measured for a longer

In this lab, we used synchronous logic to build digital
counters and we learned how to use the simulator to see
the exact logic values held by different bits in different
parts of the circuit.
A. Lab 3.1: Binary counter, simulator
1. Procedures
In this first part of the lab, we created a 40 bit counter
from the megawizard to test the simulator functional-
ity of Quartus. The counter had sclr (set clear), clock,
and cin (count in) inputs, and a 40 bit data output, to
which we connected a series of 7-segment displays, and
connected key inputs to the sclr and cin. Because the
key inputs are always high unless pushed, we put a NOT
gate on the sclr. Next, to use the simulator, we created
an output node. This is not necessary for the opera-
tion of the circuit, but it is an easy way to view the
counter output in the simulator. The other method has
us search for a node in the memory which starts with
a long name starting with the name of our counter, like
”mf count1:inst2—lpm...” (the registered group). This
design can be seen in FIG. 1.
Upon opening the simulator, we used the node
finder to find both our created output node and the
mf count1:inst2 instance of the output terminal in mem-
ory, and then also the KEY[0] and KEY[1] inputs. Then
we set the view range to an end time of 10 us and the
clock period to 20 ns. Finally, we set all the data to dis-
play in hexadecimal. To add onto the tests we ran in the
simulation, we also tried the Timing Simulation in the
end.
time, we probably could have gotten closer to 50MHz.
Then we tested the simulator and ran the “Simula-
tion/Run Functional Simulation” function. The output
is formatted in the way that the 7-segment displays read,
with the first tick being 1001111 and next being 0010010.
For a more interesting simulation, we also had KEY[0] be
simulated to be pushed down for a small period of time.
During this time, the clock was shown to stop count-
ing, and held a value of 0 until we “released” KEY[0], at
which the counter resumed counting starting at 1. This is
shown in FIG. 2, with the highlighted column being the
second clock tick immediately after releasing KEY[0], so
it displays 0010010.
By watching the placed output pin, we can see the
counter very simply displaying an increasing 1, 2, 3, 4,
..., value in hexadecimal in FIG. 3. In FIG. 4, which is
a picture of the lowest five bits of OUT[39..0], it can be
seen that this is just an increasing binary number across
the 40 bits of the output.
Next we looked at the value of the register bus directly,
setup as seen in FIG. 5. Before running the simulation it
just says UUUUUUUU, but once the simulation is run,
it properly displays the 40 bits of the output.
Finally, we ran a Timing Simulation instead of a Func-
tional Simulation. The Timing Simulation simulates all
the various internal delays in the FPGA chip, and so
the register output is slightly delayed from the clock
edges, and this was precisely shown in the graphs. We
looked closely at the start and end times of a random
count tick of the number 0002. Given the clock period of
20ns, the 0002 tick came into the register from 33.26ns to
53.26ns (exactly 20ns), but appeared across the output
from 37.27ns to 57.27ns (a delay of 4.01ns). These delays
are from the internal circuitry of the FPGA board.
B. Lab 3.2: Binary-coded decimal counter

2. Analysis and Discussion 1. Procedures

We first wanted to check that the clock was actually
50MHz as was stated. We used a stopwatch and let it
count up for an arbitrary amount of time, then stopped
it by turning off cin using the key input. In 27 ± 0.5
seconds, the counter reached a value of 5074dca2, which
is 1,349,835,938 in decimal. This gives a frequency of
By utilizing the counter function from Lab 3.1 we were
able to construct a timer. However, we first needed
to introduce the “modulus” attribute into our counters.
The modulus attribute makes it so whenever the counter
reaches a certain number, the counter will reset back to
0 and the carry-out output pin will be 1 for one tick.

First, we connected our 50 MHz clock to the count in
pin on a 20-bit, modulus-500,000 counter. This creates
one carry out pulse every 1/100 of a second, since the
clock ticks 50 million times a second and the counter
sends one carry out pulse once every 500 thousand
counts.
Next, we utilized a series of 16-bit, modulus-10 coun-
ters to display our timer in decimal numbers. Our
carry out of the main modulus-500,000 counter is con-
nected to the carry in pin of our first modulus-10 counter.
Thus, every 1/100 of a second the first modulus-10
counter will go up one digit until it reaches 10, in which
case it resets back to 0 and sends one carry out pulse.
The number the first modulus-10 counter has currently
counted to (the q output) is input into the HEX2 hex-
adecimal display. The carry out of the first modulus-10
counter is input into the carry in of the second modulus-
10 counter, thus making the second modulus-10 counter
count up one every 1/10 of a second. The outputs of the
second counter to the hexadecimal displays and the third
counter mirrors those of the first counter to the hexadec-
imal displays and the second counter. This process of
stacking modulus-10 counters is repeated until there is 6
modulus-10 counters total, allowing us to track up to the
1000 seconds place on our timer.
Lastly, we connected the the 50 MHz clock to all of
our counters and connected a not-gated input VCC con-
trolled by KEY[0] (the right-most push button) into the
setclear input pin of each counter.
2. Analysis and Discussion
After completing the process described in the ”Pro-
cedures” section, our final circuit appeared as in FIG.
6. Once the circuit was programmed into our FPGA
board, the timer worked as expected. The HEX[2] dis-
play seemed to be going up once every 1/100 of a second,
the HEX[4] display was going up once a second, and we
used our phone timer to check that the HEX[7] display
went up after 16 minutes and 40 seconds (1000 seconds).
Pushing KEY[0] cleared the counter so it went back to
0000.00 seconds. Pushing KEY[1] paused the timer on
its current value.
C. Lab 3.3: Counter from elementary gates
1. Procedures
For the final part of the lab, we built a binary counter
rather than a decimal counter. Internally, it counts up in
binary, and then we added onto the end of it a converter
to decimal. The internal logic is built from analyzing the
patterns in the counting up of binary. Specifically, in the
sequence 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111,
1000, the 0-bit alternates every tick, the 1-bit alternates if
the 0-bit is 1, the 2-bit alternates only if the 0-bit AND
2
the 1-bit are 1, and the 3-bit similarly only alternates
only if all of the 2-bit, 1-bit, and 0-bits are 1.
We started with a modulus-50M counter with an input
of 50MHz. This will output one c out tick every second.
This single uptick enters a circuit involving four D flip-
flops all turned into trigger flip-flops using XOR gates.
To simulate the binary counting logic described in the
above paragraph, each of the last three T flip-flops also
starts with an AND gate. The first T flip-flop starts with
cout and qOut[0] going into the XOR gate. If the out-
put of the flip-flop is 0, then the XOR gate will activate
with the incoming cout high pulse, and the clock tick will
change the output from 0 to 1. In the time before the
next cout pulse, the XOR gate will always be outputting
a 1 from the 1 of the qOut[0], until the pulse, at which
time both inputs to the XOR will be 1, output will be 0,
and the flip-flop will change to a 0 output until the next
clock cycle.
For the next flip-flops, we added an AND gate before
where cout used to be. The requirement here is that
both cout and qOut[0] must be 1 for qOut[1] to switch.
If that is true, then the AND gate will give a 1 to the
XOR gate, and the logic in the above paragraph precedes
just as before.
To convert to decimal, we combine the four qOut[3..0]
bits into a divide-by-10 module. The output is named
hexOut10[3..0] and the remainder is fed into a second
identical divider, for which the name is hexOut1[3..0].
These two hexOut outputs are fed into two 7segment
converters for hex display output at HEX0 and HEX1.
2. Analysis and Discussion
The final circuit appears in FIG. 7. Note that “boucn-
ter” instance in the screenshot was not used. The circuit
worked as expected. Although the original instructions
never told us to display in decimal, we wanted to display
it that way, but displaying the binary output would have
been easily possible by just skipping the dividers. The
end output just proceeded up from 0, going to 1, 2, 3,
etc, until 15, at which the next tick reset it back from
1111 to 0000. Pushing KEY[0] did not reset the output
hexadecimal display, it only reset the 50,000,000 counter.
Thus, holding it down temporarily halted the counting,
as did repeatedly pressing faster than once every second.
Similarly, holding KEY[1] temporarily halted the count-
ing also. If we wanted KEY[0] to reset the output display,
we would have fed KEY[0] into the reset input of all the
flip-flops.
II. CONCLUSION
Over the course of Lab 3 we utilized and created many
different counters. We learned how counters can create
timers and how using the modulus attribute of counters
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can convert binary and hexadecimal numbers into dec-

imal numbers. Lastly, we created our own counter by
employing simple logic gates and a series of D flip-flops.
During Lab 3, we also discovered how useful of a tool the
Quartus simulator can be for checking and debugging cir-
cuits.

III. IMAGES APPENDIX

FIG. 2. Lab 3.1: This shows the simulator after depressing

KEY[0], which is connected through a NOT gate to the sclr
(set clear) input, and the first hexadecimal display. This will
reset the counter. Upon releasing KEY[0], it can be seen
that the next tick of the clock causes HEX0[7..0] to change
from 0000,0001 (a zero in the hexadecimal display coding) to
1001,1110 (one), then to the highlighted column 0010,0100
(two).

FIG. 1. Lab 3.1: The basic circuit layout of the counter,

including the placed output pin OUT[39..0]. This output is
not necessary in any way to the function of the circuit, but
gives the user an easy way to view q[39..0] in the Quartus
Simulator. Also note that the NOT gate between KEY[0] and
sclr, which is there because the KEY inputs are set to default
high, which would mean that the counter was set to always
clear each clock cycle unless KEY[0] was asserted. In 27 ±
0.5 seconds, this counter reached a value of 5074dca2, which
is 1,349,835,938 in decimal. This confirms that the clock set
by CLOCK 50 input is indeed 50MHz. Two more 7segment
displays below the border of the screenshot are needed to
properly display this number.

FIG. 3. Lab 3.1: The simulator showing the counting up of

OUT[39..0] pin at every clock rising edge, 0000, 0001, 0002,
...

FIG. 4. Lab 3.1: The bottom five bits of the 40 bit OUT[39..0]
pin, which are shown to just count upwards in binary, 00000,
00001, 00010, 00011, 00100, ...
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FIG. 5. Lab 3.1: The simulator window showing the addition

of the register address output. Although now it only displays
UUUUUUUUUU, it looks like FIG. 3 and 4.

FIG. 7. Lab 3.3: The multi-stage output of the binary

counter. The modulus-50,000,000 outputted a single high tick
every second, which was fed into a circuit of AND gates, XOR
gates, and D flip-flops. This second part of the circuit com-
pletes the binary counter, with qOut[3..0] representing a 4-bit
binary number, increasing by 1 every second. The d10 mod-
ules next converted the 4-bit binary number into a 2-digit
decimal number which counts from 0 to 15. This is finally fed
into the 7segment display module for display on the hexadec-
imal display.

FIG. 6. Lab 3.2: An input of 1 controlled by KEY[1] is

counted in the modulus-500000 counter for every tick of the
50 MHz clock controlling all the counters in the circuit. The
carry out of the modulus-500000 counter (which outputs a
pulse every 1/100 of second) is input into a series of modulus-
10 counters that each input the previous counter’s carry out
so that their q outputs represent a decimal timer. Each of
their 4-bit q outputs are displayed on the hexadecimal dis-
plays HEX[2]-Hex[7] so that a timer with 1/100 of a second
precision and range to the 1000s seconds place is displayed on
the FPGA board.