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DIGITAL CARRIER LINE ENCODING

Digital line encoding involves converting standard logic levels (TTL, CMOS, and the like)

to a form more suitable to telephone line transmission. Essentially, six primary factors must

be considered when selecting a line-encoding format:

1. Transmission voltages and DC component

2. Duty cycle

3. Bandwidth considerations

4. Clock and framing bit recovery

5. Error detection

6. Ease of detection and decoding

Transmission Voltages and DC Component

Transmission voltages or levels can be categorized as being either unipolar (UP) or bipolar
(BP). Unipolar transmission of binary data involves the transmission of only a single nonzero

voltage level (e.g., either a positive or a negative voltage for a logic 1 and 0 V [ground] for a

logic 0). In bipolar transmission, two nonzero voltages are involved (e.g., a positive voltage

for a logic 1 and an equal-magnitude negative voltage for a logic 0 or vice versa).

Duty Cycle

The duty cycle of a binary pulse can be used to categorize the type of transmission. If the binary pulse is
maintained for the entire bit time, this is called nonreturn to zero (NRZ). If the active time of the binary
pulse is less than 100% of the bit time, this is called return to zero (RZ).

Bandwidth Requirements

To determine the minimum bandwidth required to propagate a line-encoded digital signal,

you must determine the highest fundamental frequency associated with the signal (see Figure

12). The highest fundamental frequency is determined from the worst-case (fastest transition) binary bit
sequence. With UPNRZ, the worst-case condition is an alternating 1/0 sequence; the period of the
highest fundamental frequency takes the time of two bits and, therefore, is equal to one-half the bit rate
(fb/2). With BPNRZ, again the worst-case condition is an alternating 1/0 sequence, and the highest
fundamental frequency is one-half the bit rate (fb/2).

With UPRZ, the worst-case condition occurs when two successive logic 1s occur. Therefore,

the minimum bandwidth is equal to the bit rate (fb).With BPRZ encoding, the worst-case condition
occurs for successive logic 1s or successive logic 0s, and the minimum bandwidth is
again equal to the bit rate (fb). With BPRZ-AMI, the worst-case condition is two or more consecutive
logic 1s, and the minimum bandwidth is equal to one-half the bit rate (fb /2).

Clock and Framing Bit Recovery

To recover and maintain clock and framing bit synchronization from the received data, there

must be sufficient transitions in the data waveform. With UPNRZ and BPNRZ encoding, a

long string of 1s or 0s generates a data signal void of transitions and, therefore, is inadequate for clock
recovery. With UPRZ and BPRZ-AMI encoding, a long string of 0s also

generates a data signal void of transitions. With BPRZ, a transition occurs in each bit position regardless
of whether the bit is a 1 or a 0. Thus, BPRZ is the best encoding scheme for

clock recovery. If long sequences of 0s are prevented from occurring, BPRZ-AMI encoding provides
sufficient transitions to ensure clock synchronization.

Error Detection

With UPNRZ, BPNRZ, UPRZ, and BPRZ encoding, there is no way to determine if the received data have
errors. However, with BPRZ-AMI encoding, an error in any bit will cause

a bipolar violation (BPV, or the reception of two or more consecutive logic 1s with the same

polarity). Therefore, BPRZ-AMI has a built-in error-detection mechanism. T carriers use


BPRZ-AMI with 3 V and 3 V representing a logic 1 and 0 V representing a logic 0.

Digital Biphase

Digital biphase (sometimes called the Manchester code or diphase) is a popular type of line

encoding that produces a strong timing component for clock recovery and does not cause

dc wandering. Biphase is a form of BPRZ encoding that uses one cycle of a square wave at

0° phase to represent a logic 1 and one cycle of a square wave at 180° phase to represent a

logic 0. Digital biphase encoding is shown in Figure 14. Note that a transition occurs in the

center of every signaling element regardless of its logic condition or phase. Thus, biphase

produces a strong timing component for clock recovery. In addition, assuming an equal

probability of 1s and 0s, the average dc voltage is 0 V, and there is no dc wandering. A disadvantage of
biphase is that it contains no means of error detection.