Design of a FPGA Controller for Full Bridge Phase-Shifted Zero Voltage Switching DC/DC Power Converters

Hao Li and Qin Jiang School of Communications and Informatics Victoria University, P.O. Box 14428, Melbourne City MC 8001, Vic. Australia Email: jq@cabsav.vu.edu.au

Abstract
The paper describes the development of a FPGA (Field Programmable Gate Array) digital controller for the control of a full bridge phase-shifted zero voltage switching (FPZVS) dc/dc power converter. The merits of the FPGA technology are its flexibility, intelligence and a much faster speed than that of a DSP type digital controller. The design details are presented in this paper based on a 500 W, 500 kHz model converter. The simulation results of both the controller and the converter are presented using the Xilinx Foundation Series environment and the PSpice software respectively. 1. INTRODUCTION The switching mode power supply (SMPS) operating at a high frequency can provide small size and weight, as the filtering inductance and capacitance are reduced and power density is increased. However, a high switching frequency results in high switching losses which reduce the efficiency of the converter. To overcome this dilemma the soft-switching techniques were introduced [1-5], such as the Zero Voltage Switching (ZVS) techniques which can be used to increase the converter efficiency at high switching frequencies [3-5]. In this technique, effects of the parasitic circuit elements are used advantageously to facilitate the resonant transitions as opposed to being dissipatively snubbed. The resonant tank functions to position zero voltage across the switching device prior to turn-on, eliminating any power loss due to the simultaneous overlap of switch current and voltage at each transition [4]. Not only the switching losses but also the Radio Frequency Interference (RFI) and the ElectroMagnetic Interference (EMI) are significantly reduced. The requirement of power MOSFET switches dissipation is reduced as well and the conversion efficiency is increased significantly. Most of FPZVS converters on the market use the analog controller of integrated circuit from companies like Unitrode, Motorala and etc [1-5]. Typically two ICs are used, for instance, UC3875 IC generates the gate drive signal to the MOSFETs, and the TL074 IC implements the control loop regulators [4]. Analog controllers can provide the fastest control loop update compared with digital controllers. However, as they are designed and implemented with hardware only, it takes a long design cycle and lacks flexibility and intelligence. The application of digital controllers using digital signal processor to the control of FPZVS converters was reported [6]. Where the control law is software programmed, this allows for advanced control algorithm such as predictive and adaptive controls to be implemented. Also the non-linear dependence of the desired duty factor on the input and output voltages of the converter can be easily taken into account in the software programming. This is not possible with the analog controllers. However, given the switching frequencies 500 kHz plus for the ZVS technology, the speed of DSP may be not sufficiently high to implement advanced control algorithms. In this paper, the application of the latest PLD (Programmable Logic Device) technology into the control of the FPZVS power converter is explored. The technology features combined merits of both analog and DSP controllers, in that its design process is that of computer programming using Clike high level language. Whereas its speed is much faster than DSP. The throughput time of the PLD controller is found approximate to the conversion time of Analog/Digital converters in use. In what follows, the operation principle of the FPZVS converter is described first, features to be taken into account in the design process of the digital controller are highlighted. The design example of the FPGA digital controller based on a model converter is then discussed. Finally the simulation results are presented.

2. OPERATION PRINCIPLE OF THE FPZVS CONVERTER
+

S1

D1

C1

S4

D4

C4

Ip A

Fig.1 gives the main circuit of the full bridge with a zero voltage transition design. S1, S2, S3 and S4 are controlled switching devices, MOSFETs. D1, D2, D3 and D4 are body diodes of the MOSFETs. C1, C2, C3 and C4 are the equivalent parasitic output capacitance of the MOSFETs. T is the isolation transformer. The inductance L equals Lc + Lt, where Lc is the commutation inductance and Lt is the leakage inductance of the transformer. Zero voltage transition requires each MOSFET to be turned on and off when the voltage across its drain and source terminals, VDS, is zero. Turn-off with a zero voltage is achieved by the existence of Ci (i = 1, 2, 3, 4) as shown in Fig.1. When the MOSFET Si is conducting, Ci is short-circuited, i.e. VDSi is zero. As the voltage across the Ci cannot change instantaneously, the MOSFET is always turned off with a zero voltage. Turn-on with a zero voltage however, requires a resonant process, during which Ci of the incoming MOSFET’s Si discharges until its anti-parallel diode conducts prior to turn on, VDSi of the incoming switch is then clamped to the diode’s conducting voltage [7]. Power is only transferred to the output section during the ON time of the diagonal switches, S1/S2 or S3/S4 of Fig.1. This is similar to a conventional full bridge converter, which alternately places the transformer primary across the input supply Vi for some period of time. This duration is termed active state. During the freewheeling period, either the top two or the bottom two MOSFETs (S2/S3 or S1/S4 ) are on, termed as the passive state. The load and magnetizing currents can therefore continue to flow in the primary winding. In fact, their commutation to the secondary side is resisted by the leakage inductance, and the total resistance of the transformer, the MOSFETs, and the diode rectifier is not large enough to force a significant commutation during the freewheeling period [5]. In Fig.1, the two legs of the bridge, leg A and leg B operate under significantly different conditions. Depending on the switching sequence of S1 through S4, switching one of the legs moves the converter from the active state to the passive state. While switching the other leg moves the converter from the passive state to the active state. The former is termed A–P leg and the latter the P–A leg.

L T

B

Vi -

S3

D3

C3

S2

D2

C2

D5

Lf +

D6 Cf Ro Vo -

Fig.1 Topology of the full bridge phase shifted ZVS converter. Minimum turn-on delay time In principle, to ensure loss-less transitions, the MOSFET must be turned on only when current flows in its body diode, i.e. after its parasitic output capacitance is completely discharged and the output capacitance of the other MOSFET of the same leg is charged up. The time it takes to complete the above process is referred to as the minimum turnon delay time, Ton-min, which if associated with the P-A leg transition is greater than that of the A-P leg transition. Also it is proportional to Vi and inversely proportional to the load current. To minimize the conduction loss, the designed turn-on delay time should be based on the Ton-min corresponding to the specified load condition. The effective duty cycle The FPZVS converter works at a fixed switching frequency, its operating duty cycle, D, is proportional to the on-pulse overlap between two diagonal MOSFETs. Normally, one gating signal is fixed as a reference one, while the other is phase shifted so that the duration of the on-pulse overlap of the two devices is varied. At the maximum output, the overlap is maximum and vice versa. In Fig.2, the gating signals (top four traces) S1 through S4 over one power transfer cycle are illustrated, where the turn-on time delays between two pair of diagonal switches S1/S2 and S3/S4 are (t13 – t10) and (t5 – t2) respectively, corresponding to the amount of the phase shift implemented.

S1 S2

S3 S4 Ip VA-B DoTs/2 Ts/2 DTs/2 DeTs/2

voltages of the converter. To realize this control law with an analog controller would be complicated. While the digital control offers the possibility to program the equation in software. The minimum turn on delay and the effective duty cycle can be easily taken into account in the design of a digital controller.
t8 t10 t13 t

Vi

0

t0 t1 t2 t3 t4 t5 t6

t7 slope = Vi / ( Lc + Lt )

3. DESIGN OF THE DIGITAL CONTROLLER 500 W Model Converter

-Vi -Ipa -Iap Vs t slope = ( Vi - Vo ) / ( Lc + Lt + Lf ) slope = Vo / Lf

0

A 500 W, 400/40 V FPZVS power converter has been designed in this study, however, design details are beyond the scope of this paper, parameters of the converter are listed bellow instead: MOSFET device IRF840; switching frequency = 500 kHz; commutating inductor Lc = 14 µH; output filtering inductor Lf = 6.2 µH; output filtering capacitor Cf = 6.5 µF; load resistance Ro = 3 Ω; fixed individual switching duty cycle = 48%; maximum phase shift duty cycle = 88%; minimum turn on delay = 40 ns 3.1 The software programming The block diagram of the FPGA controlled FPZVS converter is given in Fig.3. The design of the controller is a process of computer programming using the C-like VHDL code. There are 3 concurrent processes embedded in the program, the control cycle, the reference gating signal generation and the phase shift implementation respectively. They are to be detailed in what follows. Control Cycle The command phase shift duty cycle at ith sampling cycle, Di, is calculated based on the feedback signals Vo and If as shown in Fig.3. The current control mode is implemented with a band-band control algorithm as follows: If (Im – If) > 0, Di = Di-1 + k1× sign (Vref – Vo) Otherwise Di = Di-1 + k2 × sign (Im – If) Where k1 and k2 are control constant representing the step change in Di-1, Vo is the output voltage, Vref is the reference of Vo, If is the filter inductor current and Im is the upper limit of If.

Fig.2 Gate timing and typical waveforms. Responses associated with the voltage and current at the primary terminals of the transformer, VA-B and Ip, are given as two middle traces of Fig.2 respectively. Please note that the finite slope of the rising and falling edges of the primary current, IP, results in the loss of the duty cycle Do. The effective duty cycle De is therefore reflected from the pulse width of the secondary voltage, Vs, shown as the bottom trace of Fig.2. The difference between D and De is thus

D = De + Do

(1)

The effective voltage gain of the converter can be expressed based on the effective duty cycle De.

Vo N s = ⋅ De Vi Np

(2)

where Np and Ns are turns of the primary and the secondary windings of the transformer respectively. The expression of D can be derived from Fig.1 and Fig.2 as follows N 2 ⋅ Vo − D= ( Lc + Lt ) ⋅ Vo + 4 ⋅ ( Lc + Lt ) ⋅ f s ⋅ I o Lf ( L + Lt ) N ⋅ Vi − c ⋅ Vo Lf (3)

1 where f s = – the switching frequency and Ts Np – the transformer turns ratio. N= Ns
The last equation indicates that the duty cycle D depends non-linearly on the input and output

XC4005XL Clock (25MHz) ACT22025 D0 – D7 A/D Converter MAX113 Sensor Digital Controller (FPGA) S1 – S4 FPZVS Converter Vo If

switching duration, which is 25 clock cycles in this design. If the diagonal pair, say S3 and S4, is turned on and off simultaneously, then the max Di is 96% (24/25), however, the zero voltage switching is lost and MOSFET’s experience a hard switching process. To ensure the ZVS process, there must be two transitions, the freewheeling and resonant respectively, between the turn-on of S3 and S4, both takes time to complete. During the freewheeling period, S2 and S3 are conducting immediately before and after the turn-on of S3. Followed by a resonant interval prior to turn-on S4. Referring to Fig.2 for the corresponding time (t5 – t2). In this design one clock cycle is allowed for each transition respectively, gives the minimum phase shift of two clock cycles and thus the maximum Ton of 22 clock cycles. The maximum Di is therefore 88% (22/25). 3.2 Design of the FPGA controller After programming, the compilation, synthesis and implementation of the written program are carried out under the Xilinx Foundation Series environment. A series of reports are produced by the software in different aspects at different stages. One report is issued after a successful compilation and synthesis of the VHDL program. Up to 8 reports are issued on successful implementation at different stages. By analyzing these reports, one can know whether or not the program achieves the design specifications before finalizing the hardware implementation. For instance, from the Map Report, the 2nd implementation report, it indicates that total number of logic gates up to 2604 are required. Consequently, the chip XC4005X with up to 5000 logical gates available is selected for this design. From the Post Layout Timing Report, the 7th implementation report, it is found that the propagation delay at the longest route formed in the device of the digital controller is 33.6 ns, corresponding to the maximum allowable frequency of 29.76 MHz. This is greater than the selected external clock frequency of 25 MHz for the XC4005X chip and is therefore satisfactory. The chip can run at synchronous system clock rates of up to 80 MHz, and internal performance can exceed 150 MHz. However, the device only supports 12-mA Sink Current Per Output, which is not sufficient high to drive the power MOSFET’s gate at the fsw of 500kHz, due to the MOSFET’s high input capacitance of 1300 pF. Therefore, a Totem Pole buffer of low output impedance is necessary to obtain required gate drive current.

Fig.3 The block diagram of the FPGA controlled system. On the calculation of the duty cycle Di, it is changed division by division at each control cycle. In this way the soft start-up is automatically ensured. The controller also provides total device and system overload protection due to its inherent current limitation. While the control algorithm employed is simple in this study, any upgrade is ready to be implemented by reconfiguring logic functions in the present system with a PC or other device through the standard X-Checker Adapter socket. Reference Gating Signal Generation Process Fixed gating signals S1 and S3 are generated in this process. They are used as the reference waveforms for gating signals S2 and S4 respectively. Unlike the hard switching method where the individual gating signal is symmetrical with a duty cycle of 50%, in the case of the soft switching, to ensure a zero voltage switching of the converter, the minimum turn-on delay time, Ton-min, between two switches of the same leg needs to be considered and is set at 40 ns in this design, corresponding to one cycle of the external clock frequency of 25 MHz (refer to Fig.3). This means that the turn-on duration takes 24 clock cycles against a turn-off duration of 26 ones, given a total clock cycles of 50 to cover one switching cycle of 500kHz. Thus the individual switching duty cycle is 48% (24/50), and is fixed for all four gating signals. Phase Shift Implementation Process During this process gating signals S2 and S4 are phase shifted with respect to S1 and S3 respectively. The amount of phase shift is based on the command duty cycle Di determined at each sampling cycle. The maximum Di needs to be specified for the controller. Generally, Di is defined as 2Ton /Tsw. Where Ton is the on-pulse overlap of the two diagonal switches, and Tsw /2 is one half of the

The throughput time of the controller is found approximate to the conversion time of the A/D converter, that is 193.8 kHz using the device MAX113 with two sampling channels in parallel operation. The control loop update can be significantly reduced by update the A/D converter to MAX1003, a dual device with a sampling rate of 90 MHz. A circuit schematic is translated from the program by the software. The circuit will actually be formed in a PLD. With the circuit schematic, the program can be debugged on the component level [8-10]. 4. SIMULATION OF THE CONTROLLER AND THE CONVERTER 4.1 Controller simulation Simulation of the FPGA controller is carried out at real time situation using Xilinx Foundation series environment, and results are given in Fig. 4(a). Where the top trace shows the input to the controller, that is the clock signal at 25 MHz, followed by four output gating signals S1 through S4 respectively. It can be seen that waveform of the gating signals are asymmetrical with a constant onpulse duration of 48% of the switching duration as expected. 4.2 Control system simulation Responses of the voltage and current of the model converter to the gating signals of Fig.4(a) are simulated using the simulation package MicroSim DesignLab, a PSpice type circuit simulator. Due to the limitation of the package, only the responses of the open-loop system is simulated. Nevertheless, both steady state and transient responses of the converter can be analyzed based on this work, and results are given in Fig.4(b) and (c) respectively. Fig.4 (b) gives the step response of the model converter up to 100 µs. From the top trace downwards, it shows waveforms of the primary voltage VAB, primary current Ip, secondary voltage Vs and output voltage Vo respectively.

Fig.4.(a) The post layout timing simulation results at 88% duty cycle.

Fig.4(b) Step response up to 100 µs.

Fig.4(c) Steady state portion of Fig.4(b) The steady-state portion of Fig.4 (b) is extended in Fig.4 (c) for 95µs ≤ t ≤ 100µs to give a clear view of waveforms. The output voltage ripple of 1MHz with a peak to peak value less than 50mV can be observed. This implies that the voltage error window, Vref – Vo of the controller should be set greater than 25 mV.

means that if the complexity of the control algorithm is increased it has little effect on the control loop time, however, more logic gates are required for the FPGA device to implement the control algorithm, consequently, the propagation time of the chip is expected to increase. By proper design it is possible for the FPGA controller to obtain combined merits of the analog and DSP type digital controller, makes it an ideal candidature for a high performance FPZVS converter. Fig.5 Switching patterns versus voltage of primary side. To confirm the zero voltage transition achieved by this design, the gating signals versus the steady state response of the primary voltage, VAB, are given in Fig.5, results are compared with the ZVS conditions. Regarding the ZVS conditions, with the switching sequence as shown, the leg A (left one in Fig.1) is the A-P leg, this means that immediately before and after the turn-on of S1 or S3, the converter is in a passive state when it is freewheeling, resulting in VAB of zero. That ZVS conditions are Prior to the turn-on of S1, VS1=0 and VAB = 0; Prior to the turn-on of S3, VS3=0 and VAB = 0; The leg B is the P-A leg, immediately before and after the turn-on of S2 or S4, the converter is in a active state and the power is transferred to the transformer secondary. Thus VAB is equal to the input supply VI, gives the ZVS conditions as below Prior to the turn-on of S2, VS2=0 and VAB =Vi; Prior to the turn-on of S4, VS4=0 and VAB = -Vi Although VDS is not shown in Fig.5, it can be derived from VAB which satisfy above ZVS conditions as depicted in Fig.5. This means that VSi =0 for i= 1, 2, 3 & 4 is met at the instant of turn on of each MOSFET, the ZVS operation is thus achieved. 5. CONCLUSION The design example of the FPGA digital controller and simulation results for both the controller and the converter are presented. The current mode control is applied which is ready to be replaced by an advanced control algorithm during the software programming. The control loop time is found approximate to the A/D conversion time, this 6. REFERENCE [1] M. Marx and D. Schroder ‘Analysis of a ZeroVoltage-Transition DC-DC Full-Bridge Converter’, IEEE Transactions on Power Electronics, pp. 298-303, 1995. [2] W. Chen, F.C. Lee, M. M. Jovanovic and J. A. Sabate, ‘A Comparative Study of a Class of Full Bridge Zero-Voltage-Switched PWM Converters’, IEEE Transactions on Power Electronics, pp. 893-899, 1995. [3] M. M. Walters and W. M. Polivka ‘A HighDensity Modular Power Processor for Distributed Military Power Systems’, Proc, APEC 1989, pp. 403-412, 1989. [4] R. Redl, N.O. Sokal and L. Balogh, ‘A Novel Soft-Switching Full-Bridge DC/DC Converter: Analysis, Design Considerations, and Experimental Results at 1.5 kW, 100 kHz’, IEEE Transactions on Power Electronics, Vol.6, No.3, pp.408-418, 1991. [5] L.H. Mweene, C. A.Wright and M.F. Schlecht, ‘A 1 kW 500kHz Front-End Converter for a Distributed Power Supply System’, IEEE Transactions on Power Electronics, Vol.6.NO.3.pp.398-407, 1991. [6] P. F. Kocybik and K. N. Bateson, ‘Digital Control of a ZVS Full-Bridge DC-DC Converter’, IEEE Transactions on Power Electronics, pp.687-693, 1995. [7] B. Andreycak, ‘Phase Shifted, Zero Voltage Transition Design Considerations and the UC3875 PWM Controller’, Product & Applications Handbook 1995-96, Unitrode Integrated Circuits Corporation. [8] Louis Baker, ‘VHDL Programming with Advanced Topics’, John Wiley and Sons, Inc., 1993. [9] Jayaram Bhasker, ‘A Guide to VHDL Syntax’, Prentice-Hall, Inc., 1995. [10] Simon S. Ang, ‘Power-Switching Converters’, Marcel Dekker, Inc., 1995.

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