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126 IEEE ELECTRON DEVICE LETTERS, VOL. EDL-2, NO.

5, MAY 1981

High-Performance Heat Sinking for VLSI


D. B. TUCKERMAN AND R. F. W. PEASE

Abstrucr-The problem of achieving compact, high-performance is an integral part of the silicon substrate, which exhibits a
forcedliquidcooling of planar integrated circuits has been In- maximum thermalresistance of O.WC/W over 1 cm2 area, and
vestigated. The convectiveheat-transfer coefficient h between the which has been tested up to 790 W/cmZ.
substrate and the coolant was found to be the primary impediment to
achieving low thermal resistance. For laminar flow in confined
channels, h scales inversely with channel width, making microscopic THEORY
channelsdesirable.Thecoolant viscosity determines the minimum
practicalchannelwidth. The use of high-aspect ratio channels to The performance of a heat sink is measured by its thermal
increasesurfaceareawill, to an extent, further reduce thermal resistance B = AT/Q , where AT is the temperature rise of the
resistance. Based on these considerations,anew, very compact, circuit above the inputcoolanttemperature (often room
water-cooled integral heat sink for silicon integrated circuits has been temperature)and Q is the dissipated power. In forced-
designed and tested. At a power density of 790 W/cm2, a maximum
convection cooling, 8 is nearly independent of power level.
substrate temperaturerise of 71°C above the input water temperature
was measured, in good agreement with theory. By allowing such high Because semiconductor ICstypically have maximum operating
power densities, the heat sink may greatly enhance the feasibility of temperatures of AT,,, = 50°C to 100°C above room tempera-
ultrahigh-speed VLSI circuits. ture, thermal resistance determines the maximum power at
which an IC can operate. In general 0 is the sum of three
IXTRODUCTION components: d c o n d , due to conduction fromthe circuits through
the substrate, package, and heat-sink interface; Bconv, due to
T HE advent of systems employing high-speed,high-density, convection fromthe heat sinkto the coolant fluid, and Ohcat, due
very-large-scale integrated (VLSI) circuits implies the re- to heating of the fluid as it absorbs energypassing through the
quirement for effective and compactheatremoval, For ex- heat exchanger. '
ample, high-speed digital circuits employing submicron chan- We can makeBcondvery small by locating the heat exchanger
nel lengths yet dissipating 1 mW per gate have been reported (containing the flowing coolant) very near to the heat source.
recently [l]. A VLSI circuit containing lo5 such gates would Fortunately silicon, the substrate used for most planarICs, has
thus dissipate 100 W. Conventional IC packages typically have a high thermal conductivity (kSi= 1.48 WjC-cm at 27°C for
thermal resistances of50'C:W and hencewould be totally lightly-doped Si; about 113 of copper's thermal conductivity)
unsuitable for such circuits. [SI. If an ICsubstrate is thinned to 100pm andits back sideis in
Although an isolated chip dissipating 100 W couldbe cooled intimate thermal contactwith the heat exchanger, thenOcond is
by forced-air convection, an arrayof such chips (closely spaced only 0.007'C/W for a 1-cm2 circuit.
to minimize propagation delays) presents a far more difficult We can reduce Oheat by using a coolant of high volumetric
cooling problem becauseof the large size ( 2 10 cm on aside) of heat capacity PC, at a sufficiently high flow rate f (Oheat =
high-performance forced-air heat exchangers. Liquid cooling 1/PC#. Water is a particularly good choice (PC,= 0.18 J , K -
promises to be a more compact arrangement and its use has cm3), with a modest flow rate of 10 cm3/s contributing only
been reported recently forcooling thecentral processing unit of 0.024"C;'W to the thermal resistance.
a large computing system [2]. In that system, heatis conducted Because Bcondand Oheat can be made very small by rather
through aluminumpistons spring-loaded onto the back of each obvious means, we expect that convective thermal resistance,
chip, through cylinder wallssurrounding the pistons, and into a B,,,, will be thedominantconsideration in high-performance
heatexchanger.Thethermal resistance of such apackage heat sink design. In fact a naive approach to liquid cooling in
allows a dissipation of about 3 or 4 W per chip. Even more which water simply flows over the back of a circuit substrate
compact configurationshave been proposed by integrating the can result in Bcony being orders of magnitude above the other
heat exchanger with the silicon chip [3]. thermal resistances. It is therefore necessary to examine some
There havebeen suggestions that physical limits of heat- aspects of convective heat-transfer theory [SI.
transfer technology will limit the power density of arrays of Consider acollection of n parallel channels eachof length L,
planar circuits to 20 W/cm2 orso [4]. In this letter we show that imbedded in a substrate of the same lengthL and width W.A
by scaling liquid-cooled heat-exchanger technology to micro- coolant flows in each channel, absorbing a constant heatflow
scopic dimensions, circuit power densities of more than loo0 per unit length Q /nL. from it walls (the substrate). For example,
W/cmZ should be feasible.To demonstrate these principles, we these channels mightbe etched directly in the back of a silicon
have constructed a,very compact water-cooled heat sink which IC chip. The use of many separate channels, rather than single
a
coolant flow over the entire back substratesurface, allows usto
Manuscript received March 10, 1981; revised March 3 1 , 1981.
The authors are with Stanford Electronics Laboratories, Stanford, CA
multiply the substrate surface area by a factor a. Specifically, we
94305. define cc=(total surface area of channel walls in contact with

0193-8576/81/0500-0l26$00.75 0 1981 IEEE


HIGH-PERFORMANCE
SINKING
PEASE:
HEATTUCKERMAN
AND FOR VLSI 127

TABLE I
Experimental values of maximum thermal resistance 0 max for three integral water-cooled silicon heat sinks of specified channel with w
and depthz , wall thickness w w,water pressureP,and flow rate f. The heated area was approximately ( 1 cm) X (1 cm), and the heat sinks
were tested up to a specified maximum power density Q.

Expt w,(Ctm) ww(Ctm) zf Ctm) P(psi) f(cm 3/s) e ,,,(~c/w) Q(wicrn2)

1 56 44 320 ’ 15 4.7 0.110 181


2 55 45 287 17 2176.5 0.113
3 50 50 302 31 8.6 0.090 790

fluid) P (area of circuit).At each cross-section along the length Thus we approximate h= ksNu,iD, where Nu, is be-
of the channel, we initially assume that the walls are infinitely tween 3 and 9. This result is consistent with an intuitive model
thermally conductive so thatthetemperature is uniform for convection in which the heat is conducted through the fluid
around theperimeter. The convective heat-transfer coefficient h to the middle of the channel: where it is transported away by the
is then defined as h = Q /nLp(T,- T,), where T , is the wall flow. Fora given coolant- fluid, clearly the only way to
temperature, T, is the mean fluid temperature, and p is the significantly increase h is to reduce D. Achievingveryhigh
cross-sectional perimeter. Then O,,,, = 1/hnLp = 1/ h d W , so values of h therefore requires channels of microscopic width.
that for a given circuit area LW, we clearly want to make bothh The only important lower limit on channel size is set by the
and a large. Whereas it is well known that the use of extended- coolant viscosity. For a given pump pressure, the volumetric
surface (large-a) structures such as finswill enhance heat flow rate decreases rapidly as D is reduced, resulting in an
transfer, the importance of making h large has receivedless increase in Ohea,. By assuming a practical limit on the available
attention. pressure, we can calcuiate an optimum channel size D which
It is customary to calculate h using dimensionless groups: minimizes the sumof O,,,, and Qhea,. A more fundamentallimit
on channel size occurs when the pumping power becomes
Nu = hD /kJ, the Nusselt number, a dimensionless heat-
comparable to the circuit power dissipation (and hence viscous
transfer coefficient;
heating becomes significant), but this qnly occurs at impracti-
Pr = p C p / k J ,the Prandtl number, aproperty of the fluid
cally high pressures.
(Pr = 6.4 for water at 23°C);
Increasing the channel aspect ratio (i.e., increasing x ) can
Re =z’Dp/p, the Reynolds number.
further reduce O,,,,,. However, we had assumed infinitely-
Here D is a “characteristic width” of the channel, defined as conductive channel walls; for a substrate with finite thermal
D = 4. (cross-sectional area) + (perimeter p). For high-aspect conductivity, there is little benefit in increasing x beyond the
ratio rectangular channels, D is equal to twice the channel point at which thermal resistance due to conduction along the
width. The terms p, k,, p , C,, and z’ denote respectively the length of the walls becomes comparable to convective thermal
viscosity, thermal conductivity, density, specific heat, and mean resistance.
velocity of the coolantfluid. Noting that the channel width D is
‘ likely to be small because the channels must be very closeto the
DESIGK
circuits to minimize Ocond we tentatively assume laminar flow (a
valid assumption when Re 5 2100). For calculating &u, we Figure 1 is a diagram of a high-performance IC heat sink
further assume that the flow is “fully-developed,”i.e.,invariant which embodies the principles just discussed. The front surface
along thechannel length (a good assumption if Pr 2 5: as is the of the substrate (length L, width W)contains a planar heat
case for most liquids). Then Nu is a monotonically decreasing source (the circuits), andthe back surface contains deep
function of x/(D.Re. Pr), where x is the distance from the rectangular channels of width w C and depth z whish carry the
entrance of the channel (0 5 x 5 L). Asymptotic formulas are: coolant, separated by walls of width w , ~ Neglecting
. the heat
transferred at the top and bottom of the channels, the surface-
area multiplication factor due to the channels is CI =2z/
Nu x (D.&, pr)-’,’3 for x/(D.Re.Pr) cz 0.02; ( w c + w,,).
A cover plate is bonded to the bask of the substrate
to confine the coolant to the channels. We will neglect Ocond in
Nu ‘v NU=, aconstant, for x:D.Re,Pr) 5 0.02 (“fully- our discussion, because it can be made very small independ-
developed temperature profile”). ently of O,,,, and cheat by making the substrate only slightly
thicker than the channel depth z.
Not knowing a priori which region we are in, we conservatively Recall that 8,,,, = l / h x LW= D/kfNu,xL W for infinitely
assume that Nu has the minimum, asymptotic (large x) value conductive walls. To account for a finite wall conductivity k ,
Nu,; in any case the dependence of Nu onx is weak. The exact (which implies a nonuniform temperatureup the walls), wecan
value of Nu, depends on the shapeof the channel cross section ’,
multiply by a correction factor 9- where q is known as the “fin
but is usually between 3 and 9. efficiency.” Approximating D as 2w), for high-aspect ratio
128 IEEE ELECTRON DEVICE LETTERS, VOL. EDL-2, NO, 5, MAY 1981

asymptoticallyapproachesa lowerlimit emin= wc/keflLW,


where kerf=,/--can be viewed as an effectivethermal
conductivity for the heat sink assembly. This result is signif-
cant: for it indicates the highest performance (lowest0) which we
can expect to achieve withliquid cooling (within the framework
of our model),given thechannelwidth andsubstrateand
coolantthermal conductivities. Fora water-cooled silicon
substrate withvery high-aspectratiochannels,k,,=0.13
WfC-cm. The maximum allowable circuit power density is
( Q / L w = (ATmaJkelf/wo which confirms that microscopically
narrow channelsare the key to efficient heat removal:if wc< 50
Cover PIote pm and AT,,,= 50T,then over 1300 W/cmZ canbe dissipated!
- IC Substrate Fora practical design, we choose an
aspect
ratio ac=
( e g Slllcon) .t;/k,/k,Nu,,forwhich N = l , y=O.76, and hence

Fig. 1. Schematic view of thecompactheat sink incorporatedintoan


integrated circuit chip. For a 1 cm* silicon IC using a water coolant, the
optimum aimensions are approximately w = w c 57 Ccm and z = 365
Ccm. Further increases inalpha would provide onlysmall reductions
in O,,,,, as it approaches emirReferring to equations 3 and 4
channels, we have and setting %=a,, wesee that @ h e a t varies as I V , - ~ and
7
i
varies as w C , hence an optimum channel width existswhich
Qcom = (W,% - l y - 1). minimizes their sum, 8:
kfKu, L W
I\', =2.29</pksL2 Nu,/pC,P.
We canget an analytical approximation for v by assuming a
constant heat-transfer coefficient 11 up the walls (a good for which
assumption providedy is not toosmall) and modelingthe heat
flow in the walls as one-dimensional:

For a water-cooled silicon heat sink on a (1 cm) x (1 cm)


substrate,awaterpressure of P = 30psi = 2.07 x lo6
where dynes/cm2, our design procedure gives:

w , = w ,= 57 pm;
2, = 6.4. so z = 365 pm,which conveniently is a typical
IC siliconwafer thickness!
0 = O.O86T/W at f= 11 cm3/s.
y is thus a monotonically decreasing functionof N. with v z 1 (We have used Nu,=6, which is about right for this aspect
for N e and qz.M-' for N > l . ratio). Note that L/(D.Re. Pr)=0.018 and Re=730 for our
As discussed, there will probably be some maximum pressure design, so our assumptions were self-consistent (laminar flow
P available to pump the coolant. The mean flow velocity ti in and an almost fully-developed temperature profile).
our high-aspect ratio channels can then be calculated, assuming
laminar flow between parallel plates: z: = wC2P/12pL. The total EXPERIMENTS
volume flow rate is easily seen to bef=$Ww,x, whence Using the precedingparameters as guidelines, we have
fabricated and tested several high-performance heatsinks. In a
series of experiments,' 50-pm wide channels with 50-ym wide
wallswere etched verticallyusing KOH (anorientation-
dependent etch) [7] to a depth of about 300 pm in (1 10) silicon
We seek an optimum choiceof design variables ww,wcrand R wafers of thickness 400pm.A Pyrex cover plate was anodically
whichminimizes the total thermal resistance Oconv(wW,wc: bonded [9] over the channelsand over a pair of etched
x ) + @heat(wc, x ) . Referring to equations B and 2, we see that for manifolds at the endsof the channel array. Deionized water at
any w, and a, we can minimize thermal resistance by maxi- approximately 23°C was fed into the input manifold through a
mizing v, which means w ,= w,. hole in the cover plate at pressures up to 31 psi, and drained
Bothand Bheat decreasemonotonically with increasing from the output manifold through a similar hole. Heat was
x , so there is no theoretical optimum value for a. However, the supplied by a thin-film WSi, resistor approximately (1 cm) x (1
fin
efficiency q rolls off as a- for large a, hence O,,,, cm) in area and 1 pm thick, which was sputtered onto the
OR
HIGH-PERFORMANCE
SINKING
PEASE:
HEATTUCKERMAN
AND VLSI 129

I I I ” ’ 9 I I I This termwould be exceedingly small (e 0.0l‘C:W) in a VLSI


circuit consistingof thousands of uniformly-distributed devices,
but it may be important in specialized ICs consisting of only a
few localized high-power heat sources.
The dramatic(forty-fold) improvement in practical,compact
IC heat-sinking capability presented here offers a new degreeof
freedomfor the systemdesigner. For example,speed-power
tradeoffs can now be resolved in favor of more speed, and in
particular ECL circuitry may now be a moreattractive
candidate for high-speedVLSI. The low thermal resistance may
also be useful formoderate-power ICs where the temperatures
of different components must match closely or be held close to
2 O 20 10 5 4 3 22 thecoolant temperature. Theincorporation of thisvery
compact integral heat sink into a conventional IC package is
WATER FLOW RATE f ( c r n 3 / s )
relatively straight forward.
Fig. 2 . Measuredvalues of maximum[downstream)thermalresistance
8 as a function of inverse flow rate lifforheatsinkno. 3ofTable 1.As
predicted, the datafallonastraightline,implyingfully-developed ACK~OWLEDGMENTS
temperature profiles. We would like to thank K. Bean of Texas Instruments, Inc.
and P. Barth, J. Beaudouin, W. Kays, J. Plummer?.K. Saraswat,
thermally-oxidized front surface of the wafer. Thermocouples J. Shott, and R.Swanson of Stanford University for their help.
monitored the temperatureof the input and outputwater and One of us (D.B.T.) wassupported by the Fannie and John Hertz
the heater resistor (the latter was measured near the Foundation. This work was partially supported by the Joint
downstreamend, where thetemperature is
highest). We Services Electronics Program.
confirmed that the flow rate obeyed Poiseuille’s equation and
that the thermal resistance was independent of powerlevel. REFERENCES
Table 1 summarizes the results obtained for three different heat R. K. Watts, W. Fichtner, E. N.Fuls, L. R . Thibault. and R . L.
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IEDM Technical Digest, pp. 772-775, 1980.
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