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Active Element and Grounded Passive Components

Jitendra Mohan1*, Sudhanshu Maheshwari2, Durg S. Chauhan3

1

Department of Electronics and Communications, Jaypee University of Information Technology,

Solan, India

2

Department of Electronics Engineering, Z. H. College of Engineering and Technology,

Aligarh Muslim University, Aligarh, India

3

Department of Electrical Engineering, Institute of Technology, Banaras Hindu University,

Varanasi, India

E-mail: jitendramv2000@rediffmail.com

Received April 23, 2010; revised May 27, 2010; accepted June 2, 2010

Abstract

In this paper, four new first order voltage mode cascadable all-pass sections are proposed using single active

element and three grounded passive components, ideal for IC implementation. The active element used is a

fully differential current conveyor. All the proposed circuit possess high input and low output impedance

feature which is a desirable feature for voltage-mode circuits. Non-ideality aspects and parasitic effects are

also given. As an application, a multiphase oscillator is designed. The proposed circuits are verified through

PSPICE simulation results using TSMC 0.35 µm CMOS parameters.

high input impedance but uses two active element and

Voltage mode (VM) active filters with high-input and three grounded passive components. Some of the circuits

low-output impedance are of great interest because seve- described in [15,21-23] fall in the separate category of

ral cells of this kind can be directly connected in cascade tunable, resistorless realizations, the most recent of these

within voltage-mode systems without additional voltage [22,23] enjoys high input and/or low output impedance.

buffers. On the other hand, the use of grounded capacitor A recent published all-pass filter circuit in [24] employ

is beneficial from the point of integrated circuit imple- two DVCCs and two passive components with the ad-

mentation and also having less parasitic compared to vantage of high input impedance and low output imped-

floating counterparts [1]. ance, which is ideal for cascading, but it still suffer from

First order all-pass filters are an important class of ana- floating resistor. But a careful survey reveals that none of

logue signal processing circuits which have been exten- the reported works realizes a VM-APS using single ac-

sively researched in the technical literature [2,3] due to tive element, grounded passive components, and also

their utility in communication and instrumentation sys- providing high input impedance and low output imped-

tems, for instance as a phase equalizer, phase shifter or ance features simultaneously.

for realizing quadrature oscillators band pass filters etc. This paper proposes four new first order VM cascad-

Numerous first-order voltage-mode all-pass sections (VM- able all-pass sections, with high input and low output

APSs) employing different types of active element such impedance using single active element and three grounded

as current conveyors and its different variations have passive components, which are ideal for IC implementa-

been reported in the literature [4-24]. Among the cited tion. Each circuit employs two grounded resistors and

references, several VM-APSs employ a single standard one grounded capacitor. The proposed circuits are based

current conveyor [6-16,19-22]. Such circuits aim at reali- on fully differential second generation current conveyor

zing the first order all-pass function using optimum num- (FDCCII), an active element to improve the dynamic

ber of passive components, rather using grounded compo- range in mixed mode application, where fully differential

nents or offering high input and low output impedance signal processing is required [25]. As an application, the

6 J. MOHAN ET AL.

proposed circuit realizes a multiphase oscillator. PSPICE are shown in Figure 1 [25]. The Y1, Y2, Y3, and Y4 termi-

simulation results using TSMC 0.35 μm CMOS parameters nals are high-impedance terminals, while X+ and X– ter-

are given to validate the circuits. minals are low-impedance ones. The Z+ and Z– terminals

The paper is organized as follows: in Section 2, the pro- are high impedance nodes suitable for current outputs.

posed all-pass filters using FDCCII are presented. In FDCCII is a useful and versatile active element for ana-

Section 3, parasitic and non-ideal analyses of the pro- log signal processing. The applications of FDCCIIs in

posed circuits are given. In Section 4, to verify the theo- filters and oscillators design using only grounded passive

retical study the first order all-pass filters were con- components were demonstrated in [26,27].

structed and simulated with PSPICE program. In Section The voltage transfer function of an all-pass filter can

5, a multi- phase oscillator is implemented to show the be given as

usefulness of the proposed circuits as an illustrating ex- VOUT sτ - 1

ample and finally the conclusion in Section 6. =K (2)

VIN sτ - 1

where K is the gain constant and its sign determines whe-

2. Proposed Circuit ther phase shifting is from 0° to –180° or from 180° to 0°,

and τ is the time constant. The four proposed first order

The FDCCII is an eight terminal analog building block VM cascadable all-pass sections using a single FDCCII

with a describing matrix equation of the form [25] and three grounded passive components are shown in

Figures 2(a)-2(d). The four circuits in Figures 2 (a)-2(d)

IY 1 0 0 0 0 0 0 0 0 VY 1 are characterized by the voltage transfer function as

I 0 0 0 0 0 0 0 0 VY 2

Y2 VOUT s (1/ C1 )[(1/ R2 ) (1/ R1 )]

IY 3 0 0 0 0 0 0 0 0 VY 3 = K (3)

VIN s + (1/ R1C1 )

IY 4 0 0 0 0 0 0 0 0 VY 4

V 1 1 1 0 0 0 0 0 I X + (1) For R2 = R1/2 Equation (3) becomes

X+

VX - 1 1 0 1 0 0 0 0 I X - VOUT sR C -1

=K 1 1 (4)

I 0 0 0 0 1 0 0 0 VZ + VIN sR1C1 +1

Z+

I Z - 0 0 0 0 0 1 0 0 VZ - where the value of K = +1 for Circuit-I and Circuit-II

(Figures 2(a) and 2(b)) and the value of K = –1 for Cir-

The symbol and CMOS implementation of FDCCII cuit-III and Circuit-IV (Figures 2 (c) and 2(d)).

IY1

Y1 IZ+

IY2 Z+

Y2

IY3 IZ-

Y3 FDCCІІ Z-

IY4

Y4

X+ X-

IX+ IX-

(a)

VDD

M7 M8 M9

M13

M14 M18 M22

a b

M27 M29

M33

M19 M30

M15 Vbp Vbp M34

IB

IZ+ IX+ X+ X-

IX- IZ-

M25 Z+

M3 M4 Y3 Y1 M1 M2 Y2 Y4 M5 M6 Z-

M26 M16 Vbn

M24 M10 M11 M12

M17 M21 M32 M36

ISB M23

M28

VSS

(b)

Figure 1. Fully differential second generation current conveyor (a) symbol (b) CMOS implementation [25].

J. MOHAN ET AL. 7

Y1 Z+ VIN Y1 Z+ VIN Y1 Z+ Y1 Z+

VIN Y2 Y2 Y2 R1 C1 VIN Y2

FDCCІІ R1 C1 FDCCІІ FDCCІІ FDCCІІ

Y3 Z- Y3 Z- Y3 Z- Y3 Z-

Y4 Y4 R1 C1 Y4 Y4

X+ X- X+ X- X+ X- R1 C1

X+ X-

VOUT VOUT R2 R VOUT VOUT

R 2 2 R2

Figure 2. Proposed first order cascadable all-pass filters (a) circuit-I; (b) circuit-II; (c) circuit-III and (d) circuit-IV.

The salient features of the four proposed circuits are deviation in circuit’s parameters, which can be elimi-

high input and low output impedance, single active ele- nated by pre-distorting the element values to be used

ment and use of grounded passive components; the three in the circuit. It is seen that the pole-frequency would

features are not exhibited together in any of the available be slightly deviated (in deficit) due to these parasitics.

works, including the most recent circuits [4-24]. It may The deviation is expected to be small for an integrated

be noted that the new circuits are based on a topology FDCCII; the actual value would be given in the ‘simula-

with input at Y and output at one of the X terminals, the tion results’.

other X-terminal being terminated by a resistor. The four

proposed circuits with similar properties being derivable 3.2. Non-Ideal Analysis

from a topology are a result of the versatility of FDCCII.

It is also worth mentioning that four additional new Taking the non-idealities of the FDCCII into account, the

circuits can further be obtained from the proposed cir- relationship of the terminal voltages and currents can be

cuits by replacing the resistor (R2) with a capacitor (C2). rewritten as

However these circuits would employ a capacitor at X

terminal, thus degrading high frequency operation. This IY 1 0 0 0 0 0 0 0 0 VY 1

aspect will not be further elaborated for brevity reasons. I 0 0 0 0 0 0 0 0 VY 2

Y2

IY 3 0 0 0 0 0 0 0 0 VY 3

3. Parasitic and Non-Ideal Analysis

IY 4 0 0 0 0 0 0 0 0 VY 4

VX + 1 2 3 0 0 0 0 0 I X +

3.1. Parasitic Effects

VX - 4 5 0 6 0 0 0 0 I X -

A study is next carried out on the effects of various para- I 0 0 0 0 1 0 0 0 VZ +

Z+

sitic of the FDCCII used in the proposed circuits. These 2

I Z - 0 0 0 0 0 0 0 VZ -

are port Z parasitic in form of RZ//CZ, port Y parasitic in

form of RY//CY and port X parasitic in form of series re- (7)

sistance RX [13]. The proposed circuits are reanalyzed where αi (i = 1, 2) accounts for current transfer gains and

taking into account the above parasitic effects. The volt- βi (i = 1, 2, 3, 4, 5, 6) accounts for voltage transfer gains

age transfer function (assuming R << RY or RZ and RX <<

of the FDCCII. These transfer gains differ from unity by

R), for the circuits of Figures 2(a)-2(d), is given as

the voltage and current tracking errors of the FDCCII.

VOUT s (1/ (C1 CP ))[(1/ R ') (1/ R1 )] More specifically, αi = 1 – δi, (|δi| << 1) δ1 is the current

= K (5) tracking error from X+ to Z+ and δ2 is the current track-

VIN s + (1/ R1 (C1 CP ))

ing error from X– to Z–. Similarly, βi = 1 – εi, (|εi| << 1)

where, R′ = R2 + RX, (for Figures 2(a)-2(d)), K = +1, (for where, voltage tracking errors are ε1 (from Y1 to X+), ε2

Figures 2(a) and 2(b)), K = –1, (for Figures 2(c) and (from Y2 to X+), ε3 (from Y3 to X+), ε4 (from Y1 to X–), ε5

2(d)), and CP = CZ+ + CY4 (for Figures 2(a) and 2(c)), (from Y2 to X–), and ε6 (from Y4 to X–). The circuits of

and CP = CZ- + CY3 (for Figures 2(b) and 2(d)). Figures 2(a)-2(d) are reanalyzed using (7) and the

From (5), it is seen that the gain is unity and the non-ideal voltage transfer functions are found as

pole-frequency is Circuit-I:

1

ωo (6) VOUT s [(1 2 6 R1 5 R2 ) / 5C1 R1 R2 ]

R1 (C1 + CP ) 5 (8)

VIN s (1/ C1 R1 )

From (5), the parasitic resistance/capacitances merge

with the external value. Such a merger does cause slight Circuit-II:

8 J. MOHAN ET AL.

1 (9) frequency was 1.59 MHz. The phase and gain plots are

VIN s (1/ C1 R1 ) shown in Figure 3. The phase is found to vary with fre-

Circuit-III: quency from 180° to 0° with a value of 90° at the pole fre-

quency, and the pole frequency was found to be 1.54 MHz,

VOUT s [(1 1 6 R1 4 R2 ) / 4 C1 R1 R2 ] which is close to the theoretical value. The circuit was

4 (10)

VIN s (1/ C1 R1 ) next used as a phase shifter introducing 90° shift to a

sinusoidal voltage input of 1 Volt peak at 1.59 MHz. The

Circuit-IV: input and output waveforms are given in Figure 4 which

VOUT s [( 2 3 5 R1 2 R2 ) / 2 C1 R1 R2 ] verify the circuit as a phase shifter. The THD variation at

2 (11) the output for varying signal amplitude at 1.59 MHz was

VIN s (1/ C1 R1 ) also studied and the results shown in Figure 5. The THD

From (8)-(11), it is seen that the pole-frequency is un- for a wide signal amplitude (few mV-1V) variation is

altered by FDCCII non-idealities for all the transfer func- found within 4.27% at 1.59 MHz. The Fourier spectrum

tions of the respective circuit, but the filters gain are of the output signal, showing a high selectivity for the

slightly modified due to the FDCCII non-idealities. Thus applied signal frequency (1.59 MHz) is also shown in

the pole-frequency sensitivity to the FDCCII nonideali- Figure 6. Both theoretical and simulated pole frequen-

ties is zero, and the filters gain sensitivity to these non- cies are found to closely match; the discrepancy (deficit)

idealities is found within unity in magnitude. This sug- in simulated frequency being the result of various para-

gests a good sensitivity performance for the proposed sitic discussed in Section 3.

circuits.

Table 2. Transistor aspect ratios for the circuit shown in

Figure 1.

4. Simulation Results

Transistors W(µm) L(µm)

To verify theoretical result the proposed filter circuits

were simulated by the PSPICE simulation program. The M1-M6 60 4.8

FDCCII was realized based on the CMOS implementa- M7-M9, M13 480 4.8

tion as shown in Figure 1 [25] and simulated using M10-M12, M24 120 4.8

TSMC 0.35 μm, level 3 MOSFET parameters as listed in M14,M15,M18,M19,M25,M29,M30,M33,M34 240 2.4

Table 1. The aspect ratio of the MOS transistors are listed M16,M17,M20,M21,M26,M31,M32,M35,M36 60 2.4

in Table 2, with the following DC biasing levels Vdd = M22,M23,M27,M28 4.8 4.8

–Vss = 3.3 V, Vbp = Vbn = 0 V, and IB = ISB = 1.7 mA. The

circuit-I (Figure 2(a)) was designed with C1 = 50 pF,

40

1 2

Table 1. 0.35 μm level 3 MOSFET parameters. 150d

20

Phase (degree)

Gain (dB)

NMOS: 100d

0

LEVEL = 3 TOX = 7.9E – 9 NSUB = 1E17 50d -20

GAMMA = 0.5827871 PHI = 0.7 VTO = 0.5445549 DELTA = 0

SEL>>

UO = 436.256147 ETA = 0 THETA = 0.1749684 0d -40

KP = 2.055786E – 4 VMAX = 8.309444E4 KAPPA=0.2574081 10KHz 100KHz 1.0MHz 10MHz 100MHz

LD = 3.162278E – 11 WD = 7.04672E – 8 CGDO = 2.82E – 10

Figure 3. Gain and phase responses for the circuit-I.

CGSO = 2.82E – 10 CGBO = 1E – 10 CJ = 1E – 3 PB = 0.9758533

MJ = 0.3448504 CJSW = 3.777852E – 10 MJSW = 0.3508721

2.0v

PMOS:

Output Input

LEVEL = 3 TOX = 7.9E – 9 NSUB = 1E17

Amplitude

0v

DELTA = 0 UO = 212.2319801 ETA = 9.999762E – 4

THETA = 0.2020774 KP = 6.733755E – 5 VMAX = 1.181551E5

KAPPA = 1.5 RSH = 30.0712458 NFS = 1E12 TPG = –1 SEL>>

XJ = 2E – 7 LD = 5.000001E – 13 WD = 1.249872E – 7 -2.0v

CGDO = 3.09E – 10 CGSO = 3.09E – 10 CGBO = 1E – 10 0s 0.5us 1.0us 1.5us 2.0us 2.5us

CJ = 1.419508E – 3 PB = 0.8152753 MJ = 0.5 Time

CJSW = 4.813504E – 10 MJSW = 0.5 Figure 4. Input/output waveshapes for Circuit-I at 1.59 MHz.

J. MOHAN ET AL. 9

6 0d 40

1 2

-50d 20

Phase (degree)

Gain (dB)

4 0

THD (%)

-100d

-20

SEL>>

2 -180d -40

10KHz 100KHz 1.0MHz 10MHz 100MHz

Frequency

0 Figure 7. Gain and phase responses for the circuit-III.

0.1 1 10 100 1000

VIN (mV)

2.0v

Figure 5. THD variation at output with signal amplitude at

1.59 MHz. Input Output

Amplitude

1.0v 0v

SEL>>

0.5v -2.0v

0.5us 1.0us 1.5us 2.0us 2.5us 3.0us

Time

0v

0Hz 4MHz 8MHz 12MHz

V(1) V(4) Frequency

Y1 Z+

Similarly, the circuit-III (Figure 2(c)) was designed

with the same values and frequency as above. The phase Y2 R1 C1

FDCCІІ

and gain plots are shown in Figure 7. The phase is found Y3

to vary with frequency from 0 to –180° with a value of

–90° at the pole frequency, and the pole frequency was Y4 Z- VOUT3

found to be 1.54 MHz, which is close to the theoretical X+ C’

X-

value. The circuit was next used as a phase shifter intro- VOUT1 VOUT2

ducing –90° shift to a sinusoidal voltage input of 1 Volt R2 R’

peak at 1.59 MHz. The input and output waveforms

are given in Figure 8 which verify the circuit as a phase

shifter. Figure 9. Multiphase oscillator using Circuit-I of Figure 2(a).

5. Application Example 1 1 R1 R2

s2 s 0 (12)

C1 R1 C ' R ' C1C ' R1 R2 R '

To further illustrate the utility of the proposed circuits a

sinusoidal oscillator producing a number of quadrature At the frequency of oscillation, with s = jω, the Equa-

signals was realized using the Circuit-I (Figure 2(a)). By tion (5) gives the frequency of oscillation (FO) and con-

connecting Y2 terminal, the input node to the Z-terminal dition of oscillation (CO) as

of FDCCII, connecting resistor (R′) and capacitor (C′) at R1 R2

X– and Z– terminals of FDCCII. The resulting circuit is FO : ωO ; CO: C′R′ ≥ C1R1 (13)

C1C ' R1 R2 R '

shown in Figure 9. The circuit analysis yields the fol-

lowing characteristic equation Assuming R′ = R1 = 2R2; C′ = C1

10 J. MOHAN ET AL.

FO : ωO

1

(14)

7. Acknowledgements

2C ' R '

From Figure 9, at oscillating frequency the circuit pro- The authors would like to thank the anonymous review-

vides three quadrature voltage outputs (VOUT1, VOUT2 and ers for their valuable comments.

VOUT3) whose phasor relationship is shown in Figure 10.

The circuit was designed with C1 = C′ = 50 pF, R1 = R′ 8. References

= 2 kΩ, and R2 = 1 kΩ, the theoretical frequency of os-

cillation was around fo = 1.59 MHz, whereas the simu- [1] M. Bhusan and R. W. Newcomb, “Grounding of Capaci-

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