You are on page 1of 59

A B C D E

1 1

LCFC Confidential

l
ACLUA M/B Schematics Document

tia
2 2

Intel Haswell/Broadwell U-Processor with DDRIIIL + NV (N15V-GM/N15S-GT) GPU

en
fid
2013-12-26
REV:0.3
3
on 3
C

4 4

Security Classification LC Future Center Secret Data Title


Issued Date 2013/08/08 Deciphered Date 2013/08/05 Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLUA
Date: Thursday, December 26, 2013 Sheet 1 of 59
A B C D E

PDF created with pdfFactory Pro trial version www.pdffactory.com


A B C D E

LCFC confidential File Name : ACLUA

NV (N15V-GM/N15S-GT)
GB2B-64 Package PCI-Express
Page 18~28 PCIe Port5
4x Gen2 Memory BUS (DDR3L)
Dual Channel DDR3L-SO-DIMM X2
Page 14,15
VRAM 256/128*16
1
1.35V DDR3L 1600 MT/s 1

DDR3L*8 4GB/2GB/1GB UP TO 8G x 2
Page 24~27

HDMI USB Left


HDMI Conn.
Page 34 USB 3.0 1x
USB 3.0 Port1
USB 2.0 Port1
DP to VGA DPx2 Lane USB 2.0 2x
VGA Conn.
Page 36 Page 35 Parade PS8613 Intel MCP USB 2.0 Port2
Page 41

l
eDP x2 Lane
eDP Conn

tia
USB 2.0 1x Touch Screen
USB2.0 1x
Int. Camera Page 33 USB2.0 Port4
USB2.0 Port5

2
Haswell U 15W / 2

Int. MIC Conn. Broadwell U 15W

en
Page 33
USB2.0 1x USB Right
USB2.0 Port0
SATA HDD SATA Gen3
Page 42 SATA Port0 USB2.0 1x
BGA-1168 Cardreader Realtek SD/MMC Conn.
40mm*24mm RTS5170 USB2.0 Port3

fid
SATA ODD SATA Gen1 USB Board
Page 42 SATA Port1

USB 2.0 1x
LAN Realtek NGFF Card
RJ45 Conn. PCIe 1x PCIe 1x WLAN&BT
Page 38
RTL8111GUL (1G) PCIe Port4

3
RTL8106EUL (10M/100M)
Page 37 PCIe Port3
on Page 40 USB2.0 Port6

Sub-board ( for 14")


3

HD Audio SPI BUS SPI ROM


Page 3~13
8MB Page 07 POWER BOARD

Codec SPI ROM 4MB USB Board


SPK Conn. for reserve
C
Conexant CX20752 Page 07
Page 43
Page 43

EC
ITE IT8586E-LQFP Sub-board ( for 15")
Page 44

HP&Mic Combo Conn. POWER BOARD

USB Board USB Board


Touch Pad Int.KBD Thermal Sensor
4 Page 45 Page 45 NCT7718W 4
Page 39
ODD Board

Security Classification LC Future Center Secret Data Title


Issued Date 2013/08/08 Deciphered Date 2013/08/05 Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLUA
Date: Thursday, December 26, 2013 Sheet 2 of 59
A B C D E

PDF created with pdfFactory Pro trial version www.pdffactory.com


A B C D E

Voltage Rails ( O --> Means ON , X --> Means OFF )


SIGNAL
+5VS STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
+3VS
Power Plane Full ON HIGH HIGH HIGH HIGH ON ON ON ON
+1.5VS
+1.35VS S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
1
+1.05VS 1
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
+3VALW +0.675VS
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
B+ +3VALW_PCH CPU_CORE

+5VALW +1.35V S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF

+VGA_CORE
State +3VGS
+1.8VGS
+1.35VGS
+0.95VGS
USB Port Table BOM Structure Table
USB 2.0 USB 3.0
BOM Structure BTO Item
EHCI1 XHCI Not stuff
@

l
S0 O O O O O 0 USB Port (Right Side) 14@ For 14" part

tia
15@ For 15" part
1 USB Port1 (Left Side) 1 USB Port1 (Left Side) 100M LAN Part
100M@
S3 O O O O X 2 USB Port2 (Left Side) 2 GIGA@ GIGA LAN Part
2 OPT@ Discrete GPU SKU part 2
3 Cardreader 3
N15SGT@ For N15S-GT GPU part
S3
Battery only O O O O X 4 TOUCH PANEL 4 N15VGM@ For N15V-GM part

en
GC6@ GC62.0 support part
5 Camera For VRAM RankA part
RANKA@
6 NGFF(WLAN) RANKB@ For VRAM RankB part
S5 S4/AC Only O O O X X UMA@ UMA SKU part
7 For support touch panel sku part
TS@
S5 S4 AOAC@ AOAC support part
Battery only O X X X X ME@ ME part(connector, hole)

fid
S5 S4
AC & Battery X X X X X
don't exist
PCIE PORT LIST
SMBUS Control Table Port Device
3

SOURCE VGA BATT IT8586E SODIMM


WLAN
WiMAX
on
Thermal
Sensor
PCH TP
Module charger
1
2
3

3 LAN
4 WLAN
EC_SMB_CK1 IT8586E V 5 Discrete GPU
EC_SMB_DA1 +3VALW X V +3VALW X X X X X V
6
C
EC_SMB_CK2 IT8586E V V
X X V V X X
EC_SMB_DA2 +3VS +3VGS X +3VS +3VS +3VALW_PCH

PCH_SMB_CLK PCH
PCH_SMB_DATA +3VALW_PCH X X X V V X V X X
+3VS +3VS +3VALW_PCH

EC SM Bus1 address EC SM Bus2 address PCH SM Bus address


Device Address
Device Device Address DDR DIMMA 1010 000Xb
4 4
Smart Battery 0X16 Thermal Sensor NCT7718W 1001_100xb DDR DIMMB 1010 010Xb
Charger 0001 0010 b VGA 0x41(default) Wlan Rsvd
PCH need to update

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Notes List


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLUA
Date: Thursday, December 26, 2013 Sheet 3 of 59
A B C D E

PDF created with pdfFactory Pro trial version www.pdffactory.com


5 4 3 2 1

UC1A HSW_ULT_DDR3L

HDMI_TX2- C54 C45 CPU_EDP_TX0-


34 HDMI_TX2- DDI1_TXN0 EDP_TXN0 CPU_EDP_TX0- 33
HDMI D2 HDMI_TX2+ C55 B46 CPU_EDP_TX0+
D 34 HDMI_TX2+ DDI1_TXP0 EDP_TXP0 CPU_EDP_TX0+ 33
HDMI_TX1- B58 A47 CPU_EDP_TX1- D
34 HDMI_TX1- DDI1_TXN1 EDP_TXN1 CPU_EDP_TX1- 33
HDMI D1 HDMI_TX1+ C58 B47 CPU_EDP_TX1+
34 HDMI_TX1+ DDI1_TXP1 EDP_TXP1 CPU_EDP_TX1+ 33
HDMI_TX0- B55
34 HDMI_TX0- DDI1_TXN2
HDMI D0 HDMI_TX0+ A55 C47
34 HDMI_TX0+ DDI1_TXP2 EDP_TXN2
HDMI_CLK- A57 C46
34 HDMI_CLK- DDI1_TXN3 EDP_TXP2
HDMI CLK HDMI_CLK+ B57 A49
34 HDMI_CLK+ DDI1_TXP3 EDP_TXN3
DDI EDP B49
VGA_TX0- C51 EDP_TXP3
35 VGA_TX0- DDI2_TXN0
VGA_TX0+ C50 A45 CPU_EDP_AUX# +VCCIOA_OUT +VCCIOA_OUT & EDP_COMP :
35 VGA_TX0+ DDI2_TXP0 EDP_AUXN CPU_EDP_AUX# 33
DP TO VGA Converter VGA_TX1- C53 B45 CPU_EDP_AUX Trace Width: 20mil
35 VGA_TX1- DDI2_TXN1 EDP_AUXP CPU_EDP_AUX 33
VGA_TX1+ B54
35 VGA_TX1+ DDI2_TXP1 Space: 25mil
C49 D20 EDP_COMP RC1 1 2 24.9_0402_1%
B50 DDI2_TXN2 EDP_RCOMP A43 LCD_BKLT_CTRL_R RC2 1 @ 2 0_0402_5% Max length: 100mil
DDI2_TXP2 EDP_DISP_UTIL INVT_PWM 33
A53
B53 DDI2_TXN3
DDI2_TXP3

1 OF 19
HASWELL-ULT-DDR3L_BGA1168

l
tia
+3VS

RPC19
DDPC_CLK 1 8
DDPC_DATA 2 7
DDPB_CLK 3 6
UC1I HSW_ULT_DDR3L 4 5
DDPB_DATA

C 2.2K_0804_8P4R_5% C

PCH_EDP_PWM B8 B9 DDPB_CLK DDPx_CTRLDATA


33 PCH_EDP_PWM EDP_BKLCTL DDPB_CTRLCLK DDPB_CLK 34
PCH_ENBKL A9 C9 DDPB_DATA DDPB_DATA 34 The signal has a weak internal pull-down.
33 PCH_ENBKL

en
PCH_ENVDD C6 EDP_BKLEN eDP SIDEBAND DDPB_CTRLDATA D9 DDPC_CLK
33 PCH_ENVDD EDP_VDDEN DDPC_CTRLCLK
DDPC_CTRLDATA
D11 DDPC_DATA * H
L
Port is detected.
Port is not detected.

PCI_PIRQA# U6
PCI_PIRQB# P4 PIRQA/GPIO77 C5
PCI_PIRQC# N4 PIRQB/GPIO78 DDPB_AUXN B6 VGA_AUX#
PIRQC/GPIO79 DDPC_AUXN VGA_AUX# 35
PCI_PIRQD# N2 DISPLAY B5
@ PAD 1 AD4 PIRQD/GPIO80 DDPB_AUXP A6 VGA_AUX
TC1 PME PCIE DDPC_AUXP VGA_AUX 35
BOARD_ID3 U7
9 BOARD_ID3 GPIO55
GPIO52 L1
19 GPIO52 GPIO52
PXS_PWREN RC7 1 OPT@2 1K_0402_5% PXS_PWREN_R L3 C8 HDMI_HPD
21,58 PXS_PWREN GPIO54 DDPB_HPD HDMI_HPD 34

fid
PXS_RST# RC8 1 OPT@2 0_0402_5% PXS_RST#_R R5 A8 VGA_HPD
19 PXS_RST# GPIO51 DDPC_HPD VGA_HPD 35
GPIO53 L4 D6 EDP_HPD
19 GPIO53 GPIO53 EDP_HPD

1
RC37 After confirm with vendor, HPD
1

D 9 OF 19 100K_0402_5%
RC170 1 @ 2 2 QC13 HASWELL-ULT-DDR3L_BGA1168 @
has internal pull-down ~100K at
44 VGA_GATE# G PS8613, just reserve in case.
0_0402_5% 2N7002KW_SOT323-3

2
1 RC37 can be removed next phase
CC96 @ S
if no issue.
3

.1U_0402_10V6-K
@

B
2
on B

+3VS +3VS

1
RC9

2
+3VS 1M_0402_5%

G
@

2
RPC1
C
1 8 PCI_PIRQA# EDP_HPD @ 3 1 QC4 CPU_EDP_HPD 33

D
2 7 PCI_PIRQB#
3 6 PCI_PIRQC# 2N7002KW_SOT323-3
4 5 PCI_PIRQD#

1
10K_0804_8P4R_5% RC13
100K_0402_5%

+3VS @

2
RC16 1 2
N15VGM@
RC10 1 2 10K_0402_5% GPIO52 0_0402_5%

RC11 1 2 10K_0402_5% GPIO53

RC14 1 2 10K_0402_5% PXS_PWREN_R

RC15 1 @ 2 10K_0402_5% PXS_RST#_R

A A
Reserve for NV GPU
RC27 1 @ 2 10K_0402_5% GPIO52

RC30 1 @ 2 10K_0402_5% GPIO53

Security Classification LC Future Center Secret Data Title


RC17 2 @ 1 100K_0402_5% PXS_PWREN_R

RC18 2 1 100K_0402_5% PXS_RST#_R


Issued Date 2013/08/08 Deciphered Date 2013/08/05 MCP (DDI,EDP)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLUA
Date: Thursday, December 26, 2013 Sheet 4 of 59
5 4 3 2 1

PDF created with pdfFactory Pro trial version www.pdffactory.com


5 4 3 2 1

UC1B HSW_ULT_DDR3L

+1.05V_VCCST

TC2 @ 1 PROC_DETECT# D61


PROC_DETECT

1
D TC3 @ 1 CATERR# K61 MISC D
RC19 H_PECI N62 CATERR J62 XDP_PRDY# 1 PAD @
44 H_PECI PECI PRDY TC4
62_0402_1% K62 XDP_PREQ# 1 PAD @
PREQ TC5
E60 XDP_TCLK 1 PAD @
PROC_TCK E61 1 TC6
XDP_TMS PAD @
TC7

2
56_0402_5% 1 2 RC20 H_PROCHOT#_R K63 JTAG PROC_TMS E59 XDP_TRST# 1 PAD @
44,51,52 H_PROCHOT# PROCHOT PROC_TRST TC8
THERMAL F63 XDP_TDI 1 PAD @
PROC_TDI TC9
F62 XDP_TDO 1 PAD @
PROC_TDO TC10
+1.35V 1 2 RC21 CPU_PROCPWRGD C61
10K_0402_5% PROCPWRGD PWR
J60 XDP_BPM0# 1 PAD @
BPM#0 TC11

1
H60 XDP_BPM1# 1 PAD @
BPM#1 TC12
RC22 H61 XDP_BPM2# 1 PAD @
BPM#2 H62 1 TC13
470_0402_5% XDP_BPM3# PAD @
BPM#3 TC14
SM_RCOMP_0 AU60 K59 XDP_BPM4# 1 PAD @
SM_RCOMP0 DDR3L BPM#4 TC15
SM_RCOMP_1 AV60 H63 XDP_BPM5# 1 PAD @
TC16

2
SM_RCOMP_2 AU61 SM_RCOMP1 BPM#5 K60 XDP_BPM6# 1 PAD @
SM_RCOMP2 BPM#6 TC17
RC23 1 2 0_0402_5% CPU_DRAMRST#_R AV15 J61 XDP_BPM7# 1 PAD @
14,15 CPU_DRAMRST# AV61 SM_DRAMRST BPM#7 TC18
@ SM_PG_CNTL1
SM_PG_CNTL1
1
CC1 2 OF 19
0.01U_0402_25V7K HASWELL-ULT-DDR3L_BGA1168

l
2
C C

tia
100_0402_1% 2 1 RC24 SM_RCOMP_2

121_0402_1% 2 1 RC25 SM_RCOMP_1


+3VALW
200_0402_1% 2 1 RC26 SM_RCOMP_0

en
1
RC28
100K_0402_5%

2
CPU_DRAMPG_CNTL 55
+1.35V
B B

1
C +1.35V

fid
RC3 1 2 2 QC14
1K_0402_5% B
E

3
MMBT3904WH_SOT323-3 1 QC5
D
RC31 1 2 0_0402_5% 2
SM_PG_CNTL1 @ G
1 S
CD1 PJA138K_SOT23-3 RD1 1 2 66.5_0402_1% DDRA_ODT0
3 DDRA_ODT0 14
2

.1U_0402_10V6-K
RC29 @ DDR_ODT RD2 1 2 66.5_0402_1% DDRA_ODT1
2 DDRA_ODT1 14
10K_0402_5%
on @
1

RD3

RD4
1

1
2 66.5_0402_1%

2 66.5_0402_1%
DDRB_ODT0

DDRB_ODT1
DDRB_ODT0

DDRB_ODT1
15

15

A A
C
Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 MCP (MISC,THERMAL,JATG)


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLUA
Date: Thursday, December 26, 2013 Sheet 5 of 59
5 4 3 2 1

PDF created with pdfFactory Pro trial version www.pdffactory.com


5 4 3 2 1

UC1C HSW_ULT_DDR3L UC1D HSW_ULT_DDR3L

14 DDRA_DQ[0..15] AH63 AU37


DDRA_DQ0
AH62 SA_DQ0 SA_CLK#0 AV37 DDRA_CLK0# 14 14 DDRA_DQ[32..47] AY31 AM38
DDRA_DQ1 DDRA_DQ32
AK63 SA_DQ1 SA_CLK0 AW36 DDRA_CLK0 14 AW31 SB_DQ0 SB_CK#0 AN38 DDRB_CLK0# 15
DDRA_DQ2 DDRA_DQ33
D AK62 SA_DQ2 SA_CLK#1 AY36 DDRA_CLK1# 14 AY29 SB_DQ1 SB_CK0 AK38 DDRB_CLK0 15 D
DDRA_DQ3 DDRA_DQ34
AH61 SA_DQ3 SA_CLK1 DDRA_CLK1 14 AW29 SB_DQ2 SB_CK#1 AL38 DDRB_CLK1# 15
DDRA_DQ4 DDRA_DQ35
AH60 SA_DQ4 AU43 AV31 SB_DQ3 SB_CK1 DDRB_CLK1 15
DDRA_DQ5 DDRA_DQ36
AK61 SA_DQ5 SA_CKE0 AW43 DDRA_CKE0 14 AU31 SB_DQ4 AY49
DDRA_DQ6 DDRA_DQ37
AK60 SA_DQ6 SA_CKE1 AY42 DDRA_CKE1 14 AV29 SB_DQ5 SB_CKE0 AU50 DDRB_CKE0 15
DDRA_DQ7 DDRA_DQ38
AM63 SA_DQ7 SA_CKE2 AY43 AU29 SB_DQ6 SB_CKE1 AW49 DDRB_CKE1 15
DDRA_DQ8 DDRA_DQ39
DDRA_DQ9 AM62 SA_DQ8 SA_CKE3 DDRA_DQ40 AY27 SB_DQ7 SB_CKE2 AV50
DDRA_DQ10 AP63 SA_DQ9 AP33 DDRA_DQ41 AW27 SB_DQ8 SB_CKE3
AP62 SA_DQ10 SA_CS#0 AR32 DDRA_CS0# 14 AY25 SB_DQ9 AM32
DDRA_DQ11 DDRA_DQ42
AM61 SA_DQ11 SA_CS#1 DDRA_CS1# 14 AW25 SB_DQ10 SB_CS#0 AK32 DDRB_CS0# 15
DDRA_DQ12 DDRA_DQ43
AM60 SA_DQ12 AP32 1 AV27 SB_DQ11 SB_CS#1 DDRB_CS1# 15
DDRA_DQ13 SA_ODT0 PAD @ DDRA_DQ44
AP61 SA_DQ13 SA_ODT0 TC19 AU27 SB_DQ12 AL32 SB_ODT0 1
DDRA_DQ14 DDRA_DQ45 PAD @
AP60 SA_DQ14 AY34 AV25 SB_DQ13 SB_ODT0 TC20
DDRA_DQ15 DDRA_DQ46
15 DDRB_DQ[0..15] AP58 SA_DQ15 SA_RAS AW34 DDRA_RAS# 14 AU25 SB_DQ14 AM35
DDRB_DQ0 DDRA_DQ47
AR58 SA_DQ16 SA_WE AU34 DDRA_W E# 14 15 DDRB_DQ[32..47] AM29 SB_DQ15 SB_RAS AK35 DDRB_RAS# 15
DDRB_DQ1 DDRB_DQ32
AM57 SA_DQ17 SA_CAS DDRA_CAS# 14 AK29 SB_DQ16 SB_WE AM33 DDRB_W E# 15
DDRB_DQ2 DDRB_DQ33
AK57 SA_DQ18 AU35 AL28 SB_DQ17 SB_CAS DDRB_CAS# 15
DDRB_DQ3 DDRB_DQ34
AL58 SA_DQ19 SA_BA0 AV35 DDRA_BS0# 14 AK28 SB_DQ18 AL35
DDRB_DQ4 DDRB_DQ35
AK58 SA_DQ20 SA_BA1 AY41 DDRA_BS1# 14 AR29 SB_DQ19 SB_BA0 AM36 DDRB_BS0# 15
DDRB_DQ5 DDRB_DQ36
AR57 SA_DQ21 SA_BA2 DDRA_BS2# 14 AN29 SB_DQ20 SB_BA1 AU49 DDRB_BS1# 15
DDRB_DQ6 DDRB_DQ37
AN57 SA_DQ22 AU36 DDRA_MA[0..15] 14 AR28 SB_DQ21 4 OF 19 SB_BA2 DDRB_BS2# 15
DDRB_DQ7 DDRA_MA0 DDRB_DQ38
AP55 SA_DQ23 SA_MA0 AY37 AP28 SB_DQ22 AP40 DDRB_MA[0..15] 15
DDRB_DQ8 DDRA_MA1 DDRB_DQ39 DDRB_MA0
DDRB_DQ9 AR55 SA_DQ24 SA_MA1 AR38 DDRA_MA2 DDRB_DQ40 AN26 SB_DQ23 SB_MA0 AR40 DDRB_MA1
DDRB_DQ10 AM54 SA_DQ25 SA_MA2 AP36 DDRA_MA3 DDRB_DQ41 AR26 SB_DQ24 SB_MA1 AP42 DDRB_MA2
AK54 SA_DQ26 SA_MA3 AU39 AR25 SB_DQ25 SB_MA2 AR42

l
DDRB_DQ11 DDRA_MA4 DDRB_DQ42 DDRB_MA3
DDRB_DQ12 AL55 SA_DQ27 SA_MA4 AR36 DDRA_MA5 DDRB_DQ43 AP25 SB_DQ26 SB_MA3 AR45 DDRB_MA4
DDRB_DQ13 AK55 SA_DQ28 SA_MA5 AV40 DDRA_MA6 DDRB_DQ44 AK26 SB_DQ27 SB_MA4 AP45 DDRB_MA5
SA_DQ29 SA_MA6 SB_DQ28 SB_MA5

tia
DDRB_DQ14 AR54 AW39 DDRA_MA7 DDRB_DQ45 AM26 AW46 DDRB_MA6
DDRB_DQ15 AN54 SA_DQ30 DDR CHANNEL A SA_MA7 AY39 DDRA_MA8 DDRB_DQ46 AK25 SB_DQ29 SB_MA6 AY46 DDRB_MA7
14 DDRA_DQ[16..31] AY58 SA_DQ31 SA_MA8 AU40 AL25 SB_DQ30 SB_MA7 AY47
DDRA_DQ16 DDRA_MA9 DDRB_DQ47 DDRB_MA8
AW58 SA_DQ32 SA_MA9 AP35 14 DDRA_DQ[48..63] AY23 SB_DQ31 DDR CHANNEL B SB_MA8 AU46
DDRA_DQ17 DDRA_MA10 DDRA_DQ48 DDRB_MA9
DDRA_DQ18 AY56 SA_DQ33 SA_MA10 AW41 DDRA_MA11 DDRA_DQ49 AW23 SB_DQ32 SB_MA9 AK36 DDRB_MA10
C DDRA_DQ19 AW56 SA_DQ34 SA_MA11 AU41 DDRA_MA12 DDRA_DQ50 AY21 SB_DQ33 SB_MA10 AV47 DDRB_MA11 C
DDRA_DQ20 AV58 SA_DQ35 SA_MA12 AR35 DDRA_MA13 DDRA_DQ51 AW21 SB_DQ34 SB_MA11 AU47 DDRB_MA12
DDRA_DQ21 AU58 SA_DQ36 SA_MA13 AV42 DDRA_MA14 DDRA_DQ52 AV23 SB_DQ35 SB_MA12 AK33 DDRB_MA13
DDRA_DQ22 AV56 SA_DQ37 SA_MA14 AU42 DDRA_MA15 DDRA_DQ53 AU23 SB_DQ36 SB_MA13 AR46 DDRB_MA14
DDRA_DQ23 AU56 SA_DQ38 SA_MA15 DDRA_DQ54 AV21 SB_DQ37 SB_MA14 AP46 DDRB_MA15
DDRA_DQ24 AY54 SA_DQ39 AJ61 DDRA_DQS#0 DDRA_DQ55 AU21 SB_DQ38 SB_MA15
DDRA_DQ25 AW54 SA_DQ40 SA_DQSN0 AN62 DDRA_DQS#1 DDRA_DQ56 AY19 SB_DQ39 AW30 DDRA_DQS#4
DDRA_DQ26 AY52 SA_DQ41 SA_DQSN1 AM58 DDRB_DQS#0 DDRA_DQ57 AW19 SB_DQ40 SB_DQSN0 AV26 DDRA_DQS#5
DDRA_DQ27 AW52 SA_DQ42 SA_DQSN2 AM55 DDRB_DQS#1 DDRA_DQ58 AY17 SB_DQ41 SB_DQSN1 AN28 DDRB_DQS#4

en
DDRA_DQ28 AV54 SA_DQ43 SA_DQSN3 AV57 DDRA_DQS#2 DDRA_DQ59 AW17 SB_DQ42 SB_DQSN2 AN25 DDRB_DQS#5
DDRA_DQ29 AU54 SA_DQ44 SA_DQSN4 AV53 DDRA_DQS#3 DDRA_DQ60 AV19 SB_DQ43 SB_DQSN3 AW22 DDRA_DQS#6
DDRA_DQ30 AV52 SA_DQ45 SA_DQSN5 AL43 DDRB_DQS#2 DDRA_DQ61 AU19 SB_DQ44 SB_DQSN4 AV18 DDRA_DQS#7
DDRA_DQ31 AU52 SA_DQ46 SA_DQSN6 AL48 DDRB_DQS#3 DDRA_DQ62 AV17 SB_DQ45 SB_DQSN5 AN21 DDRB_DQS#6
15 DDRB_DQ[16..31] AK40 SA_DQ47 SA_DQSN7 AU17 SB_DQ46 SB_DQSN6 AN18
DDRB_DQ16 DDRA_DQ63 DDRB_DQS#7
AK42 SA_DQ48 AJ62 15 DDRB_DQ[48..63] AR21 SB_DQ47 SB_DQSN7
DDRB_DQ17 DDRA_DQS0 DDRB_DQ48
DDRB_DQ18 AM43 SA_DQ49 SA_DQSP0 AN61 DDRA_DQS1 DDRB_DQ49 AR22 SB_DQ48 AV30 DDRA_DQS4
DDRB_DQ19 AM45 SA_DQ50 SA_DQSP1 AN58 DDRB_DQS0 DDRB_DQ50 AL21 SB_DQ49 SB_DQSP0 AW26 DDRA_DQS5
DDRB_DQ20 AK45 SA_DQ51 SA_DQSP2 AN55 DDRB_DQS1 DDRB_DQ51 AM22 SB_DQ50 SB_DQSP1 AM28 DDRB_DQS4
DDRB_DQ21 AK43 SA_DQ52 SA_DQSP3 AW57 DDRA_DQS2 DDRB_DQ52 AN22 SB_DQ51 SB_DQSP2 AM25 DDRB_DQS5
DDRB_DQ22 AM40 SA_DQ53 SA_DQSP4 AW53 DDRA_DQS3 DDRB_DQ53 AP21 SB_DQ52 SB_DQSP3 AV22 DDRA_DQS6
DDRB_DQ23 AM42 SA_DQ54 SA_DQSP5 AL42 DDRB_DQS2 DDRB_DQ54 AK21 SB_DQ53 SB_DQSP4 AW18 DDRA_DQS7
DDRB_DQ24 AM46 SA_DQ55 SA_DQSP6 AL49 DDRB_DQS3 DDRB_DQ55 AK22 SB_DQ54 SB_DQSP5 AM21 DDRB_DQS6
DDRB_DQ25 AK46 SA_DQ56 SA_DQSP7 DDRB_DQ56 AN20 SB_DQ55 SB_DQSP6 AM18 DDRB_DQS7
SA_DQ57 SB_DQ56 SB_DQSP7

fid
DDRB_DQ26 AM49 AP49 DDRB_DQ57 AR20
AK49 SA_DQ58 SM_VREF_CA AR51 DDR_SM_VREFCA 14 AK18 SB_DQ57
DDRB_DQ27 DDRB_DQ58
AM48 SA_DQ59 SM_VREF_DQ0 AP51 DDR_SA_VREFDQ 14 AL18 SB_DQ58
DDRB_DQ28 DDRB_DQ59
AK48 SA_DQ60 SM_VREF_DQ1 DDR_SB_VREFDQ 15 AK20 SB_DQ59
DDRB_DQ29 DDRB_DQ60
DDRB_DQ30 AM51 SA_DQ61 DDRB_DQ61 AM20 SB_DQ60
SA_DQ62 SMVREF SB_DQ61
DDRB_DQ31 AK51 WIDTH:20MIL DDRB_DQ62 AR18
SA_DQ63 DDRB_DQ63 AP18 SB_DQ62
SPACING: 20MIL SB_DQ63

B B

DDRA_DQS#[0..7] DDRB_DQS#[0..7]
DDRA_DQS#[0..7] 14 DDRB_DQS#[0..7] 15

HASWELL-ULT-DDR3L_BGA1168
3 OF 19
on DDRA_DQS[0..7]
DDRA_DQS[0..7] 14

HASWELL-ULT-DDR3L_BGA1168
DDRB_DQS[0..7]
DDRB_DQS[0..7] 15
C

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2013/08/08 Deciphered Date 2013/08/05 MCP (DDR3L)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLUA
Date: Thursday, December 26, 2013 Sheet 6 of 59
5 4 3 2 1

PDF created with pdfFactory Pro trial version www.pdffactory.com


5 4 3 2 1

RTC_X1

+3VS
RC32 2 1 10M_0402_5% RTC_X2 1 RPC2

1
CC3 JME1 ODD_DETECT# 1 8
VCCRTC 1U_0402_10V6K SHORT PADS SATA0GP 2 7
YC1 1 2 @ SATA2GP 3 6

2
2 SATA3GP 4 5
2 32.768KHZ_12.5PF_200458-PG14 2 RC33 1 2 20K_0402_1% SRTC_RST#
CC4 RC34 1 2 20K_0402_1% RTC_RST# 10K_0804_8P4R_5%
15P_0402_50V8J CC5
18P_0402_50V8J 1

1
1 1 CC6 JCMOS1
1U_0402_10V6K SHORT PADS
@

2
2
D D
CRYSTAL +3VALW _PCH
1, Space 15MIL
2, No trace under crystal
3, Place on oppsosit side of MCP for temp influence SML0_CLK RC35 2 1 2.2K_0402_5%

SML0_DATA RC36 2 1 2.2K_0402_5%


UC1E HSW_ULT_DDR3L

VCCRTC RPC22
RTC_X1 AW5 SMB_ALERT# 1 8
RTC_X2 AY5 RTCX1 SML0_ALERT# 2 7
RC39 2 1 1M_0402_5% SM_INTRUDER# AU6 RTCX2 J5 SATA_PRX_DTX_N0 SML1_ALERT# 3 6
INTRUDER SATA_RN0/PERN6_L3 SATA_PRX_DTX_N0 42
RC41 2 1 330K_0402_5% INTVRMEN AV7 H5 SATA_PRX_DTX_P0 4 5
INTVRMEN SATA_RP0/PERP6_L3 SATA_PRX_DTX_P0 42
SRTC_RST# AV6 RTC B15 SATA_PTX_DRX_N0 HDD
RTC_RST# AU7 SRTCRST SATA_TN0/PETN6_L3 A15 SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 42
INTVRMEN 10K_0804_8P4R_5%
RTCRST SATA_TP0/PETP6_L3 SATA_PTX_DRX_P0 42
* H Integrated VRM enable (Default)
J8 SATA_PRX_DTX_N1
L Integrated VRM disable SATA_RN1/PERN6_L2 H8
SATA_PRX_DTX_N1 42
SATA_PRX_DTX_P1
(INTVRMEN should always be pull high.) SATA_RP1/PERP6_L2 A17 SATA_PTX_DRX_N1
SATA_PRX_DTX_P1 42
SATA_TN1/PETN6_L2 SATA_PTX_DRX_N1 42
ODD
B17 SATA_PTX_DRX_P1
SATA_TP1/PETP6_L2 SATA_PTX_DRX_P1 42
RC42 1 2 33_0402_5% HDA_BCLK AW8 J6
43 HDA_BITCLK_AUDIO HDA_BCLK/I2S0_SCLK SATA_RN2/PERN6_L1
RC43 1 2 33_0402_5% HDA_SYNC AV11 H6
43 HDA_SYNC_AUDIO HDA_SYNC/I2S0_SFRM SATA_RP2/PERP6_L1
RC44 1 2 33_0402_5% HDA_RST# AU8 B14
43 HDA_RST_AUDIO# HDA_SDIN0 AY10 HDA_RST/I2S_MCLK AUDIO SATA SATA_TN2/PETN6_L1 C15

l
43 HDA_SDIN0 AU12 HDA_SDI0/I2S0_RXD SATA_TP2/PETP6_L1
+3VALW _PCH RC45 1 2 33_0402_5% HDA_SDOUT AU11 HDA_SDI1/I2S1_RXD F5
43 HDA_SDOUT_AUDIO HDA_SDO/I2S0_TXD SATA_RN3/PERN6_L0
RC46 1 2 0_0402_5% TC21 @ 1 AW10 E5

tia
44 ME_FLASH HDA_DOCK_EN/I2S1_TXD SATA_RP3/PERP6_L0
@ TC22 @ 1 AV10 C17
RC47 1 @ 2 1K_0402_5% HDA_SDOUT TC23 @ 1 AY8 HDA_DOCK_RST/I2S1_SFRM SATA_TN3/PETN6_L0 D17
I2S1_SCLK SATA_TP3/PETP6_L0

HDA_SDO This signal has a weak internal pull-down. V1 SATA0GP


SATA0GP/GPIO34 U1 ODD_DETECT#
* 0 = Enable security measures defined in the Flash Descriptor. SATA1GP/GPIO35 ODD_DETECT# 42
V6 SATA2GP IREF&RCOMP
1 = Disable Flash Descriptor Security(override). This strap SATA2GP/GPIO36 AC1 SATA3GP +1.05VS_PSATA3PLL Width: 12-15Mil
should only be asserted high during external pull-up in TC24 @ 1 PCH_JTAG_TRST# AU62 SATA3GP/GPIO37
manufacturing/debug environments ONLY. PCH_TRST Space:12Mil
C TC25 @ 1 PCH_JTAG_TCK AE62 A12 C
TC26 @ 1 PCH_JTAG_TDI AD61 PCH_TCK SATA_IREF L11
Length: 500Mil
TC28 @ 1 PCH_JTAG_TDO AE61 PCH_TDI RSVD3 K10
TC30 @ 1 PCH_JTAG_TMS AD62 PCH_TDO RSVD4 C12 SATA_RCOMP RC48 2 1 3.01K_0402_1%
For EMI PCH_TMS
JTAG
SATA_RCOMP
HDA_SDIN0 AL11 U3 SATALED# RC49 1 @ 2 10K_0402_5%
RSVD1 SATALED +3VS

en
TC32 @ 1 AC4
TC33 @ 1 PCH_JTAGX AE63 RSVD2
TC34 @ 1 AV2 JTAGX
1 RSVD0
@
CC7
10P_0402_50V8J
2
5 OF 19
HASWELL-ULT-DDR3L_BGA1168

UC1G HSW_ULT_DDR3L

fid
AU14 AN2 SMB_ALERT#
44 LPC_AD0 AW12 LAD0 SMBALERT/GPIO11 AP2 PCH_SMB_CLK
44 LPC_AD1 AY12 LAD1 SMBCLK AH1
LPC PCH_SMB_DATA
44 LPC_AD2 AW11 LAD2 SMBUS SMBDATA AL2 SML0_ALERT#
44 LPC_AD3 AV12 LAD3 SML0ALERT/GPIO60 AN1 SML0_CLK
44 LPC_FRAME# LFRAME SML0CLK AK1 SML0_DATA
SML0DATA AU4 SML1_ALERT#
SML1ALERT/PCHHOT/GPIO73 AU3 PCH_SML1_CLK
SPI_CLK_1 RC1731 @ 2 33_0402_5% SML1CLK/GPIO75 AH3 PCH_SML1_DAT
SML1DATA/GPIO74 DIMM1, DIMM2, NGFF
SPI_CLK RC50 1 2 15_0402_5% SPI_CLK_R AA3
44 SPI_CLK SPI_CLK
SPI_CS0# RC51 1 2 0_0402_5% SPI_CS0#_R Y7 AF2
44 SPI_CS0# SPI_CS0 CL_CLK
SPI_CS1# RC1741 @ 2 0_0402_5% SPI_CS1#_R Y4 AD2 +3VALW _PCH +3VS +3VS
SPI_SI_1 RC1751 @ 2 33_0402_5% AC2 SPI_CS1 SPI C-LINK
CL_DATA AF4
SPI_SI RC52 1 2 15_0402_5% SPI_SI_R AA2 SPI_CS2 CL_RST
44 SPI_SI SPI_MOSI
RC53 1 2 AA4
44 SPI_SO
SPI_SO
SPI_SO_1 RC1771 @ 2
on
15_0402_5%
33_0402_5%
SPI_SO_R
SPI_W P#_R Y6 SPI_MISO
SPI_IO2

1
SPI_HOLD#_R AF1
B SPI_IO3 RC56 RC57 RC58 RC59
B

2
2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5%

G
7 OF 19

2
HASWELL-ULT-DDR3L_BGA1168 PCH_SMB_CLK QC2A 6 1

S
+3V_SPI SMB_CLK_S3 14,15,40

D
2N7002KDW H_SOT363-6

5
G
1

RC60 RC61 PCH_SMB_DATA QC2B 3 4


C

S
SMB_DATA_S3 14,15,40
1K_0402_5% 1K_0402_5%

D
+3V_SPI 2N7002KDW H_SOT363-6
2

UC3
SPI_W P#_R RC54 1 @ 2 33_0402_5% SPI_W P# SPI_CS0# 1 8
CS# VCC
SPI_SO 2 7 SPI_HOLD# 1
SPI_HOLD#_R RC55 1 @ 2 33_0402_5% SPI_HOLD# DO HOLD# CC8 GPU, EC, Thermal Sensor
SPI_W P# 3 6 SPI_CLK .1U_0402_10V6-K
WP# CLK
4 5 SPI_SI 2 +3VALW _PCH +3VS
GND DI

+3V_SPI W 25Q64FVSSIG_SO8

1
RC62 RC63

2
2.2K_0402_5% 2.2K_0402_5%

G
1

+3V_SPI
RC179 RC180 UC6 @

2
1K_0402_5% 1K_0402_5%
@ @ SPI_CS1# 1 8 PCH_SML1_CLK QC3A 6 1

S
CS VCC EC_SMB_CK2 19,39,44

D
2

SPI_SO_1 2 7 SPI_HOLD#_1 1 2N7002KDW H_SOT363-6


DO(IO1) HOLD/RST(IO3)

5
A SPI_W P#_R RC176 1 @ 2 33_0402_5% SPI_W P#_1 CC97 A

G
SPI_W P#_1 3 6 SPI_CLK_1 .1U_0402_10V6-K
+3VALW _PCH +3V_SPI WP(IO2) CLK @
SPI_HOLD#_R RC178 1 @ 2 33_0402_5% SPI_HOLD#_1 4 5 SPI_SI_1 2
RC1711 2 GND DI(IO0) PCH_SML1_DAT QC3B 3 4

S
EC_SMB_DA2 19,39,44

D
0_0402_5% W 25Q32FVSSIG_SO8
+3VS 2N7002KDW H_SOT363-6

RC1721 @ 2
0_0402_5%
Security Classification LC Future Center Secret Data Title
+3V_SPI
1. If support DS3, connect to +3VS and don't support EC mirror code; Issued Date 2013/08/08 Deciphered Date 2013/08/05 MCP (RTC&AUDIO&SATA&SMBUS)
* 2. If don't support DS3, connect to +3VALW_PCH and support EC mirror code.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLUA
Date: Thursday, December 26, 2013 Sheet 7 of 59
5 4 3 2 1

PDF created with pdfFactory Pro trial version www.pdffactory.com


5 4 3 2 1

+3VS RC71 2 1 1M_0402_5%

RPC3 YC2
1 8 PCIE_CLKREQ1#
2 7 PCIE_CLKREQ0# 2 3 XTAL24_OUT
3 6 PCIE_CLKREQ5# GND1 OSC2
4 5 XTAL24_IN 1 4
OSC1 GND2
10K_0804_8P4R_5%

1
24MHZ_6PF_7V24000032

1
RPC4 CC11
D D
1 8 LAN_CLKREQ# CC12 4.7P_0402_50V8-J

2
2 7 WLAN_CLKREQ# 4.7P_0402_50V8-J

2
3 6 SYS_RESET#
UC1F HSW_ULT_DDR3L
4 5 PM_CLKRUN#

10K_0804_8P4R_5%

RC120 1 2 10K_0402_5% GPU_CLKREQ#


C43 A25 XTAL24_IN
C42 CLKOUT_PCIE_N0 XTAL24_IN B25 XTAL24_OUT
PCIE_CLKREQ0# U2 CLKOUT_PCIE_P0 XTAL24_OUT
PCIECLKRQ0/GPIO18 K21 +1.05VS_PLPTCLKPLL
RSVD5
DIFFCLK_BIASREF
B41 M21 Width: 12-15Mil
A41 CLKOUT_PCIE_N1 RSVD6 C26 DIFFCLK_BIASREF 2 1
CLKOUT_PCIE_P1 DIFFCLK_BIASREF Space:12Mil
PCIE_CLKREQ1# Y5 RC72 3.01K_0402_1%
PCIECLKRQ1/GPIO19 C35 MCP_TESTLOW1
Length: 500Mil
CLK_PCIE_LAN# C41 CLOCK TESTLOW_C35 C34 MCP_TESTLOW2
37 CLK_PCIE_LAN# CLKOUT_PCIE_N2 TESTLOW_C34
PCIE CLK2 LAN CLK_PCIE_LAN B42 AK8 MCP_TESTLOW3
37 CLK_PCIE_LAN CLKOUT_PCIE_P2 SIGNALS TESTLOW_AK8
LAN_CLKREQ# AD1 AL8 MCP_TESTLOW4
37 LAN_CLKREQ# PCIECLKRQ2/GPIO20 TESTLOW_AL8
CLK_PCIE_WLAN# B38 AN15 CLK_PCI_EC_R RC73 2 1 22_0402_5% RPC5

l
40 CLK_PCIE_WLAN# C37 CLKOUT_PCIE_N3 CLKOUT_LPC_0 AP15 CLK_PCI_EC 44 8 1
PCIE CLK3 WLAN CLK_PCIE_WLAN MCP_TESTLOW1
40 CLK_PCIE_WLAN CLKOUT_PCIE_P3 CLKOUT_LPC_1
WLAN_CLKREQ# N1 MCP_TESTLOW2 7 2
40 WLAN_CLKREQ# PCIECLKRQ3/GPIO21

tia
B35 MCP_TESTLOW3 6 3
CLK_PCIE_GPU# A39 CLKOUT_ITPXDP A35 MCP_TESTLOW4 5 4
19 CLK_PCIE_GPU# CLKOUT_PCIE_N4 CLKOUT_ITPXDP_P
PCIE CLK4 GPU CLK_PCIE_GPU B39
19 CLK_PCIE_GPU U5 CLKOUT_PCIE_P4
GPU_CLKREQ# 10K_0804_8P4R_5%
19 GPU_CLKREQ# PCIECLKRQ4/GPIO22
B37
C A37 CLKOUT_PCIE_N5 C
PCIE_CLKREQ5# T2 CLKOUT_PCIE_P5
+3VALW PCIECLKRQ5/GPIO23

6 OF 19
RC74 1 2 10K_0402_5% AC_PRESENT_R HASWELL-ULT-DDR3L_BGA1168 VCCRTC

en
RC75 1 @ 2 10K_0402_5% PCH_GPIO72

1
RC76 1 2 10K_0402_5% WAKE# RC77
330K_0402_5%

2
+3VALW_PCH
DSWODVREN

1
RC78 1 2 10K_0402_5% SUSWARN#_R
RC80

fid
RC90 1 2 10K_0402_5% PCH_GPIO72 330K_0402_5%
UC1H HSW_ULT_DDR3L @

2
Reserve for DS3 SYSTEM POWER MANAGEMENT RC182 1 2 0_0402_5% EC_RSMRST#

RC79 1 @ 2 0_0402_5% SUSACK#_R AK2 AW7 DSWODVREN Reserve for DS3


44 SUSACK# SUSACK DSWVRMEN
SYS_RESET# AC3 AV5 PCH_DPWROK_R RC81 1 @ 2 0_0402_5% DSWODVREN - On Die DSW VR Enable
SYS_RESET DPWROK DPWROK_EC 44
RC139 1 @ 2 0_0402_5% SYS_PWROK_R AG2 AJ5 WAKE# RC82 1 @ 2 0_0402_5%
44
10,44
SYS_PWROK
PCH_PWROK
RC126 1 @ 2 0_0402_5% PCH_PWROK_R AY7 SYS_PWROK
PCH_PWROK
WAKE PCIE_WAKE# 9,37,40,44 * H Enable
L Disable
RC83 1 @ 2 0_0402_5% APWROK AB5
RC84 1 @ 2 0_0402_5% PLT_RST#_R AG7 APWROK V5 PM_CLKRUN#
B 19,37,40,44 PLT_RST# PLTRST CLKRUN/GPIO32 B
AG4 SUS_STAT# 1 @ TC37
SUS_STAT/GPIO61

44
44 EC_RSMRST#
SUSWARN#
RC85
RC86
1
1
@ 2 0_0402_5%
2 0_0402_5%
on
PCH_RSMRST#_R
SUSWARN#_R
AW6
AV4 RSMRST
SUSWARN/SUSPWRDNACK/GPIO30
SUSCLK/GPIO62
SLP_S5/GPIO63
AE6
AP5
SUSCLK
PM_SLP_S5#
SUSCLK
PM_SLP_S5#
40
44

RC87 1 @ 2 0_0402_5% PBTN_OUT#_R AL7 AJ6 PM_SLP_S4#_R RC140 1 @ 2 0_0402_5%


44 PBTN_OUT# PWRBTN SLP_S4 PM_SLP_S4# 44
AC_PRESENT_R AJ8 AT4 PM_SLP_S3#_R RC141 1 @ 2 0_0402_5%
AN4 ACPRESENT/GPIO31 SLP_S3 AL5 PM_SLP_S3# 44
PCH_GPIO72
1 AF3 BATLOW/GPIO72 SLP_A AP4 PM_SLP_SUS#_R RC89 1 @ 2 0_0402_5%
TC38 SLP_S0 SLP_SUS PM_SLP_SUS# 44
@ PAD 1 AM5 AJ7 1
TC39 SLP_WLAN/GPIO29 SLP_LAN
CC104 @ @ PAD TC40 Reserve for DS3
1 2 PCH_PWROK @ PAD
1000P_0402_50V7K
C
CC103 @ 8 OF 19
1 2 PCH_DPWROK_R HASWELL-ULT-DDR3L_BGA1168
1000P_0402_50V7K

@
CC101 1 2 1000P_0402_50V7K

RC91 1 2 10K_0402_5% SYS_PWROK


RC88 1 @ 2 0_0402_5% AC_PRESENT_R
44 AC_PRESENT
RPC21
1 8
2 7 PCH_PWROK
3 6 PCH_RSMRST#_R
1

4 5 D
2 QC8
44,53 ACIN# G
A 10K_0804_8P4R_5% 2N7002KW_SOT323-3 A

S
3

100K_0402_5% 2 1 RC92 PLT_RST#_R


@
100K_0402_1% 2 @ 1 RC94 PCH_DPWROK_R
Security Classification LC Future Center Secret Data Title
1K_0402_5% 1 @ 2 RC95 SUSCLK

10K_0402_5% 2 @ 1 RC105 GPU_CLKREQ#


Issued Date 2013/08/08 Deciphered Date 2013/08/05 MCP (Clock,PM)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLUA
Date: Thursday, December 26, 2013 Sheet 8 of 59
5 4 3 2 1

PDF created with pdfFactory Pro trial version www.pdffactory.com


5 4 3 2 1

H_THRMTRIP#_R

.01U_0402_16V7-K
44 EC_LID_OUT# RC96 1 2 PCH_GPIO14

CC102
+3VALW 0_0402_5% +3VS
1
RC97 1 @ 2 10K_0402_5% PCH_GPIO12 DC2 1 2 @
RC98 1 2 10K_0402_5% DS3_WAKE# +1.05V_VCCST
RC99 1 2 10K_0402_5% PCH_GPIO25 SDM10U45LP-7_DFN1006-2-2

2
@ 2

2
RC100 RC101 RC102 RC121
UC1J HSW_ULT_DDR3L RC104 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
1K_0402_5% @ 15@ @ @
+3VALW_PCH

1
BOARD_ID0

1
BOARD_ID1
RC103 1 2 10K_0402_5% ODD_EN PCH_GPIO76 P1 D60 H_THRMTRIP#_R RC124 1 2 0_0402_5% BOARD_ID2
BMBUSY/GPIO76 THRMTRIP H_THRMTRIP# 19
PCH_GPIO8 AU2 V4 KBRST# @ KBRST# 44 BOARD_ID3
D GPIO8 RCIN/GPIO82 4 BOARD_ID3 D
PCH_GPIO12 AM7 T4 SERIRQ
LAN_PHY_PWR_CTRL/GPIO12 SERIRQ SERIRQ 44

2
PCH_GPIO15 AD6 CPU/ AW15 OPI_COMP RC106 2 149.9_0402_1%
BOARD_ID0 Y1 GPIO15 MISC PCH_OPI_RCOMP AF20 1 @ RC107 RC108 RC109 RC123
+3VALW_PCH ODD_DA# T3 GPIO16 RSVD7 AB21 TC41 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
42 ODD_DA# GPIO17 RSVD8
OPI_RCOMP
ODD_EN AD5 Width 20Mil @ 14@
42 ODD_EN GPIO24
RPC6 RC110 1 @ 2 DS3_WAKE# AN5 Space 15Mil
8,37,40,44 PCIE_WAKE#

1
8 1 PCH_GPIO8 0_0402_5% PCH_GPIO28 AD7 GPIO27
7 2 PCH_GPIO26 AN3 GPIO28 Length 500Mil
6 3 PCH_GPIO28 GPIO26 R6 PCH_GPIO83
5 4 PCH_GPIO26 PCH_GPIO56 AG6 GSPI0_CS/GPIO83 L6 BOARD_ID1
PCH_GPIO57 AP1 GPIO56 GSPI0_CLK/GPIO84 N6 PCH_GPIO85
10K_0804_8P4R_5% PCH_GPIO58 AL4 GPIO57 GSPI0_MISO/GPIO85 L8 PCH_GPIO86
PCH_GPIO59 AT5 GPIO58 GSPI0_MOSI/GPIO86 R7 PCH_BT_OFF# BOARD_ID0 BOARD_ID1 BOARD_ID2 BOARD_ID3 Description
GPIO59 GSPI1_CS/GPIO87 PCH_BT_OFF# 40
RPC7 PCH_GPIO44 AK4 GPIO L5 PCH_WLAN_OFF#
GPIO44 GSPI1_CLK/GPIO88 PCH_WLAN_OFF# 40
8 1 PCH_GPIO57 PCH_GPIO47 AB6 N7 PCH_GPIO89
7 2 PCH_GPIO56 VGA_PWRGD U4 GPIO47 GSPI1_MISO/GPIO89 K2 PCH_GPIO90 0 Reserve Reserve N15S-GT single rank
22,44 VGA_PWRGD GPIO48 GSPI_MOSI/GPIO90
6 3 PCH_GPIO58 PCH_GPIO49 Y3 J1 PCH_GPIO91
5 4 PCH_GPIO59 PCH_GPIO50 P3 GPIO49 UART0_RXD/GPIO91 K3 PCH_GPIO92
PCH_GPIO71 Y2 GPIO50 UART0_TXD/GPIO92 J2 PCH_GPIO93 1 Reserve Reserve N15S-GT Dual rank
10K_0804_8P4R_5% PCH_GPIO13 AT3 HSIOPC/GPIO71 SERIAL IO UART0_RTS/GPIO93 G1 PCH_GPIO94
PCH_GPIO14 AH4 GPIO13 UART0_CTS/GPIO94 K4 PCH_GPIO0
RPC8 @ PCH_GPIO25 AM4 GPIO14 UART1_RXD/GPIO0 G2 PCH_GPIO1 0 Reserve Reserve 14’ panel
8 1 PCH_GPIO47 EC_SMI# RC111 1 2 PCH_GPIO45 AG5 GPIO25 UART1_TXD/GPIO1 J3 PCH_GPIO2
44 EC_SMI# GPIO45 UART1_RST/GPIO2
7 2 PCH_GPIO44 PCH_GPIO46 AG3 J4 PCH_GPIO3
6 3 PCH_GPIO13 0_0402_5% GPIO46 UART1_CTS/GPIO3 F2 PCH_GPIO4 1 Reserve Reserve 15’ panel
5 4 PCH_GPIO14 PCH_GPIO9 AM3 I2C0_SDA/GPIO4 F3 PCH_GPIO5
PCH_GPIO10 AM2 GPIO9 I2C0_SCL/GPIO5 G4 PCH_GPIO6
10K_0804_8P4R_5% PCH_GPIO33 P2 GPIO10 I2C1_SDA/GPIO6 F1 PCH_GPIO7 RC112 1 2 0_0402_5%
DEVSLP0/GPIO33 I2C1_SCL/GPIO7 EC_SCI# 44
PCH_GPIO70 C4 E3 PCH_GPIO64 @
RPC9 PCH_GPIO38 L2 SDIO_POWER_EN/GPIO70 SDIO_CLK/GPIO64 F4 PCH_GPIO65

l
8 1 PCH_GPIO45 BOARD_ID2 N5 DEVSLP1/GPIO38 SDIO_CMD/GPIO65 D3 PCH_GPIO66
7 2 PCH_GPIO46 PCH_BEEP V2 DEVSLP2/GPIO39 SDIO_D0/GPIO66 E4 PCH_GPIO67
43 PCH_BEEP SPKR/GPIO81 SDIO_D1/GPIO67
6 3 PCH_GPIO10 C3 CMOS_ON#

tia
SDIO_D2/GPIO68 CMOS_ON# 33
5 4 PCH_GPIO9 E2 PCH_GPIO69
SDIO_D3/GPIO69
10K_0804_8P4R_5% 10 OF 19
HASW ELL-ULT-DDR3L_BGA1168
C C

+3VS

RC125 1 2 10K_0402_5% ODD_DA#

RPC10 19 PCIE_CRX_GTX_N[0..3]
8 1 PCH_GPIO33
7 2 PCH_GPIO49 19 PCIE_CRX_GTX_P[0..3] +3VALW_PCH
6 3 PCH_GPIO50
5 4 PCH_GPIO76 PCH_GPIO15 RC114 1 @ 2 1K_0402_5%
19 PCIE_CTX_C_GRX_N[0..3]

en
10K_0804_8P4R_5% UC1K HSW_ULT_DDR3L
19 PCIE_CTX_C_GRX_P[0..3]
GPIO15, Internal PD
RPC11 1: INTEL ME TLS W/ Confidentiality
8 1 PCH_GPIO83 PCIE_CRX_GTX_N0 F10 AN8 USB20_N0 *0: INTEL ME TLS W/O Confidentiality
PERN5_L0 USB2N0 USB20_N0 45
7 2 PCH_GPIO38 PCIE_CRX_GTX_P0 E10 AM8 USB20_P0
6 3 PCH_GPIO70 PERP5_L0 USB2P0 USB20_P0 45 RIGHT USB (2.0)
5 4 PCH_GPIO85 PCIE_CTX_C_GRX_N0 .1U_0402_10V6-K OPT@ 1 2 CC16 PCIE_CTX_GRX_N0 C23 AR7 USB20_N1
PETN5_L0 USB2N1 USB20_N1 41
PCIE_CTX_C_GRX_P0 .1U_0402_10V6-K OPT@ 1 2 CC14 PCIE_CTX_GRX_P0 C22 AT7 USB20_P1
10K_0804_8P4R_5% PETP5_L0 USB2P1 USB20_P1 41 LEFT USB (3.0)
PCIE_CRX_GTX_N1 F8 AR8 USB20_N2 +3VS
PERN5_L1 USB2N2 USB20_N2 41
RPC12 PCIE_CRX_GTX_P1 E8 AP8 USB20_P2
8 1 PCH_GPIO89 PERP5_L1 USB2P2 USB20_P2 41 LEFT USB (2.0) PCH_GPIO66 RC113 1 @ 2 1K_0402_5%
7 2 PCH_GPIO90 PCIE_CTX_C_GRX_N1 .1U_0402_10V6-K OPT@ 1 2 CC15 PCIE_CTX_GRX_N1 B23 AR10 USB20_N3
PETN5_L1 USB2N3 USB20_N3 45
6 3 PCH_GPIO91 PCIE_CTX_C_GRX_P1 .1U_0402_10V6-K OPT@ 1 2 CC17 PCIE_CTX_GRX_P1 A23 AT10 USB20_P3 GPIO66, Internal 20K PD
5 4 PCH_GPIO92 PETP5_L1 USB2P3 USB20_P3 45 Card reader 1: Enable Top Swap Mode
GPU PCIE5 PCIE_CRX_GTX_N2 H10 AM15 USB20_N4 *0: Disable Top Swap Mode(default)
PERN5_L2 USB2N4 USB20_N4 33

fid
10K_0804_8P4R_5% PCIE_CRX_GTX_P2 G10 AL15 USB20_P4
PERP5_L2 USB2P4 USB20_P4 33 Touch panel
RPC13 PCIE_CTX_C_GRX_N2 .1U_0402_10V6-K OPT@ 1 2 CC18 PCIE_CTX_GRX_N2 B21 AM13 USB20_N5
PETN5_L2 USB2N5 USB20_N5 33
8 1 PCH_GPIO93 PCIE_CTX_C_GRX_P2 .1U_0402_10V6-K OPT@ 1 2 CC19 PCIE_CTX_GRX_P2 C21 AN13 USB20_P5
7 2 PCH_GPIO1 PETP5_L2 USB2P5 USB20_P5 33 Camera
6 3 PCH_GPIO94 PCIE_CRX_GTX_N3 E6 AP11 USB20_N6 +3VS
PERN5_L3 USB2N6 USB20_N6 40
5 4 PCH_GPIO0 PCIE_CRX_GTX_P3 F6 AN11 USB20_P6
PERP5_L3 USB2P6 USB20_P6 40 BT
10K_0804_8P4R_5% PCIE_CTX_C_GRX_N3 .1U_0402_10V6-K OPT@ 1 2 CC20 PCIE_CTX_GRX_N3 B22 AR13 PCH_GPIO86 RC115 2 @ 1 1K_0402_5%
B
PCIE_CTX_C_GRX_P3 .1U_0402_10V6-K OPT@ 1 2 CC21 PCIE_CTX_GRX_P3 A21 PETN5_L3 USB2N7 AP13 B
RPC14 PETP5_L3 USB2P7 RC116 2 @ 1 1K_0402_5%
8 1 PCH_GPIO3 37 PCIE_PRX_DTX_N3 PCIE_PRX_DTX_N3 G11
7 2 PCH_GPIO2 PCIE_PRX_DTX_P3 F11 PERN3 G20 USB30_RX_N1
37 PCIE_PRX_DTX_P3 PERP3 USB3RN1 USB30_RX_N1 41
6 3 PCH_GPIO4 LAN PCIE3 H20 USB30_RX_P1 GPIO86, Internal PD
USB3RP1 USB30_RX_P1 41
5 4 PCH_GPIO5 CC22 1 2 .1U_0402_10V6-K PCIE_PTX_DRX_N3 C29 1: LPC
37 PCIE_PTX_C_DRX_N3
CC23 1 2 .1U_0402_10V6-K PCIE_PTX_DRX_P3 B30 PETN3 PCIE USB C33 USB30_TX_N1 LEFT USB (3.0) *0: SPI
37 PCIE_PTX_C_DRX_P3 PETP3 USB3TN1 USB30_TX_N1 41
10K_0804_8P4R_5% B34 USB30_TX_P1

8
7
6
RPC15
1
2
3
PCH_GPIO64
PCH_GPIO6
PCH_GPIO65
WLAN PCIE4
40
40

40
40
PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4

PCIE_PTX_C_DRX_N4
PCIE_PTX_C_DRX_P4
CC24 1
CC25 1
2 .1U_0402_10V6-K
2 .1U_0402_10V6-K
on
PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4

PCIE_PTX_DRX_N4
PCIE_PTX_DRX_P4
F13
G13

B29
A29
PERN4
PERP4

PETN4
USB3TP1

USB3RN2
USB3RP2
E18
F18

B33
USB30_TX_P1 41

+3VS
5 4 PCH_GPIO7 PETP4 USB3TN2 A33
G17 USB3TP2
10K_0804_8P4R_5% F17 PERN1/USB3RN3 PCH_BEEP RC117 2 @ 1 1K_0402_5%
PERP1/USB3RP3
RPC16 C30
8 1 PCH_GPIO67 C31 PETN1/USB3TN3 AJ10 USBRBIAS RC118 2 1
PETP1/USB3TP3 USBRBIAS
GPIO81, No Reboot, Internal PD
7 2 PCH_GPIO69 AJ11 22.6_0402_1% USBRBIAS 1: Enabled No Reboot Mode
6 3 PCH_GPIO71 F15 USBRBIAS AN10
PERN2/USB3RN4 RSVD11
Width 20Mil *0: Disable No Reboot Mode
5 4 G15 AM10 Space 15Mil
PERP2/USB3RP4 RSVD12
10K_0804_8P4R_5% B31 Length 500Mil
A31 PETN2/USB3TN4
C
PETP2/USB3TP4 AL3 USB_OC0#
OC0/GPIO40 AT1 USB_OC1#
OC1/GPIO41 USB_OC1# 41
AH2 USB_OC2#
+1.05VS_PUSB3PLL OC2/GPIO42 USB_OC2# 45
E15 AV3 USB_OC3#
E13 RSVD9 OC3/GPIO43 +3VALW_PCH
+3VS RC119 2 1 3.01K_0402_1% PCIE_RCOMP A27 RSVD10
B27 PCIE_RCOMP
RPC18 PCIE_IREF
1 8 CMOS_ON# PCIE_RCOMP&PCIE_IREF RPC17
2 7 PCH_WLAN_OFF# Width 12~15Mil USB_OC0# 8 1
3 6 PCH_BT_OFF# Space >12Mil 11 OF 19 USB_OC1# 7 2
4 5 KBRST# HASW ELL-ULT-DDR3L_BGA1168 USB_OC3# 6 3
A
Length 500Mil USB_OC2# 5 4 A
10K_0804_8P4R_5%
10K_0804_8P4R_5%
RC122 1 2 10K_0402_5% SERIRQ

RC181 1 2 10K_0402_5% VGA_PWRGD

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 MCP (GPIO,USB,PCIE)


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLUA
Date: Monday, December 30, 2013 Sheet 9 of 59
5 4 3 2 1

PDF created with pdfFactory Pro trial version www.pdffactory.com


5 4 3 2 1

CPU_CORE +1.35V_CPU
UC1L HSW_ULT_DDR3L

+1.35V Need short +1.35V_CPU @ TC45 1 L59 C36


RSVD13 VCC8

2.2U_0603_10V6-K

2.2U_0603_10V6-K

2.2U_0603_10V6-K

2.2U_0603_10V6-K
@ TC46 1 J58 C40
JC1 @ RSVD14 VCC9 C44
VCC10 1 1 1 1

CC26

CC27

CC28

CC29
1 2 AH26 C48
1 2 AJ31 VDDQ1 VCC11 C52
AJ33 VDDQ2 VCC12 C56
JUMP_43X79 AJ37 VDDQ3 VCC13 E23 2 2 2 2
CD@
AN33 VDDQ4 VCC14 E25
AP43 VDDQ5 VCC15 E27
AR48 VDDQ6 VCC16 E29
D
AY35 VDDQ7 VCC17 E31 D

AY40 VDDQ8 VCC18 E33


CPU_CORE
VDDQ9 VCC19
For cost down, change to X5R.
AY44 E35
CPU_CORE AY50 VDDQ10 VCC20 E37
VDDQ11 VCC21

2
VCC_SENSE E39
F59 VCC22 E41
Length Match: <25Mil RC127
VCC1 VCC23

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
Space: More Than 25Mil 100_0402_1% @ TC47 1 N58 E43
RSVD15 VCC24

330U_2.5V_M
@ TC48 1 AC58 E45 1 1 1 1 1 1 1
GND Reference RSVD16 VCC25

CC34

CC30

CC35

CC31

CC32

CC33
E47

1
VCC26

CC41
+VCCIO_OUT RC128 1 @ 2 0_0402_5% E63 E49 +
59 CPU_VCC_SENSE AB23 VCC_SENSE VCC27 E51
A59 RSVD17 VCC28 E53 2 2 CD@ 2 2 2 2
E20 VCCIO_OUT VCC29 E55 2
+VCCIOA_OUT VCCIOA_OUT VCC30
1 @ TC50 1 AD23 E57 @
@ TC51 1 AA23 RSVD18 VCC31 F24
CC36 @ TC52 1 AE59 RSVD19 VCC32 F28
4.7U_0603_10V6-K RSVD20 VCC33 F32
@ 2 CPU_SVID_ALERT#_R L62 VCC34 F36
VIDALERT VCC35 1.35V_CPU(1.4A)
CPU_SVID_CLK_R N63 HSW ULT POWER F40
CPU_SVID_DAT_R L63 VIDSCLK VCC36 F44
VIDSOUT VCC37 HW 4PCS 2.2UF CAP Mounted
VCCST_PW RGD B59 F48 HW 6PCS 10UF CAP Mounted
CPU_VR_ON F60 VCCST_PWRGD VCC38 F52
59 CPU_VR_ON
CPU_VR_READY C59 VR_EN VCC39 F56 PWR 2PCS 470U Near VR Output
+1.05VS VR_READY VCC40 G23
D63 VCC41 G25

l
RC129 2 @ 1 150_0402_1% PW R_DEBUG H59 VSS344 VCC42 G27
P62 PWR_DEBUG VCC43 G29
@ TC53 1 P60 VSS345 VCC44 G31 +1.35V_CPU

tia
@ TC54 1 P61 RSVD_TP1 VCC45 G33
@ TC55 1 N59 RSVD_TP2 VCC46 G35
RSVD_TP3 VCC47

CC37

CC38
RC130 2 1 N61 G37
10K_0402_5% @ TC56 1 T59 RSVD_TP4 VCC48 G39
RSVD21 VCC49

33P_0402_50V8J

33P_0402_50V8J
@ TC57 1 AD60 G41
@ TC58 1 AD59 RSVD22 VCC50 G43
RSVD23 VCC51 1 1
@ TC59 1 AA59 G45
@ TC60 1 AE60 RSVD24 VCC52 G47
@ TC61 1 AC59 RSVD25 VCC53 G49
C @ TC62 1 AG58 RSVD26 VCC54 G51 2 2 C
RSVD27 VCC55

@
@ TC63 1 U59 G53
+1.05VS +1.05V_VCCST @ TC64 1 V59 RSVD28 VCC56 G55
RSVD29 VCC57 G57
VCCST(0.1A) VCC58
LC1 1 2 AC22 H23
VCCST1 VCC59

en
UPB100505T-121Y-N AE22 J23
CPU_CORE AE23 VCCST2 VCC60 K23
1 1 VCCST3 VCC61 K57
CC39 CC40 AB57 VCC62 L22
VCC2 VCC63 For RF
22U_0805_6.3V6M 1U_0402_10V6K AD57 M23
2 2 VCC3 VCC64
CC2
33P_0402_50V8J AG57 M57
C24 VCC4 VCC65 P57
1 VCC5 VCC66
C28 U57
C32 VCC6 VCC67 W57
VCC7 VCC68
2 12 OF 19
@

HASWELL-ULT-DDR3L_BGA1168
SVID
1, Stripline Line, No More Than 6000Mil
2, Alert# Route Between CLK and Data
3, CLK Length<Data Length<CLK Length + 2000Mil
For RF

fid
4, Space at least 18Mil +1.05VS
2

CC42
RC131 RC132 .1U_0402_10V6-K
75_0402_1% 130_0402_1% @
2
1

RC133 2 1 43_0402_5% CPU_SVID_ALERT#_R


59 CPU_SVID_ALERT#
@
1 2 0_0402_5%

B
59

59
CPU_SVID_CLK

CPU_SVID_DAT
RC134

RC135 1
@
2 0_0402_5%
CPU_SVID_CLK_R

CPU_SVID_DAT_R
on B

CPU_VR_ON

+1.05V_VCCST

2
2
RC146
+1.05V_VCCST RC145 10K_0402_5%
+3VALW 10K_0402_5%
@

1
1
2

0_0402_5%
C

2
+3VALW RC137 2 1 CPU_VR_READY
1K_0402_5% RC144 RC147 @
10K_0402_5%
2

3
RC136 VCCST_PW RGD D 1

1
10K_0402_5% 5 CC141
G 2N7002KDW H_SOT363-6 100P_0402_50V8J
3

D QC7B @
1

6
5 QC6B RC148 D S 2
2

4
G 2 1 2
44,59 VR_CPU_PW ROK 2N7002KDW H_SOT363-6
2N7002KDW H_SOT363-6 CC140 G
6

RC138 D S 1000P_0402_50V7K 0_0402_5% QC7A


1
4

2 1 2 QC6A 1 CC49 S
@

1
8,44 PCH_PW ROK G @ 0.01U_0402_16V7K
0_0402_5% 1 2N7002KDW H_SOT363-6 @
CC46 S 2
1

@ 0.01U_0402_16V7K
@
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 MCP (Power)


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLUA
Date: Monday, December 30, 2013 Sheet 10 of 59
5 4 3 2 1

PDF created with pdfFactory Pro trial version www.pdffactory.com


5 4 3 2 1

+3VALW _PCH

HSW_ULT_DDR3L 2
+1.05VS_VCCHSIO UC1M CC50
VCCHSIO 1.838A 1U_0402_10V6K
K9
L10 VCCHSIO[1] 1
VCCHSIO[2]

1U_0402_10V6K

1U_0402_10V6K
+1.05VS VCC1_05[1:9] 1.741A M9 VCCRTC
N8 VCCHSIO[3] HSIO RTC AH11
1 1 VCC1_05[1] VCCSUS3_3[5] VCCRTC 1mA

CC53

CC51

1U_0402_10V6K
P9 AG10
VCC1_05[2] VCCRTC

CC55

CC56

CC57
1 +1.05VS_PUSB3PLL
B18 AE7 +DCPRTC CC52 2 1
VCCUSB3PLL DCPRTC

CC54

0.1U_0402_10V7K

0.1U_0402_10V7K
B11
D 2 2 +1.05VS_PSATA3PLL VCCSATA3PLL D

1U_0402_10V6K
VCCSPI 0.1U_0402_10V7K
2
VCCSPI 18mA 2 2 2

0.1U_0402_10V7K
+1.05VS_POPIPLL Y20 SPI Y8
AA21 RSVD30 OPI
VCCSPI
VCCAPLL[1] 2

CC58 @
W21 +1.05VS
VCCAPLL[2] AG14 1 1 1
VCCASW[1] AG13
VCCASW[2] 1 +1.05VS
VCCASW[1:5] 658mA
@ 1U_0402_10V6K 1 2 CC59 +1.05VS_DCPSUS3 J13 USB3
VCCHDA DCPSUS3 J11
VCC1_05[3]

CC63

CC64

CC65
VCCHDA 11mA H11
AH14 HDA VCC1_05[4] H15
VCCHDA VCC1_05[5]

1U_0402_10V6K

1U_0402_10V6K

10U_0603_6.3V6M
AE8
VCC1_05[6]
1U_0402_10V6K

AF22 1U_0402_10V6K 2 2 2
@ 1U_0402_10V6K 1 2 CC60 +1.05VS_DCPSUS2 AH13 VRM VCC1_05[7] AG19 +PCH_DCPSUSBYP CC61 2 1 +1.05VS
1 DCPSUS2 DCPSUSBYP[1]
CC62

CORE AG20
+3VALW _PCH DCPSUSBYP[2] AE9
VCCASW[3] 1 1 1

CC68

CC69
VCCSUS3_3[1:5] 65mA AF9
2 AC9 VCCASW[4] AG8
VCCSUS3_3[1] VCCASW[5]
22U_0805_6.3V6M

1U_0402_10V6K

22U_0805_6.3V6M
VCCDSW 114mA AA9 GPIO/LPC AD10 +1.05VS_DCPSUS1 CC66 2 1 @ CD@
AH10 VCCSUS3_3[2] DCPSUS1[1] AD8
1 VCCDSW 3_3 VCCDSW3_3 DCPSUS1[2] 2 1
CC67

1U_0402_10V6K

+3VS
V8 +1.5VS 1U_0402_10V6K
W9 VCC3_3[1]
1 VCC3_3[1:4] 41mA VCC3_3[2] VCCTS1_5 3mA
CC70 @

22U_0805_6.3V6M J15 +3VS


2 THERMAL SENSOR VCCTS1_5 K14 1 2

l
1 VCC3_3[3]
CC71

@
K16
2 VCC3_3[4]

0.1U_0402_10V7K
+1.05VS_PLPTVCC1P05
+3VS

tia
2 2

CC72
+1.05VS_PLPTCLKPLL J18 VCCSDIO 17mA
+1.05VS K19 VCCCLK[1] SERIAL IO U8
VCCCLK[2] VCCSDIO[1]

1U_0402_10V6K
A20 T9
J17 VCCACLKPLL VCCSDIO[2] 1
VCCCLK[3] 2

CC74
R21
VCCCLK[4]
1U_0402_10V6K

1U_0402_10V6K

T21 LPT LP POWER 1U_0402_10V6K


TC66 @ 1 K18 VCCCLK[5] SUS OSCILLATOR AB8 +1.05VS_DCPSUS4 CC73 2 1 @
1 1 RSVD31 DCPSUS4 1
CC75

CC76

TC67 @ 1 M20
V21 RSVD32 +1.05VS
C AE20 RSVD33 AC20 C
2 2 AE21 VCCSUS3_3[3] RSVD34 AG16
+3VALW _PCH VCCSUS3_3[4] VCC1_05[8]
USB2 AG17
VCC1_05[9]

1U_0402_10V6K
CD@ 2

CC77

en
+3VL 13 OF 19
HASWELL-ULT-DDR3L_BGA1168 1
RC149 2 @ 1 VCCDSW 3_3
+3VALW 0_0402_5%

RC150 2 1
0_0402_5%

+3VALW _PCH +1.05VS Need short +1.05VS_VCCHSIO +1.05VS_PUSB3PLL +1.05VS +1.05VS_PLPTVCC1P05

JC2 @ +1.05VS_PUSB3PLL 41mA +1.05VS_PLPTVCC1P05 185mA

fid
RC151 2 @ 1 VCCHDA 1 2 LC2 1 2 LC3 1 2
+3VS 0_0402_5% 1 2 2.2UH_CIG10W 2R2MNC_20% 2.2UH_CIG10W 2R2MNC_20%
JUMP_43X79 1 1 1 1 1 1 1 1
0_0402_5% 2 @ 1 RC152 CC78 CC79 CC80
22U_0805_6.3V6M 22U_0805_6.3V6M 1U_0402_10V6K CC81 CC100 CC82 CC83 CC84
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 1U_0402_10V6K
2 2 2 2 2 2 2 2

+3VS

RC153 2 @ 1 VCCSPI

B
+3V_SPI

0_0402_5% 2
0_0402_5%

@ 1 RC154 LC4 1 2
2.2UH_CIG10W 2R2MNC_20%
on
+1.05VS_PSATA3PLL 42mA
+1.05VS_PSATA3PLL

LC5 1
+1.05VS_PLPTCLKPLL
2
2.2UH_CIG10W 2R2MNC_20%
31mA +1.05VS_PLPTCLKPLL

1 1 1 1 1 1 1 1
CC85 CC86 CC87
22U_0805_6.3V6M 22U_0805_6.3V6M 1U_0402_10V6K CC88 CC95 CC98 CC99 CC89
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 1U_0402_10V6K
2 2 2 2 2 2 2 2

VCCDSW 3_3 CC90 1 2 0.47U_0402_25V6K +PCH_DCPSUSBYP


C
For Intel recommend, place one 0.47uF +1.05VS_POPIPLL
@ +1.05VS_POPIPLL 57mA
capacitor to address temporary inrush LC6 1 2
current.(DOC.489999) 0_0603_5%

1 1 1
1
CC91 CC92 CC93 CC94
33P_0402_50V8J 47U_0805_4V6-M 47U_0805_4V6-M 1U_0402_10V6K
@ 2@ 2@ 2
2

For RF

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 MCP (Power2)


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLUA
Date: Thursday, December 26, 2013 Sheet 11 of 59
5 4 3 2 1

PDF created with pdfFactory Pro trial version www.pdffactory.com


5 4 3 2 1

UC1N HSW_ULT_DDR3L UC1O HSW_ULT_DDR3L

A11 AJ35 AP22 AV59


A14 VSS1 VSS65 AJ39 AP23 VSS129 VSS193 AV8
D A18 VSS2 VSS66 AJ41 AP26 VSS130 VSS194 AW16 D
A24 VSS3 VSS67 AJ43 AP29 VSS131 VSS195 AW24
A28 VSS4 VSS68 AJ45 AP3 VSS132 VSS196 AW33
A32 VSS5 VSS69 AJ47 AP31 VSS133 VSS197 AW35
A36 VSS6 VSS70 AJ50 AP38 VSS134 VSS198 AW37
A40 VSS7 VSS71 AJ52 AP39 VSS135 VSS199 AW4 UC1P HSW_ULT_DDR3L
A44 VSS8 VSS72 AJ54 AP48 VSS136 VSS200 AW40 H17
A48 VSS9 VSS73 AJ56 AP52 VSS137 VSS201 AW42 D33 VSS300 H57
A52 VSS10 VSS74 AJ58 AP54 VSS138 VSS202 AW44 D34 VSS257 VSS301 J10
A56 VSS11 VSS75 AJ60 AP57 VSS139 VSS203 AW47 D35 VSS258 VSS302 J22
AA1 VSS12 VSS76 AJ63 AR11 VSS140 VSS204 AW50 D37 VSS259 VSS303 J59
AA58 VSS13 VSS77 AK23 AR15 VSS141 VSS205 AW51 D38 VSS260 VSS304 J63
AB10 VSS14 VSS78 AK3 AR17 VSS142 VSS206 AW59 D39 VSS261 VSS305 K1
AB20 VSS15 VSS79 AK52 AR23 VSS143 VSS207 AW60 D41 VSS262 VSS306 K12
AB22 VSS16 VSS80 AL10 AR31 VSS144 VSS208 AY11 D42 VSS263 VSS307 L13
AB7 VSS17 VSS81 AL13 AR33 VSS145 VSS209 AY16 D43 VSS264 VSS308 L15
AC61 VSS18 VSS82 AL17 AR39 VSS146 VSS210 AY18 D45 VSS265 VSS309 L17
AD21 VSS19 VSS83 AL20 AR43 VSS147 VSS211 AY22 D46 VSS266 VSS310 L18
AD3 VSS20 VSS84 AL22 AR49 VSS148 VSS212 AY24 D47 VSS267 VSS311 L20
AD63 VSS21 VSS85 AL23 AR5 VSS149 VSS213 AY26 D49 VSS268 VSS312 L58
AE10 VSS22 VSS86 AL26 AR52 VSS150 VSS214 AY30 D5 VSS269 VSS313 L61
AE5 VSS23 VSS87 AL29 AT13 VSS151 VSS215 AY33 D50 VSS270 VSS314 L7
AE58 VSS24 VSS88 AL31 AT35 VSS152 VSS216 AY4 D51 VSS271 VSS315 M22
AF11 VSS25 VSS89 AL33 AT37 VSS153 VSS217 AY51 D53 VSS272 VSS316 N10

l
AF12 VSS26 VSS90 AL36 AT40 VSS154 VSS218 AY53 D54 VSS273 VSS317 N3
C
AF14 VSS27 VSS91 AL39 AT42 VSS155 VSS219 AY57 D55 VSS274 VSS318 P59
C
VSS28 VSS92 VSS156 VSS220 VSS275 VSS319

tia
AF15 AL40 AT43 AY59 D57 P63
AF17 VSS29 VSS93 AL45 AT46 VSS157 VSS221 AY6 D59 VSS276 VSS320 R10
AF18 VSS30 VSS94 AL46 AT49 VSS158 VSS222 B20 D62 VSS277 VSS321 R22
AG1 VSS31 VSS95 AL51 AT61 VSS159 VSS223 B24 D8 VSS278 VSS322 R8
AG11 VSS32 VSS96 AL52 AT62 VSS160 VSS224 B26 E11 VSS279 VSS323 T1
AG21 VSS33 VSS97 AL54 AT63 VSS161 VSS225 B28 E17 VSS280 VSS324 T58
AG23 VSS34 VSS98 AL57 AU1 VSS162 VSS226 B32 F20 VSS281 VSS325 U20
AG60 VSS35 VSS99 AL60 AU16 VSS163 VSS227 B36 F26 VSS282 VSS326 U22
AG61 VSS36 VSS100 AL61 AU18 VSS164 VSS228 B4 F30 VSS283 VSS327 U61
AG62 VSS37 VSS101 AM1 AU20 VSS165 VSS229 B40 F34 VSS284 VSS328 U9
AG63 VSS38 VSS102 AM17 AU22 VSS166 VSS230 B44 F38 VSS285 VSS329 V10
AH17 VSS39 VSS103 AM23 AU24 VSS167 VSS231 B48 F42 VSS286 VSS330 V3
VSS40 VSS104 VSS168 VSS232 VSS287 VSS331

en
AH19 AM31 AU26 B52 F46 V7
AH20 VSS41 VSS105 AM52 AU28 VSS169 VSS233 B56 F50 VSS288 VSS332 W20
AH22 VSS42 VSS106 AN17 AU30 VSS170 VSS234 B60 F54 VSS289 VSS333 W22
AH24 VSS43 VSS107 AN23 AU33 VSS171 VSS235 C11 F58 VSS290 VSS334 Y10
AH28 VSS44 VSS108 AN31 AU51 VSS172 VSS236 C14 F61 VSS291 VSS335 Y59
AH30 VSS45 VSS109 AN32 AU53 VSS173 VSS237 C18 G18 VSS292 VSS336 Y63
AH32 VSS46 VSS110 AN35 AU55 VSS174 VSS238 C20 G22 VSS293 VSS337
AH34 VSS47 VSS111 AN36 AU57 VSS175 VSS239 C25 G3 VSS294
AH36 VSS48 VSS112 AN39 AU59 VSS176 VSS240 C27 G5 VSS295 V58
AH38 VSS49 VSS113 AN40 AV14 VSS177 VSS241 C38 G6 VSS296 VSS338 AH46
AH40 VSS50 VSS114 AN42 AV16 VSS178 VSS242 C39 G8 VSS297 VSS339 V23
B AH42 VSS51 VSS115 AN43 AV20 VSS179 VSS243 C57 H13 VSS298 VSS340 E62 RC158 1 @ 2 0_0402_5% B
VSS52 VSS116 VSS180 VSS244 VSS299 VSS_SENSE CPU_VSS_SENSE 59
AH44 AN45 AV24 D12 AH16

fid
VSS53 VSS117 VSS181 VSS245 VSS341

2
AH49 AN46 AV28 D14 16 OF 19
AH51 VSS54 VSS118 AN48 AV33 VSS182 VSS246 D18 HASWELL-ULT-DDR3L_BGA1168 RC159
AH53 VSS55 VSS119 AN49 AV34 VSS183 VSS247 D2 100_0402_1%
VSS56 VSS120 VSS184 VSS248 VSS_SENSE
AH55 AN51 AV36 D21 Length Match: No More Than 25Mil
AH57 VSS57 VSS121 AN52 AV39 VSS185 VSS249 D23 Space: More Than 25Mil

1
AJ13 VSS58 VSS122 AN60 AV41 VSS186 VSS250 D25
AJ14 VSS59 VSS123 AN63 AV43 VSS187 VSS251 D26
GND Reference
AJ23 VSS60 VSS124 AN7 AV46 VSS188 VSS252 D27
AJ25 VSS61 VSS125 AP10 AV49 VSS189 VSS253 D29
AJ27 VSS62 VSS126 AP17 AV51 VSS190 VSS254 D30
AJ29 VSS63 VSS127 AP20 AV55 VSS191 VSS255 D31
VSS64 VSS128 VSS192 15 OF 19 VSS256

14 OF 19
HASWELL-ULT-DDR3L_BGA1168
on HASWELL-ULT-DDR3L_BGA1168

A A
C
Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 MCP (VSS)


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLUA
Date: Thursday, December 26, 2013 Sheet 12 of 59
5 4 3 2 1

PDF created with pdfFactory Pro trial version www.pdffactory.com


5 4 3 2 1

UC1Q HSW_ULT_DDR3L

DC_TEST_AY2_AW2 AY2 A3 DC_TEST_A3_B3


DC_TEST_AY3_AW3 AY3 DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_A3 A4 TP_DC_TEST_A4 1 @ TC71
TC70 @ 1 TP_DC_TEST_AY60 AY60 DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_A4
D
DC_TEST_AY61_AW61 AY61 DAISY_CHAIN_NCTF_AY60 A60 TP_DC_TEST_A60 1 @ TC72
D

DC_TEST_AY62_AW62 AY62 DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_A60 A61 DC_TEST_A61_B61


TC73 @ 1 TP_DC_TEST_B2 B2 DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_A61 A62 TP_DC_TEST_A62 1 @ TC74
DC_TEST_A3_B3 B3 DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_A62 AV1 TP_DC_TEST_AV1 1 @ TC75
DC_TEST_A61_B61 B61 DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_AV1 AW1 TP_DC_TEST_AW1 1 @ TC76
DC_TEST_B62_B63 B62 DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_AW1 AW2 DC_TEST_AY2_AW2
B63 DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_AW2 AW3 DC_TEST_AY3_AW3
DC_TEST_C1_C2 C1 DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_AW3 AW61 DC_TEST_AY61_AW61
C2 DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_AW61 AW62 DC_TEST_AY62_AW62
DAISY_CHAIN_NCTF_C2 DAISY_CHAIN_NCTF_AW62 AW63 TP_DC_TEST_AW63 1 @ TC77
17 OF 19 DAISY_CHAIN_NCTF_AW63
HASWELL-ULT-DDR3L_BGA1168

UC1R HSW_ULT_DDR3L

N23
RSVD42 R23
TC78 @ 1 RSVD43 T23

l
AT2 RSVD44
TC82 @ 1 RSVD35 U10 1 @ TC83
AU44 RSVD45
TC84 @ 1 RSVD36
AV44

tia
D15 RSVD37
RSVD38 AL1 1 @ TC86
RSVD46 AM11
TC88 @ 1 RSVD47 AP7
F22 RSVD48
RSVD39 AU10
H22 RSVD49
RSVD40 AU15 1 @ TC93
J21 RSVD50
C RSVD41 AW14 C
RSVD51 AY14
RSVD52

18 OF 19
HASWELL-ULT-DDR3L_BGA1168

en
UC1S HSW_ULT_DDR3L

TC96 @ 1 CFG0 AC60 AV63 1 @ TC97 CFG3 RC160 2 @ 1 1K_0402_1%


TC98 @ 1 CFG1 AC62 CFG0 RSVD_TP5 AU63 1 @ TC101
TC99 @ 1 CFG2 AC63 CFG1 RSVD_TP6

fid
TC100 @ 1 CFG3 AA63 CFG2
TC102 @ 1 CFG4 AA60 CFG3 C63 1 @ TC103
CFG4 RSVD_TP7 CFG3
TC104 @ 1 CFG5 Y62 C62 1 @ TC105 *1: Disable
TC106 @ 1 CFG6 Y61 CFG5 RSVD_TP8 B43 1 @ TC107
CFG6 RSVD58 0: Enable, Set DFX Enabled BIT
TC108 @ 1 CFG7 Y60
TC109 @ 1 CFG8 V62 CFG7 A51 1 @ TC110
In Debug Interface MSR
TC111 @ 1 CFG9 V61 CFG8 RSVD_TP9 B51 1 @ TC112
TC113 @ 1 CFG10 V60 CFG9 RSVD_TP10
TC114 @ 1 CFG11 U60 CFG10 L60 1 @ TC115
TC116 @ 1 CFG12 T63 CFG11 RSVD_TP11
TC117 @ 1 CFG13 T62 CFG12 RESERVED N60 1 @ TC118 CFG4 RC161 2 1 1K_0402_1%
B
TC119 @ 1 CFG14 T61 CFG13 RSVD59 B
CFG14
TC120

TC123
TC124
@

@
@
1

1
1
CFG15

CFG16
CFG18
on
T60

AA62
U63
CFG15

CFG16
CFG18
RSVD60
RSVD61
PROC_OPI_RCOMP
W23
Y22
AY15 PROC_OPI_COMP RC162 2 1
49.9_0402_1%
PROC_OPI_RCOMP
Width 20Mil CFG4
TC125 @ 1 CFG17 AA61 AV62 1 @ TC126 Space 15Mil *L: eDP enable
TC127 @ 1 CFG19 U62 CFG17 RSVD62 D58
CFG19 RSVD63 Length 500Mil H: eDP disable
RC163 2 1 49.9_0402_1% CFG_RCOMP V63 P22
CFG_RCOMP VSS342 N21
TC129 @ 1 A5 VSS343
CFG_RCOMP&TD_IREF RSVD53 P20
E1 RSVD64 R20
Width 20Mil RSVD54 RSVD65
Space 15Mil D1 CFG0 RC164 2 @ 1 1K_0402_1%
C
J20 RSVD55
Length 500Mil TC135 @ 1 H18 RSVD56 CFG1 RC165 2 @ 1 1K_0402_1%
2 1 TD_IREF B12 RSVD57
RC166 8.2K_0402_1% TD_IREF CFG8 RC167 2 @ 1 1K_0402_1%
19 OF 19
HASWELL-ULT-DDR3L_BGA1168 CFG9 RC168 2 @ 1 1K_0402_1%

CFG10 RC169 2 @ 1 1K_0402_1%

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 MCP (OTHER)


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLUA
Date: Thursday, December 26, 2013 Sheet 13 of 59
5 4 3 2 1

PDF created with pdfFactory Pro trial version www.pdffactory.com


5 4 3 2 1

DDR_SA_VREFDQ 6 DDR3 SO-DIMM A


DDRA_DQ[0..63] 6
+1.35V
+1.35V +1.35V
DDRA_DQS[0..7] 6

1
DDRA_DQS#[0..7] 6
RD5
1.82K_0402_1% 3A@1.5V DDRA_MA[0..15] 6
RD6 For RF
JDDR1
2

1 2 +VREF_DQ_DIMMA 1 2
D 2_0402_5% 3 VREF_DQ VSS_2 4 DDRA_DQ4 D
VSS_1 DQ4
1
0.022U_0402_16V7-K

1.82K_0402_1%

2.2U_0603_6.3V6K

.1U_0402_10V6-K

33P_0402_50V8J

33P_0402_50V8J

33P_0402_50V8J
DDRA_DQ0 5 6 DDRA_DQ5
DDRA_DQ1 7 DQ0 DQ5 8
1 1 DQ1 VSS_4 1 1 1
RD7

CD5

CD6

CD7
1 CD4 CD2 9 10 DDRA_DQS#0 @ @ @
VSS_3 DQS0#
CD3

11 12 DDRA_DQS0
CD@ 13 DM0 DQS0 14
2

2 2 DDRA_DQ2 15 VSS_5 VSS_6 16 DDRA_DQ6 2 2 2


2 DDRA_DQ3 17 DQ2 DQ6 18 DDRA_DQ7
19 DQ3 DQ7 20
DDRA_DQ8 21 VSS_7 VSS_8 22 DDRA_DQ12
DQ8 DQ12
1

DDRA_DQ9 23 24 DDRA_DQ13
RD8 25 DQ9 DQ13 26
24.9_0402_1% DDRA_DQS#1 27 VSS_9 VSS_10 28
DDRA_DQS1 29 DQS1# DM1 30 CPU_DRAMRST#
DQS1 RESET# CPU_DRAMRST# 5,15
31 32
2

DDRA_DQ10 33 VSS_11 VSS_12 34 DDRA_DQ14


DDRA_DQ11 35 DQ10 DQ14 36 DDRA_DQ15
37 DQ11 DQ15 38
DDRA_DQ16 39 VSS_13 VSS_14 40 DDRA_DQ20 Layout Note:
OSCON (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y0J)
DDRA_DQ17 41 DQ16 DQ20 42 DDRA_DQ21
43 DQ17 DQ21 44 Place near DIMM (10uF_0603_6.3V)*8
DDRA_DQS#2 45 VSS_15 VSS_16 46
(1U_0402_6.3V)*4

l
DDRA_DQS2 47 DQS2# DM2 48
49 DQS2 VSS_18 50 DDRA_DQ22
VSS_17 DQ22 (.1U_0402_10V6-K)*4

tia
DDRA_DQ18 51 52 DDRA_DQ23
DDRA_DQ19 53 DQ18 DQ23 54
55 DQ19 VSS_20 56 DDRA_DQ28
DDRA_DQ24 57 VSS_19 DQ28 58 DDRA_DQ29 +1.35V
DDRA_DQ25 59 DQ24 DQ29 60
61 DQ25 VSS_22 62 DDRA_DQS#3
VSS_21 DQS3#

CD8

CD9

CD10

CD11

CD12

CD13

CD14

CD15

CD16

CD17

CD18

CD19

CD56

CD57

CD58

CD59
63 64 DDRA_DQS3
65 DM3 DQS3 66
VSS_23 VSS_24

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
C DDRA_DQ26 67 68 DDRA_DQ30 C
DQ26 DQ30 1
DDRA_DQ27 69 70 DDRA_DQ31 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
71 DQ27 DQ31 72 + CD20
VSS_25 VSS_26 220U_6.3V_M
CD@ CD@ CD@ CD@ CD@ CD@ @

en
DDRA_CKE0 73 74 DDRA_CKE1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
6 DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 6
75 76
77 VDD_1 VDD_2 78 DDRA_MA15
DDRA_BS2# 79 NC_1 A15 80 DDRA_MA14
6 DDRA_BS2# BA2 A14
81 82
DDRA_MA12 83 VDD_3 VDD_4 84 DDRA_MA11
DDRA_MA9 85 A12/BC# A11 86 DDRA_MA7
87 A9 A7 88
DDRA_MA8 89 VDD_5 VDD_6 90 DDRA_MA6
DDRA_MA5 91 A8 A6 92 DDRA_MA4
93 A5 A4 94
DDRA_MA3 95 VDD_7 VDD_8 96 DDRA_MA2
DDRA_MA1 97 A3 A2 98 DDRA_MA0
A1 A0

fid
99 100
DDRA_CLK0 101 VDD_9 VDD_10 102 DDRA_CLK1
6 DDRA_CLK0 CK0 CK1 DDRA_CLK1 6
6 DDRA_CLK0# DDRA_CLK0# 103 104 DDRA_CLK1#
CK0# CK1# DDRA_CLK1# 6
105 106 +1.35V
VDD_11 VDD_12
DDRA_MA10
DDRA_BS0#
107
109 A10/AP BA1
108
110
DDRA_BS1#
DDRA_RAS#
DDRA_BS1# 6 Note:
6 DDRA_BS0# BA0 RAS# DDRA_RAS# 6 VREF trace width:20 mils at least

1
111 112
6 DDRA_WE# DDRA_WE# 113 VDD_13
WE#
VDD_14
S0#
114 DDRA_CS0#
DDRA_CS0# 6
RD9 Spacing:20mils to other signal/planes
6 DDRA_CAS# DDRA_CAS# 115
117 CAS# ODT0
116
118
DDRA_ODT0
DDRA_ODT0 5 Trace width:20 mils 1.82K_0402_1% Place near DIMM scoket
DDRA_MA13 119 VDD_15 VDD_16 120 DDRA_ODT1
Space:20mils
DDRA_ODT1 5

2
DDRA_CS1# 121 A13 ODT1 122
6 DDRA_CS1# S1# NC_2
123 124 +VREF_CA RD10 1 2 0_0402_5%
DDR_SM_VREFCA 6
B
125
127
VDD_17
TEST
VSS_27
VDD_18
VREF_CA
VSS_28
126
128
on +VREF_CA
+VREF_CA 15
@ 1
CD21 B

1
.1U_0402_10V6-K

DDRA_DQ32 129 130 DDRA_DQ36 0.022U_0402_16V7-K


DDRA_DQ33 131 DQ32 DQ36 132 DDRA_DQ37 RD11
DQ33 DQ37 1 1 2
CD22

133 134 CD23 1.82K_0402_1%


VSS_29 VSS_30

1
DDRA_DQS#4 135 136 2.2U_0603_6.3V6K
DDRA_DQS4 137 DQS4# DM4 138 CD@

2
139 DQS4 VSS_32 140 DDRA_DQ38 2 2 RD12
DDRA_DQ34 141 VSS_31 DQ38 142 DDRA_DQ39 24.9_0402_1%
DDRA_DQ35 143 DQ34 DQ39 144

2
145 DQ35 VSS_34 146 DDRA_DQ44
DDRA_DQ40 147 VSS_33 DQ44 148 DDRA_DQ45
DDRA_DQ41 149 DQ40 DQ45 150
DQ41 VSS_35 Layout Note: (10U_0603_6.3V)*2
C
151 152 DDRA_DQS#5
153 VSS_36 DQS5# 154 DDRA_DQS5 Place near DIMM
155 DM5 DQS5 156 (.1U_0402_10V)*4
DDRA_DQ42 157 VSS_37 VSS_38 158 DDRA_DQ46
DDRA_DQ43 159 DQ42 DQ46 160 DDRA_DQ47
161 DQ43 DQ47 162
DDRA_DQ48 163 VSS_39 VSS_40 164 DDRA_DQ52
DDRA_DQ49 165 DQ48 DQ52 166 DDRA_DQ53 +0.675VS
167 DQ49 DQ53 168
DDRA_DQS#6 169 VSS_41 VSS_42 170
DQS6# DM6
CD24

CD25

CD26

CD27

CD64

CD65
DDRA_DQS6 171 172
173 DQS6 VSS_44 174 DDRA_DQ54
VSS_43 DQ54
.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

10U_0603_6.3V6M

10U_0603_6.3V6M
DDRA_DQ50 175 176 DDRA_DQ55
DDRA_DQ51 177 DQ50 DQ55 178
DQ51 VSS_46 1 1 1 1 1 1
179 180 DDRA_DQ60
DDRA_DQ56 181 VSS_45 DQ60 182 DDRA_DQ61
DDRA_DQ57 183 DQ56 DQ61 184 CD@ CD@ CD@
185 DQ57 VSS_48 186 DDRA_DQS#7 2 2 2 2 2 2
187 VSS_47 DQS7# 188 DDRA_DQS7
189 DM7 DQS7 190
A DDRA_DQ58 191 VSS_49 VSS_50 192 DDRA_DQ62 A
DDRA_DQ59 193 DQ58 DQ62 194 DDRA_DQ63
195 DQ59 DQ63 196
1 @ 2 0_0402_5% 197 VSS_51 VSS_52 198
RD13 199 SA0 EVENT# 200 SMB_DATA_S3
+3VS VDDSPD SDA SMB_DATA_S3 7,15,40
201 202 SMB_CLK_S3
SA1 SCL SMB_CLK_S3 7,15,40
1 1 203 204 +0.675VS
VTT_1 VTT_2
1

@ Security Classification LC Future Center Secret Data Title


CD28 CD29
0_0402_5%
205 206 1 0.65A@0.75V
2.2U_0603_6.3V6K .1U_0402_10V6-K 207 GND1 GND2 208 CD68
2 2 RD14 BOSS1 BOSS2 33P_0402_50V8J
Issued Date 2013/08/08 Deciphered Date 2013/08/05 DDRIII SO-DIMM A
@
2

2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
LCN_DAN06-K4406-0103 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
ME@ For RF DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLUA
Date: Thursday, December 26, 2013 Sheet 14 of 59
5 4 3 2 1

PDF created with pdfFactory Pro trial version www.pdffactory.com


5 4 3 2 1

DDR_SB_VREFDQ 6

+1.35V
DDR3 SO-DIMM B Swap Table
Pin
+1.35V +1.35V Pin Name Net Name
Number

1
DDRB_DQ[0..63] 6
RD15 5 DQ0 DDRB_DQ17
1.82K_0402_1% 3A@1.5V 7 DQ1 DDRB_DQ23
DDRB_DQS[0..7] 6
RD16 For RF 15 DQ2 DDRB_DQ18
JDDR2
DDRB_DQS#[0..7] 6

2
1 2 +VREF_DQ_DIMMB 1 2 17 DQ3 DDRB_DQ21
2_0402_5% 3 VREF_DQ VSS1 4 DDRB_DQ16 4 DQ4 DDRB_DQ16
VSS2 DQ4 DDRB_MA[0..15] 6

1.82K_0402_1%

CD30

2.2U_0603_6.3V6K

CD31

.1U_0402_10V6-K

33P_0402_50V8J

33P_0402_50V8J

33P_0402_50V8J
DDRB_DQ17 5
DQ0 DQ5
6 DDRB_DQ22 6 DQ5 DDRB_DQ22
1
0.022U_0402_16V7-K

1 1 DDRB_DQ23 7 8 1 1 1 16 DQ6 DDRB_DQ19


DQ1 VSS3

RD17

CD33

CD34

CD35
D 9 10 DDRB_DQS#2 @ @ @ D
11 VSS4 DQS#0 12 DDRB_DQS2
18 DQ7 DDRB_DQ20
1 DM0 DQS0 10 DQS#0 DDRB_DQS#2
CD32

CD@ 13 14
2 2 DDRB_DQ18 15 VSS5 VSS6 16 DDRB_DQ19 2 2 2 12 DQS0 DDRB_DQS2
2

DDRB_DQ21 17 DQ2 DQ6 18 DDRB_DQ20


2 19 DQ3 DQ7 20
VSS7 VSS8
21 DQ8 DDRB_DQ3
DDRB_DQ3 21 22 DDRB_DQ2 23 DQ9 DDRB_DQ5
DDRB_DQ5 23 DQ8 DQ12 24 DDRB_DQ4
DQ9 DQ13 33 DQ10 DDRB_DQ6
1

25 26
RD18 DDRB_DQS#0 27 VSS9 VSS10 28 35 DQ11 DDRB_DQ1
24.9_0402_1% DDRB_DQS0 29 DQS#1 DM1 30 CPU_DRAMRST# 22 DQ12 DDRB_DQ2
DQS1 RESET# CPU_DRAMRST# 5,14
31
VSS11 VSS12
32 24 DQ13 DDRB_DQ4
DDRB_DQ6 33 34 DDRB_DQ0 34 DQ14 DDRB_DQ0
2

DDRB_DQ1 35 DQ10 DQ14 36 DDRB_DQ7


37 DQ11 DQ15 38 Layout Note:
(10uF_0603_6.3V)*8 36 DQ15 DDRB_DQ7
DDRB_DQ8 39 VSS13 VSS14 40 DDRB_DQ13 27 DQS#1 DDRB_DQS#0
DDRB_DQ10 41 DQ16 DQ20 42 DDRB_DQ12 Place near DIMM (1U_0402_6.3V)*8 29 DQS1 DDRB_DQS0
43 DQ17 DQ21 44
DDRB_DQS#1 45 VSS15 VSS16 46 (.1U_0402_10V6-K)*4 39 DQ16 DDRB_DQ8
DDRB_DQS1 47 DQS#2 DM2 48
DQS2 VSS17 41 DQ17 DDRB_DQ10
49 50 DDRB_DQ9
DDRB_DQ14 51 VSS18 DQ22 52 DDRB_DQ11
51 DQ18 DDRB_DQ14

l
DDRB_DQ15 53 DQ18 DQ23 54 53 DQ19 DDRB_DQ15
55 DQ19 VSS19 56 DDRB_DQ31 +1.35V 40 DQ20 DDRB_DQ13
VSS20 DQ28

tia
DDRB_DQ27 57 58 DDRB_DQ30 42 DQ21 DDRB_DQ12
DDRB_DQ26 59 DQ24 DQ29 60
DQ25 VSS21 50 DQ22 DDRB_DQ9

CD36

CD37

CD38

CD39

CD40

CD41

CD42

CD43
61 62 DDRB_DQS#3
63 VSS22 DQS#3 64 DDRB_DQS3
52 DQ23 DDRB_DQ11
DM3 DQS3 45 DQS#2 DDRB_DQS#1

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
65 66
DDRB_DQ28 67 VSS23 VSS24 68 DDRB_DQ29 47 DQS2 DDRB_DQS1
DQ26 DQ30 1 1 1 1 1 1 1 1
DDRB_DQ24 69 70 DDRB_DQ25 CD@ CD@
71 DQ27 DQ31 72
VSS25 VSS26
57 DQ24 DDRB_DQ27
C C
2 2 2 2 2 2 2 2 59 DQ25 DDRB_DQ26
67 DQ26 DDRB_DQ28
DDRB_CKE0 73 74 DDRB_CKE1 69 DQ27 DDRB_DQ24
6 DDRB_CKE0 CKE0 CKE1 DDRB_CKE1 6
75 76 56 DQ28 DDRB_DQ31

en
VDD1 VDD2
77
NC1 A15
78 DDRB_MA15 58 DQ29 DDRB_DQ30
6 DDRB_BS2# DDRB_BS2# 79 80 DDRB_MA14 68 DQ30 DDRB_DQ29
81 BA2 A14 82
DDRB_MA12 83 VDD3 VDD4 84 DDRB_MA11
70 DQ31 DDRB_DQ25
A12/BC# A11 62 DQS#3 DDRB_DQS#3

CD44

CD45

CD46

CD47

CD60

CD61

CD62

CD63
DDRB_MA9 85 86 DDRB_MA7
87 A9 A7 88 64 DQS3 DDRB_DQS3
VDD5 VDD6

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
DDRB_MA8 89 90 DDRB_MA6
DDRB_MA5 91 A8 A6 92 DDRB_MA4
A5 A4 1 1 1 1 1 1 1 1 129 DQ32 DDRB_DQ33
93 94 131 DQ33 DDRB_DQ36
DDRB_MA3 95 VDD7 VDD8 96 DDRB_MA2
DDRB_MA1 97 A3 A2 98 DDRB_MA0 CD@ CD@ CD@ CD@
141 DQ34 DDRB_DQ39
99 A1 A0 100 2 2 2 2 2 2 2 2 143 DQ35 DDRB_DQ38
DDRB_CLK0 101 VDD9 VDD10 102 DDRB_CLK1 130 DQ36 DDRB_DQ37
6 DDRB_CLK0 CK0 CK1 DDRB_CLK1 6

fid
6 DDRB_CLK0# DDRB_CLK0# 103
CK0# CK1#
104 DDRB_CLK1#
DDRB_CLK1# 6 132 DQ37 DDRB_DQ32
105 106 140 DQ38 DDRB_DQ35
DDRB_MA10 107 VDD11 VDD12 108 DDRB_BS1#
DDRB_BS0# 109 A10/AP BA1 110 DDRB_RAS#
DDRB_BS1# 6 142 DQ39 DDRB_DQ34
6 DDRB_BS0# BA0 RAS# DDRB_RAS# 6 135 DQS#4 DDRB_DQS#4
111 112
DDRB_WE# 113 VDD13 VDD14 114 DDRB_CS0# 137 DQS4 DDRB_DQS4
6 DDRB_WE# WE# S0# DDRB_CS0# 6
6 DDRB_CAS# DDRB_CAS# 115 116 DDRB_ODT0
CAS# ODT0 DDRB_ODT0 5
117 118 147 DQ40 DDRB_DQ40
DDRB_MA13 119 VDD15 VDD16 120 DDRB_ODT1
A13 ODT1 DDRB_ODT1 5 149 DQ41 DDRB_DQ43
DDRB_CS1# 121 122
6 DDRB_CS1#
123 S1# NC2 124
157 DQ42 DDRB_DQ42
125 VDD17 VDD18 126 +VREF_CB RD19 1 2 0_0402_5% 159 DQ43 DDRB_DQ44
NCTEST VREF_CA +VREF_CA 14 146 DQ44 DDRB_DQ45
127 128 @

B
DDRB_DQ33
DDRB_DQ36

DDRB_DQS#4
129
131
133
135
VSS27
DQ32
DQ33
VSS29
DQS#4
VSS28
DQ36
DQ37
VSS30
DM4
130
132
134
136
on DDRB_DQ37
DDRB_DQ32
CD48
1
.1U_0402_10V6-K

1
CD49
2.2U_0603_6.3V6K
148
158
160
152
DQ45
DQ46
DQ47
DQS#5
DDRB_DQ41
DDRB_DQ46
DDRB_DQ47
DDRB_DQS#5
B

DDRB_DQS4 137 138 CD@


139 DQS4 VSS31 140 DDRB_DQ35 2 2 154 DQS5 DDRB_DQS5
DDRB_DQ39 141 VSS32 DQ38 142 DDRB_DQ34
143 DQ34 DQ39 144
DDRB_DQ38
DQ35 VSS33
163 DQ48 DDRB_DQ52
145 146 DDRB_DQ45 165 DQ49 DDRB_DQ51
DDRB_DQ40 147 VSS34 DQ44 148 DDRB_DQ41
DQ40 DQ45 Layout Note: (10U_0603_6.3V)*2 175 DQ50 DDRB_DQ50
DDRB_DQ43 149 150
151 DQ41 VSS35 152 DDRB_DQS#5 Place near DIMM 177 DQ51 DDRB_DQ48
153 VSS36 DQS#5 154 DDRB_DQS5 (.1U_0402_10V)*4 164 DQ52 DDRB_DQ49
DM5 DQS5
C
155
VSS37 VSS38
156 166 DQ53 DDRB_DQ53
DDRB_DQ42 157 158 DDRB_DQ46 174 DQ54 DDRB_DQ54
DDRB_DQ44 159 DQ42 DQ46 160 DDRB_DQ47
161 DQ43 DQ47 162
176 DQ55 DDRB_DQ55
DDRB_DQ52 163 VSS39 VSS40 164 DDRB_DQ49 +0.675VS 169 DQS#6 DDRB_DQS#6
DDRB_DQ51 165 DQ48 DQ52 166 DDRB_DQ53 171 DQS6 DDRB_DQS6
167 DQ49 DQ53 168
VSS41 VSS42
CD50

CD51

CD52

CD53

CD66

CD67
DDRB_DQS#6 169 170 181 DQ56 DDRB_DQ62
DDRB_DQS6 171 DQS#6 DM6 172
DQS6 VSS43 183 DQ57 DDRB_DQ57
.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

10U_0603_6.3V6M

10U_0603_6.3V6M
173 174 DDRB_DQ54
DDRB_DQ50 175 VSS44 DQ54 176 DDRB_DQ55
191 DQ58 DDRB_DQ59
DQ50 DQ55 1 1 1 1 1 1 193 DQ59 DDRB_DQ63
DDRB_DQ48 177 178
179 DQ51 VSS45 180 DDRB_DQ56 180 DQ60 DDRB_DQ56
181 VSS46 DQ60 182
DDRB_DQ62
DQ56 DQ61
DDRB_DQ61 CD@ CD@ CD@ 182 DQ61 DDRB_DQ61
DDRB_DQ57 183 184 2 2 2 2 2 2
DQ57 VSS47 192 DQ62 DDRB_DQ58
185 186 DDRB_DQS#7
187 VSS48 DQS#7 188 DDRB_DQS7
194 DQ63 DDRB_DQ60
189 DM7 DQS7 190 186 DQS#7 DDRB_DQS#7
DDRB_DQ59 191 VSS49 VSS50 192 DDRB_DQ58 188 DQS7 DDRB_DQS7
DDRB_DQ63 193 DQ58 DQ62 194 DDRB_DQ60
A 195 DQ59 DQ63 196 A
RD20 1 2 @ 197 VSS51 VSS52 198
0_0402_5% 199 SA0 EVENT# 200 SMB_DATA_S3
VDDSPD SDA SMB_DATA_S3 7,14,40
1 2 201 202 SMB_CLK_S3
+3VS SA1 SCL SMB_CLK_S3 7,14,40
RD21 10K_0402_5% 203 204 +0.675VS
VTT1 VTT2 0.65A@0.75V
1 1
205 206 1
CD54 CD55 G1 G2 CD69
Security Classification LC Future Center Secret Data Title
2.2U_0603_6.3V6K .1U_0402_10V6-K LCN_DAN06-K4406-0102 33P_0402_50V8J
2 2 @
ME@ 2 Issued Date 2013/08/08 Deciphered Date 2013/08/05 DDRIII SO-DIMM B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
For RF DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLUA
Date: Thursday, December 26, 2013 Sheet 15 of 59
5 4 3 2 1

PDF created with pdfFactory Pro trial version www.pdffactory.com


5 4 3 2 1

D D

C C

l
tia
en
B B

fid
A
on A

Security Classification LC Future Center Secret Data Title


Issued Date 2013/08/08 Deciphered Date 2013/08/05 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLUA
Date: Thursday, December 26, 2013 Sheet 16 of 59
C
5 4 3 2 1

PDF created with pdfFactory Pro trial version www.pdffactory.com


5 4 3 2 1

D D

C C

l
tia
en
B B

fid
A
on A

Security Classification LC Future Center Secret Data Title


Issued Date 2013/08/08 Deciphered Date 2013/08/05 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLUA
Date: Thursday, December 26, 2013 Sheet 17 of 59
C
5 4 3 2 1

PDF created with pdfFactory Pro trial version www.pdffactory.com


5 4 3 2 1

N15x GPIO
Performance Mode P0 TDP at Tj = 102 C* (DDR3)
GPIO I/O ACTIVE Function Description
FBVDDQ PCI Express I/O and Other
GPU Mem NVCLK FBVDD (GPU+Mem) (1.05V) PLLVDD
GPIO0 OUT - FB Enable for GC6 2.0 (4) (1,5) /MCLK NVVDD (1.35V) (1.35V) (6) (1.05V) (3.3V)
Products (W) (W) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA) (W) (mA) (W) (mA) (W)
D GPIO1 OUT N/A D

N14X
GPIO2 OUT N/A 128bit TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
2GB
DDR3
GPIO3 OUT N/A

GPIO4 OUT N/A

GPIO5 OUT N/A GPU power sequencing---3V3_MAIN_EN

GPIO6 IN - GPU wake signal for GC6 2.0

GPIO7 OUT N/A

GPIO8 I/O - System side PCIe reset Monitor

GPIO9 I/O N/A 2.2K Pull-up

l
N15x Multi-level Straps
GPIO10 OUT N/A

tia
GPIO11 OUT - GPU Core VDD PWM control signal

GPIO12 IN AC Power Detect Input (10K pull High)


Physical Logical Logical Logical Logical
GPIO13 OUT - Phase Shedding Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
C ROM_SCLK +3VGS SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED C
GPIO14 IN N/A
ROM_SI +3VGS RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
GPIO15 IN N/A ROM_SO +3VGS DEVID_SEL PCIE_CFG SMB_ALT_ADDR VGA_DEVICE

en
STRAP0 +3VGS Reserved(keep pull-up and pull-down footprint and stuff 50Kohm pull-up)
GPIO16 N/A
STRAP1 +3VGS
GPIO17 IN N/A STRAP2 +3VGS
Reserved(keep pull-up and pull-down footprint and not stuff by default)
STRAP3 +3VGS
GPIO18 IN N/A
STRAP4 +3VGS
GPIO19 IN N/A

GPIO20 N/A SMBUS_ALT_ADDR

fid
GPIO21 OUT GPU PCIe self-reset control 0 0x9E (Default)

OVERT OUT Active Low Thermal Catastrophic Over Temperature 1 0x9C (Multi-GPU usage)

N15V-GM Power Sequence

+3VG_AON Other Power rail


on N15x Binary Straps B

+VGA_CORE
+3VG_AON
Physical
tNVVDD >0 Power Rail Strap Mapping
Strapping pin
+1.35VGS
Tpower-off <10ms ROM_SCLK +3VGS SMB_ALT_ADDR
tFBVDDQ >0
ROM_SI +3VGS SUB_VENDOR
C
+1.05VS_VGA
ROM_SO +3VGS VGA_DEVICE
tPEX_VDD >0
STRAP0 +3VGS RAM_CFG[0]
1.all GPU power rails should be turned off within 10ms STRAP1 +3VGS RAM_CFG[1]
1. all power rail ramp up time should be larger than 40us 2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ
STRAP2 +3VGS RAM_CFG[2]
STRAP3 +3VGS RAM_CFG[3]
STRAP4 +3VGS PCIE_MAX_SPEED
N15S-GT Power Sequence

+3VG_AON

+VGA_CORE
A A

tNVVDD >0
+1.05VS_VGA

+1.35VGS
tPEX_VDD >0
Security Classification LC Future Center Secret Data Title

1. all power rail ramp up time should be larger than 40us Issued Date 2013/08/08 Deciphered Date 2013/08/05 VGA Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLUA
Date: Thursday, December 26, 2013 Sheet 18 of 59
5 4 3 2 1

PDF created with pdfFactory Pro trial version www.pdffactory.com


5 4 3 2 1

RV1 1 GC6@ 2 0_0402_5% FB_GC6_EN_R


4 GPIO52
RV2 1 GC6@ 2 0_0402_5% GPU_EVENT#
4 GPIO53

9 PCIE_CRX_GTX_N[0..3]

9 PCIE_CRX_GTX_P[0..3]

9 PCIE_CTX_C_GRX_N[0..3]
UV1A
9 PCIE_CTX_C_GRX_P[0..3]
+3VGS
Part 1 of 6 1 RV175 2 0_0402_5%
H_THRMTRIP# 9
PCIE_CTX_C_GRX_P0 AG6 C6 FB_GC6_EN @
D PEX_RX0 GPIO0 FB_GC6_EN 23 D

.1U_0402_10V6-K
+3VG_AON +3VG_AON PCIE_CTX_C_GRX_N0 AG7 B2
PEX_RX0_N GPIO1

1
PCIE_CTX_C_GRX_P1 AF7 D6 1
PCIE_CTX_C_GRX_N1 AE7 PEX_RX1 GPIO2 C7 RV4
PCIE_CTX_C_GRX_P2 AE9 PEX_RX1_N GPIO3 F9 10K_0402_5% CV1
2

PCIE_CTX_C_GRX_N2 AF9 PEX_RX2 GPIO4 A3 3VGS_PWR_EN @ @


PEX_RX2_N GPIO5 3VGS_PWR_EN 21,58

3
RV3 RV5 PCIE_CTX_C_GRX_P3 AG9 A4 GPU_EVENT#_R D 2

2
PEX_RX3 GPIO6

5
2.2K_0402_5% 2.2K_0402_5% PCIE_CTX_C_GRX_N3 AG10 B6 5

G
OPT@ OPT@ AF10 PEX_RX3_N GPIO7 E9 SYS_PEX_RST_MON# G
AE10 NC81 GPIO8 F8 VGA_ALERT#
A6 Symbol update to OVER QV2B
1

NC82 GPIO9

6
AE12 C5 D S 2N7002KDWH_SOT363-6

4
VGA_SMB_CK2 4
S 3 AF12 NC83 GPIO10 E7 NVVDD_PWM_VID DV1 OVERT# 2 @
EC_SMB_CK2 7,39,44 NC84 GPIO11 NVVDD_PWM_VID 58

D
AG12 D7 VGA_AC_DET_R 2 1 G
NC85 GPIO12 VGA_AC_DET 44
AG13 B4 PSI_VGA_R @ QV2A

GPIO
QV1B AF13 NC86 GPIO13 B3 RB751V-40_SOD323-2 S 2N7002KDWH_SOT363-6

1
2N7002KDWH_SOT363-6 AE13 NC87 GPIO14 C3 @
NC88 GPIO15 2 RV6
2

OPT@ AE15 D5 1 PSI_VGA


G

NC1 GPIO16 PSI_VGA 58

1
RV7 2 @ 1 0_0402_5% AF15 D4 N15SGT@ 0_0402_5% D
NC2 GPIO17

.1U_0402_10V6-K
AG15 C2 PLT_RST_VGA# 1 RV8 2 0_0402_5% 2 1
AG16 NC3 GPIO18 F7 @ G
NC4 GPIO19

.1U_0402_10V6-K
VGA_SMB_DA2 1 6 AF16 E6 QV3 CV2
S

EC_SMB_DA2 7,39,44 NC5 GPIO20


D

AE16 C4 GPU_PEX_RST_HOLD# S 2N7002KW_SOT323-3 @

3
AE18 NC6 GPIO21 @ 2
NC7 1
QV1A AF18 A6 OVERT# CV3
2N7002KDWH_SOT363-6 AG18 NC8 OVERT AB6
OPT@ AG19 NC9 NC33 @
RV9 2 @ 1 0_0402_5% AF19 NC10 RV174 2
PU AT EC SIDE, +3VS AND 4.7K
AE19 NC11 PLT_RST_VGA# 1 2 1K_0402_5%
NC12

.1U_0402_10V6-K
AE21 AG3
AF21 NC13 NC97 AF4 @
NC14 NC98 1
AG21 AF3 CV218

l
NC15 NC99

2
AG22 @

G
NC16 +3VG_AON +3VG_AON
2

tia
+3VS PCIE_CRX_GTX_P0 CV10 1 2 .1U_0402_10V6-K PCIE_CRX_C_GTX_P0 AC9 AE3

DACs
RV10 PCIE_CRX_GTX_N0 CV13 1 2 .1U_0402_10V6-K PCIE_CRX_C_GTX_N0 AB9 PEX_TX0 NC100 AE4 OVERT# 3 1
PEX_TX0_N NC101 WRST# 44

D
+3VGARST 2 @ 1 PCIE_CRX_GTX_P1 CV8 1 2 .1U_0402_10V6-K PCIE_CRX_C_GTX_P1 AB10
PCIE_CRX_GTX_N1 CV9 1 2 .1U_0402_10V6-K PCIE_CRX_C_GTX_N1 AC10 PEX_TX1
PEX_TX1_N 1 QV23

.1U_0402_10V6-K
1 2 AD11

PCI EXPRESS
C 0_0402_5% +3VG_AON PCIE_CRX_GTX_P2 CV6 .1U_0402_10V6-K PCIE_CRX_C_GTX_P2 1 C
PCIE_CRX_GTX_N2 CV7 1 2 .1U_0402_10V6-K PCIE_CRX_C_GTX_N2 AC11 PEX_TX2 W5 CV221 2N7002KW_SOT323-3 RV13
RV12 1 2 0_0402_5% PCIE_CRX_GTX_P3 CV4 1 2 .1U_0402_10V6-K PCIE_CRX_C_GTX_P3 AC12 PEX_TX2_N NC102 AE2 0.01U_0402_25V7K @ 10K_0402_5% CV12
PEX_TX3 NC103

2
@ PCIE_CRX_GTX_N3 CV5 1 2 .1U_0402_10V6-K PCIE_CRX_C_GTX_N3 AB12 AF2 @ 2 GC6@ GC6@

G
AB13 PEX_TX3_N NC104 2

1
AC13 NC89
1 NC90
AD14
UV2 NC91
CV11 AC14 GPU_EVENT#_R 3 1 GPU_EVENT#
NC92

D
.1U_0402_10V6-K AC15
PLT_RST# 1 5 2 OPT@ AB15 NC93 QV4
8,37,40,44 PLT_RST# B VCC NC94
AB16 B7 VGA_CRT_CLK 2N7002KW_SOT323-3
2 AC16 NC95 I2CA_SCL A7 VGA_CRT_DATA GC6@
4 PXS_RST# A NC96 I2CA_SDA Connect to CPU GPIO

en
AD17 I2C,if not use, can be soft grounded
3 4 SYS_PEX_RST_MON# AC17 NC17 C9 I2CB_SCL 1 @ 2 RV15
GND Y AC18 NC18 I2CB_SCL C8 I2CB_SDA
and delete pull up resistor ---colin 0_0402_5%
NC19 I2CB_SDA

I2C
AB18
AB19 NC20 A9 I2CC_SCL
74LVC1G08GW_SOT353-1-5 AC19 NC21 I2CC_SCL B9 I2CC_SDA
OPT@ 2 1 AD20 NC22 I2CC_SDA
RV14 10K_0402_5% AC20 NC23 D9 VGA_SMB_CK2 +3VG_AON +3VG_AON
OPT@ AC21 NC24 I2CS_SCL D8 VGA_SMB_DA2
NC25 I2CS_SDA Internal Thermal Sensor
AB21
1 2 RV16 AD23 NC26
@ 0_0402_5% AE23 NC27 VGA_CRT_DATA RV17 1 2 3VGS_PWR_EN 1 RV18 2
AF24 NC28 60mA OPT@ 2.2K_0402_5% OPT@ 10K_0402_5%
AE24 NC29 L6 +PLLVDD VGA_CRT_CLK RV19 1 2 OVERT# 2 RV20 1
AG24 NC30 CORE_PLLVDD M6 OPT@ 2.2K_0402_5% OPT@ 10K_0402_5%
AG25 NC31 SP_PLLVDD I2CB_SCL RV22 1 2 VGA_ALERT# 2 RV23 1
NC32 N6
45mA 1 2 RV24 +SP_PLLVDD OPT@ 2.2K_0402_5% OPT@ 10K_0402_5%
VID_PLLVDD

fid
45mA @ 0_0402_5% I2CB_SDA RV25 1 2 VGA_AC_DET_R RV26 1 2
OPT@ 2.2K_0402_5% OPT@ 100K_0402_5%
+3VGS +3VG_AON 8 CLK_PCIE_GPU CLK_PCIE_GPU AE8 I2CC_SCL RV28 1 2 PSI_VGA RV29 1 2
CLK_PCIE_GPU# AD8 PEX_REFCLK OPT@ 2.2K_0402_5% OPT@ 10K_0402_5%
8 CLK_PCIE_GPU# PEX_REFCLK_N
CLK_REQ_GPU# AC6 I2CC_SDA RV30 1 2 GPU_PEX_RST_HOLD# RV31 1 2
PEX_CLKREQ_N OPT@ 2.2K_0402_5% OPT@ 10K_0402_5%
1 2 RV32 PEX_TSTCLK_OUT AF22 XTALOUT RV33 1 2

CLK
Differential signal @ 200_0402_1% PEX_TSTCLK_OUT# AE22 PEX_TSTCLK C11 XTAL_IN @ 10K_0402_5%
2

PEX_TSTCLK_N XTAL_IN B10 XTAL_OUT


B RV180 RV37 XTAL_OUT B
2.2K_0402_5% 10K_0402_5% PLT_RST_VGA# AC7 A10 XTALSSIN 1 OPT@ 2 RV34 10K_0402_5%
GC6@ @ 1 2 RV35 PEX_TERMP AF25 PEX_RST_N XTAL_SSIN C10 XTALOUT 1 OPT@ 2 RV36 10K_0402_5%
DV6 PEX_TERMP XTAL_OUTBUFF Under GPU(below 150mils)
OPT@ 2.49K_0402_1% 180ohms (ESR=0.2) Bead
1

GPU_PEX_RST_HOLD# 2
1 PLT_RST_VGA# N15S-GT-S-A2_FCBGA595 +SP_PLLVDD 1 2 LV1 +1.05VGS
SYS_PEX_RST_MON# 3 N15SGT@ PBY160808T-181Y-N_2P

22U_0805_6.3V6M
0.1U_0402_10V7K

0.1U_0402_10V7K

4.7U_0402_6.3V6M
BAT54AWT1G_SOT323-3
GC6@
on 150mA

2
1

OPT@
CV15
1

2
OPT@
CV16
1

2
OPT@
CV17
1

2
OPT@
CV18 OPT@

1 2 RV39
N15VGM@ 0_0402_5%

1 2 RV38
change to BAT54A for cost down OPT@ 10M_0402_5%
YV1
Under GPU Near GPU 30ohms (ESR=0.05) Bead
+3VG_AON +3VG_AON XTAL_IN 1 4
OSC1 GND2 +PLLVDD 1 2 LV2 +1.05VGS
2 3 XTAL_OUT
GND1 OSC2

10P_0402_50V8J

10P_0402_50V8J
PBY160808T-300Y-N_2P
C
1 1
2

1 1 OPT@
RV40 RV41 CV19 CV20 CV21 CV22
10K_0402_5% 10K_0402_5% OPT@ 27MHZ_10PF_7V27000050 OPT@ 0.1U_0402_10V7K 22U_0805_6.3V6M
OPT@ @ OPT@ 2 2 OPT@
OPT@
2 2
1

+3VG_AON +3VG_AON
.1U_0402_10V6-K

.1U_0402_10V6-K

1 1
CV23 CV24
OPT@ @
2

2
2

A
2 RV44 2 RV45 A
G

10K_0402_5% 10K_0402_5%
OPT@ @
1

8 GPU_CLKREQ# 1 3 CLK_REQ_GPU# FB_GC6_EN_R 1 3 FB_GC6_EN


D

QV5 QV6
2

2N7002KW_SOT323-3 2N7002KW_SOT323-3
OPT@ RV46 @ RV47
10K_0402_5% 10K_0402_5%
@
Connect to CPU GPIO GC6@ Title
1 2 RV48 1 2 RV49 Security Classification LC Future Center Secret Data
1

@ 0_0402_5% GC6@ 0_0402_5%


Issued Date 2013/08/08 Deciphered Date 2013/08/05 N15X_PCIE/ DAC/ GPIO
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLUA
Date: Tuesday, December 31, 2013 Sheet 19 of 59
5 4 3 2 1

PDF created with pdfFactory Pro trial version www.pdffactory.com


5 4 3 2 1

D D

UV1C

Part 3 of 6 F11
AC3 NC50 AD10
AC4 NC105 NC51 AD7
Y4 NC106 NC52
Y3 NC107 V5
B19 Symbol update to FBA_CMD32
AA3 NC108 FERMI_RSVD1 V6
AA2 NC109 FERMI_RSVD2 G1
AB1 NC110 NC56 G2
NC111 NC57

NC
AA1 G3
AA4 NC112 NC58 G4
AA5 NC113 NC59 G5
NC114 NC60 G6
NC61 G7
AB5 NC62 V1
AB4 NC115 NC63 V2
AB3 NC116 NC64 W1
AB2 NC117 NC65 W2
AD3 NC118 NC66 W3
AD2 NC119 NC67 W4
AE1 NC120 NC68
AD1 NC121
AD4 NC122

l
AD5 NC123
NC124 D11 2 1 RV50
BUFRST_N @ 10K_0402_5%

tia
LVDS/TMDS
T2
T3 NC125 D10
T1 NC126 PGOOD
R1 NC127 E10
R2 NC128 NC71

GENERAL
R3 NC129 F10
N2 NC130 NC72
N3 NC131 Symbol update to GPIO8
NC132 D1 STRAP0
STRAP0 D2 STRAP0 28
C STRAP1 C
V3 STRAP1 E4 STRAP1 28
STRAP2
V4 NC133 STRAP2 E3 STRAP3 STRAP2 28
U3 NC134 STRAP3 D3 STRAP3 28
STRAP4
U4 NC135 STRAP4 C1 STRAP4 28
NC136 NC73

en
T4
T5 NC137
R4 NC138 F6 1 2 RV51
R5 NC139 MULTI_STRAP_REF0_GND F4 N15SGT@ 40.2K_0402_1%
NC140 MULTI_STRAP_REF1_GNDMLS_REF1 F5
MULTI_STRAP_REF2_GND
N1
M1 NC34
M2 NC35 F12
M3 NC36 THERMDP
K2 NC37 E12
K3 NC38 THERMDN
K1 NC39
J1 NC40
NC41

fid
M4 F2 VCCSENSE_VGA
NC42 VDD_SENSE VCCSENSE_VGA 58
M5
L3 NC43
NC44 trace width: 16mils
L4
K4 NC45 differential voltage sensing.
NC46 differential signal routing.
K5
J4 NC47 F1 VSSSENSE_VGA
NC48 GND_SENSE VSSSENSE_VGA 58

J5
N4 NC49
N5 NC141 TEST
NC142

B
P3
P4

J2
NC143
NC144
TESTMODE
JTAG_TCK
on
JTAG_TDI
JTAG_TDO
AD9
AE5
AE6
AF6
AD6
TESTMODE
@
@
@
1
1
1
1
1 OPT@
TV1
TV2
TV3
2 RV52
10K_0402_5%
B

@
J3 NC145 JTAG_TMS AG4 1TV4 2 RV53
NC146 JTAG_TRST_N OPT@ 10K_0402_5%

H3
H4 NC147
NC148 SERIAL
D12 @ 1
ROM_CS_N B12 TV5
ROM_SI
ROM_SI A12 ROM_SI 28
ROM_SO
ROM_SO C12 ROM_SO 28
ROM_SCLK
C
ROM_SCLK ROM_SCLK 28

N15S-GT-S-A2_FCBGA595
N15SGT@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 N15X_LVDS/ HDMI/ THERM


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLUA
Date: Thursday, December 26, 2013 Sheet 20 of 59
5 4 3 2 1

PDF created with pdfFactor