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# Middle Technical University Digital Electronic Lab.

## Electrical and Electronics First Stage

Technical Engineering College
Electrical Power Technical Engineering Dept. Mohammed D. Altamemi

Experement-9
S-R Flip-Flop

9-1 Object:

To study the S-R Flip-Flop, and to know the difference between S-R
Flip-Flop made by NAND, or NOR gates.

9-2 Theory:

## The basic digital memory circuit is obtained by the mutual coupling

of two circuits (N1 and N2 NAND gates with only one input) in the way
that is indicated in figure (9-1). The output of each gate is connected to
the input of the other, and this feedback combination is called Flip-Flop.
The most important property of the Flip-Flop is that it can remain in one
of two stable states: either the Q=1, called state 1, or the Q=0, called state
0.

## Figure (9-1) S-R Flip-Flop

Since the flip-flop has two stable state, it is also called binary,
bistable, or MULTI. As it can store one bit of information (either Q=1, or
Q=0), the result is a memory unit of 1 bit, or storage cell of 1 bit. Since
this information is closed or blocked in the same place, the flip-flop is
also called latch.

## Figure (9-2) shows us two NOR gates interconnected forming a

bistable S-R Flip-Flop. The table (9-1) shows the excitation table of S-R
NOR flip-flop.

‫د‬.‫م‬
Middle Technical University Digital Electronic Lab.
Electrical and Electronics First Stage
Technical Engineering College
Electrical Power Technical Engineering Dept. Mohammed D. Altamemi

S R Q Q(t+τ)
0 X 0 0
1 0 0 1
0 1 1 0
X 0 1 1
Table (9-1)

## 9-2-2 S-R NAND gates:

Figure (9-3) shows an S-R flip flop built with logical NAND gates.
The table (9-2) shows the excitation table of S-R NAND gate flip-flop,
take into account that in this case the inputs are the inverse, so the outputs
should also be so.

## Figure (9-3) S-R Flip-Flop with NAND gates

S R Q Q(t+τ)
1 X 0 0
0 1 0 1
1 0 1 0
X 1 1 1

‫د‬.‫م‬
Middle Technical University Digital Electronic Lab.
Electrical and Electronics First Stage
Technical Engineering College
Electrical Power Technical Engineering Dept. Mohammed D. Altamemi

9-3 Procedures:

## 2. Complete the truth table of the circuit, table (9-3).

S R Q Q(t+τ)
1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
0 0 1
0 0 0
Table (9-3)
3. Carry out the connections shown in figure (9-6).

‫د‬.‫م‬
Middle Technical University Digital Electronic Lab.
Electrical and Electronics First Stage
Technical Engineering College
Electrical Power Technical Engineering Dept. Mohammed D. Altamemi

S R Q Q(t+τ)
1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
0 0 1
0 0 0
Table (9-4)

9-4 Discussions:

## 1. What is the problem encountered in S-R flip-flop?

2. Try to build gated S-R flip flop and write its truth table
with new input CK.

‫د‬.‫م‬