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12, DECEMBER 2003

**A New Low Voltage Precision CMOS Current
**

Reference With No External Components

Rasoul Dehghani and S. M. Atarodi

Abstract—A novel current reference with low temperature and

m

supply sensitivity and without any external component has been

developed in a 0.25 mixed-mode process. The circuit is based

on a bandgap reference (BGR) voltage and a CMOS circuit sim-

ilar to a beta multiplier. An NMOS transistor in triode region has

been used in place of a resistor in conventional beta multiplier to

achieve a current which has a negative temperature coefficient and

only oxide thickness dependent. The BGR voltage has a positive

temperature coefficient to cancel the negative temperature coeffi-

cient of the beta multiplier. The simulation results using Bsim3v3

20 C +100 C

model show max-to-min fluctuation of less than 1% over a temper-

30%

ature range of to and a supply voltage range of

1.4 V to 3 V with tolerance for all of the used on-chip resis-

tors. The maximum current variation is slightly less than the oxide

thickness variation in the process corners.

Fig. 1. Architecture of the proposed current reference.

I. INTRODUCTION II. CURRENT REFERENCE ARCHITECTURE

**C URRENT reference as an essential block in analog IC’s
**

is needed in many analog signal processing applications

such as operational amplifier and data converter bias circuits.

The proposed architecture is composed of two main parts as

shown in Fig. 1. The first part is a BGR circuit with a positive

temperature coefficient output voltage Vr and the second part

Reference currents are often implemented by applying a is a quasi CMOS beta multiplier in which the resistor in con-

bandgap voltage reference across a resistor. The main problem ventional one has been replaced by an NMOS transistor (M1).

corresponding to this method concerns the used resistor. The drain-source voltage of M1 is controlled by Vr in a nega-

On-chip resistors are typically highly process-dependent, tive feedback loop established by the operational amplifier OP.

while off-chip resistors are not suitable due to cost and area The voltage Vr is less than M1 drain-source saturation voltage

considerations. Replacing resistor with its switched capacitor ( ), therefore, M1 operates in triode region. For M1 with

equivalent requires a separate frequency clock source and adequately long channel length, the drain current can be written

on-chip capacitors that leads to complexity and large area [1], as follows

[2]. Added digital noise to the circuit is another disadvantage

of the switched capacitor method. (1)

This work circumvents the need for an accurate on-chip re-

sistor without using any external component. In Section II, gen- Where: . is the inversion layer mo-

eral architecture of the proposed current reference is reviewed bility, is the gate oxide capacitance per unit area, is the

and the corresponding relations are derived. Section III is de- threshold voltage, and are the width and length of ,

voted to the description of the current reference components in- respectively. On the other hand, diode connected is in satu-

cluding BGR circuit, quasi CMOS beta multiplier, operational ration region and its current is

amplifiers, and startup circuit. The simulation results are pre-

sented in Section IV and conclusion is made in Section V. (2)

**Noting that , and , from (1) and
**

(2) the following relation is derived

Manuscript received February 18, 2003. The authors would like to express

their thanks to EMAD SEMICON CO. for financial supports. This paper was (3)

recommended by Associate Editor B. Razavi.

The authors are with the Department of Electrical Engineering, Sharif Uni- where and is the output current. For

versity of Technology, Tehran, Iran1 (e-mail: dehghani@mehr.sharif.edu). we have

Digital Object Identifier 10.1109/TCSII.2003.820239

1Note: New regulations imposed by the U.S. Government placed severe re-

(4)

strictions on the review process for this paper and prevented the editorial staff

of the journal from making any corrections to the paper. Please see the Editorial is a process independent voltage and has a low depen-

in this issue for more details. dency on process variations, thus the oxide thickness is the only

1057-7130/03$17.00 © 2003 IEEE

Authorized licensd use limted to: IE Xplore. Downlade on May 10,2 at 19:024 UTC from IE Xplore. Restricon aply.

Bandgap Reference The adopted bandgap reference circuit is shown in Fig. be set for . Using cascode devices and .to compromise the area and power dissipation.should be very large to avoid the corresponding coefficient for emitter-base voltage and the loading emitter-base voltages in and which results in second one has a positive temperature coefficient. The generated current is mirrored through M9-M10 with long-channel for and M7 (M4 and M6). is less than the saturation voltage of M1 so it is in triode region. Therefore. are n-well and -poly (without silicide) resistors to the emitter-base voltage and the current through the resistor with sheet resistance of 1100 and 180 and TCR of R5 to the difference of two emitter-base voltages.2 at 19:024 UTC from IE Xplore. the (5) change in with respect to temperature is obtained as Using . (9) and resistance) constitute a feedback loop through which the volt.DEHGHANI AND ATARODI: A NEW LOW VOLTAGE PRECISION CMOS CURRENT REFERENCE WITH NO EXTERNAL COMPONENTS 929 Fig. large area for these resistors. if is too low. Letting we will have Where . (10) Transistors . proper is Boltzman’s constant and is sizing of and sets the current independent of the electron charge) and is the ratio of the emitter areas of threshold voltage of the MOS transistors. assuming M7-M8 and M9-M10 have the same size. III. we can write the total current as follows B. a reasonable value must rent of M5 and M6 (M7 and M8) is the sum of these components. The first cur. The drain cur. In the process used in this design. . Quasi CMOS Beta Multiplier The schematic diagram of the circuit is shown in Fig. 2. 2. Downlade on May 10. from (4) we must have get (6). - current through the series connected R3 and R4 is proportional and . we achieve a and establishes a reference voltage across . Resistances in BGR circuit are determined to Substituting (8) into (9). 3.amp OP. rent component has a negative temperature coefficient due to In Fig. CIRCUIT DESCRIPTION A. the termined by process. In order to high compliance current source. In order to have an with approximately zero tem- perature coefficient. we obtain the relative variation of with respect to temperature as follows (8) (6) Where . (10) is the temperature coefficient of resistivity (TCR) and de- ages Ve1 and Ve are forced to be equal. in (4). main process parameter which affects the output current through Fig. 2. respectively. Restricon aply. The structure of the operational Authorized licensd use limted to: IE Xplore. This (7) circuit operates like a conventional gm-constant circuit [4] in which the source resistor has been replaced by an NMOS tran- Where: is thermal voltage ( sistor ( ) in triode region. Op. the required BGR temperature (9) coefficient must be about according to (5). As proved in Section II. transistors M5-M8 and resistors R1-R4 (all with the same The term in general form of in (8). As a consequence. In this design. Quasi CMOS beta multiplier circuit. . 3. and . results in satisfy (6) as described in the next section. after some manipulations on (5). Bandgap reference voltage with positive temperature coefficient. respectively. Therefore. Using . provide the bias voltages and for op amps and quasi CMOS beta multiplier.

in all process corners and with normal operation.930 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING. and . increases the total op amp gain and corner. for three different temperatures causing and to turn on. Restricon aply. 12. In maximum of variation in from TT to SS Fig. 0. 4. 4. The maximum change in is related to transition from TT to D. amplifiers used in BGR and quasi CMOS beta multiplier circuits IV. 2 enters the undesired point. SS (Slow-Slow). As a result. resistances. Simulations show that applying compensa. since at startup DC simulation results when supply voltage is swept Ve is greater than Ve1. gate. Cascode compensation in all corners. When the BGR circuit starts its ( ). Exploiting a cas. ages. Msp helps to start the quasi beta multiplier circuit by injecting is the maximum change of the output current in supply voltage Authorized licensd use limted to: IE Xplore.9% for the temperature change from folded cascode as shown in Fig. voltages SS or FF is . oxide thickness variation from TT to tion. process corners including TT (Typical model). TEMPERATURE. NMOS input folded cascode op amp. Operational Amplifiers precise simulations were performed to evaluate the effects of The schematic of the op amp used in the BGR circuit is shown the process variation on the generated current in five different in Fig. Con. but with NMOS-input resistance and is about 0.7% for change in in Fig. Msn turns on. ages . even slightly less than thickness variation. Various C. source and drain of Msn are connected to the volt. DECEMBER 2003 TABLE I SIMULATION RESULTS OF THE CURRENT REFERENCE VS. transistors in folded cascode stage reduces the total capacitance In Table I is the output current at (as of and to achieve a proper phase margin. in all process corners and for the supply voltage tion simultaneously to two source nodes of PMOS and NMOS have been summarized in Table I. The PMOS transistor is defined as the output current at . As mentioned before. . SUPPLY VOLTAGE. If the circuit in Fig.e. (FF) i. 50. Msn turns off in steady state. NO. this variation is related to the function is described as follows. 5.. PMOS input folded cascode op amp. IN ALL PROCESS CORNERS. Downlade on May 10.25 CMOS process. and to be equal. midrange temperature) and is the maximum change code topology in the output stage has the following advantages: of the output current in temperature range for each process it simplifies the bias circuit. nominal values for to are depicted in Table II.2 at 19:024 UTC from IE Xplore. for nominal and tolerance in compensation [3]. sequently. 3 has the same structure as . 5. respectively. 3 at startup and forcing Fig. IN ALL PROCESS CORNERS Fig. The toler- consists of a PMOS-input folded cascode as the first stage and a ance of was considered for the resistance of to cascode output stage in the second stage. It FF (Fast-Fast). SIMULATION RESULTS is described in the next section.25 CMOS process.4 V to 3 V. TABLE II SIMULATION RESULTS OF THE CURRENT REFERENCE VS. thus it is also used for in quasi beta multiplier. pulling down and from 1. The results obtained from Table I show a and will go to zero and approaches to [5]. DC simulation results over a temperature range was used to improve the bandwidth in comparison with Miller from to . In the used operating points: the desired one and the unwanted zero condi. As can be seen from Table I in each process corner. the reduces the op amp output sensitivity to the supply noise. The current reference simulation was carried out using Bsim3v3 models for a 0. 2. current to the gate of in Fig. VOL. OP makes voltages and equal. maximum variation in is less than 0. This structure is appropriate for low level input volt. to in the worst case (FF. ). FS (Fast-Slow) and SF (Slow-Fast). Startup Circuit SS or FF in which both threshold voltage and oxide thickness An innovative simple startup circuit has been exploited whose change. The BGR circuit has two stable oxide thickness variation in these process corners.

Costa. “A sub-1-V 15 0 ppm= C CMOS bandgap voltage reference without requiring low threshold voltage de- The ability of the startup circuit to force the current refer. vice . pp. Simulated output current vs. Garçao. Paulino. Finland.” in Circuits and Systems. Fig. Solid-State Circuits. time in various temperatures and process Fig. temperature for different resistances. Simulated output current vs. Espoo. MA: have been designed as low power as possible to reduce the total McGraw-Hill. 15’th ECCTD. ergy per conversion. E. R. with respect to the supply voltage at three different tempera. The output current is only oxide thickness dependent and is stable for a wide variation range in tempera- range for each process corner. vol. Boston. 921–924. sign of low-voltage CMOS pipelined ADC’s using 1 pico-Joule of en- The summarized specifications of two types operational am. plifiers used in the circuit are given in Table III. 6. temperature is shown for and in Fig. Q. REFERENCES The plot of the output current vs. ISCAS 2002. It can be found that the maximum ture and supply voltage. supply voltage for different temperatures. T. 7. Mok. pp. These op amps [4] B. no. Vaz. performing a transient analysis in all process corners. “Precision. Authorized licensd use limted to: IE Xplore. R. The power consumption of the whole current change over a 1. S. CONCLISION A new current reference with low temperature and voltage sensitivity was designed. TABLE III by applying a step function with 1 rise time for supply and SUMMARIZED SPECIFICATIONS OF THE CURRENT REFERENCE OP AMPS. 6. April ence circuit to settle in its proper stable point was evaluated 2002. “A low temper- proper layout. vol. temperature and supply independent CMOS current source with no external components. the output current if the matching among resistors is good by [2] S. M.” Electronics Letters. large absolute error in resistance ( ) has a little effect on 38.5 V.DEHGHANI AND ATARODI: A NEW LOW VOLTAGE PRECISION CMOS CURRENT REFERENCE WITH NO EXTERNAL COMPONENTS 931 Fig. pp. 8.39% in the worst case (which occurs for SS. Simulated output current vs. Schlarmanm. pp. IEEE International Symposium on. 526–530. Geiger. This low supply dependency of the output current is because of the long channel cascode devices used in the circuit. 392–393. N. 2001. vol. and A. tempera- ture range ( to ) and maximum tolerance in re- sistance ( ) which some of them are shown in Fig. corners. Malik. 4. Goes. J. December 2002. 2002.2 at 19:024 UTC from IE Xplore. [3] B.” IEEE J.4 V to 3 V supply range is less than current reference is 311 for a supply voltage of 1. Bernardson.” in Proc. Tavares. 37. vol. Downlade on May 10. [1] P. Design of Analog CMOS Integrated Circuits. As can be seen. 1. Fig. The circuit does not require any ex- ternal component and is robust against large absolute error in on-chip resistance. K. “De- tures. . 0. 7 shows the output current characteristics ature sensitivity switched-capacitor current reference. Aug 28–31. N. 8. power consumption of the current reference circuit. 25. and R. 269–272. Restricon aply. Leung and P. 2001. 2002. L. Razavi. 1. ). V. no. [5] K.

Since 1998.D. Iran. From 1991 to 1998. Restricon aply. and mixed-signal integrated circuit design as well as analog CAD tools. and M. design in 1993. Iran. He has published more than 30 technical papers in the area of analog quency synthesis. Authorized licensd use limted to: IE Xplore. from the University of California. He received the Ph. in 1988 and 1991. 50. He received the B. 12.Sc. he has worked as a senior design en. while working toward the Ph. from Amir Kabir University of Tech- M. Irvine. in 1987. Downlade on May 10. fre. He is currently a visiting professor at Sharif University of Tech- current research interests include RF IC design for wireless communication.E. in 1965.Sc. nology. he worked on developing several blocks for the receive from the University of Southern California (USC) on the subject of analog IC chain of a wireless communication system with the SUT. he designed and implemented various electronic circuits with communicational From 1993 to 1996 he worked with Linear Technology Corporation as a se- and industrial applications. nior analog design engineer.D. Since then. degree at the SUT. and Mojtaba Atarodi received the B.S.932 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING.2 at 19:024 UTC from IE Xplore.Sc. respectively. Tehran. . NO.E. degree in electrical engineering SUT. he has been consulting with different gineer with Emad Co. degree From 1987 to 1991. nology (Tehran Polytechnic) in 1985. VOL. degrees in electrical engineering from Sharif University of Technology. DECEMBER 2003 Rasoul Dehghani was born in Esfahan. His IC companies. and low-voltage and low-power circuits.

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