Physics of the Ferroelectric Nonvolatile Memory Field Effect Transistor

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Physics of the Ferroelectric Nonvolatile Memory Field Effect Transistor

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View online: http://dx.doi.org/10.1063/1.351910

View Table of Contents: http://aip.scitation.org/toc/jap/72/12

Published by the American Institute of Physics

Ferroelectric thin films: Review of materials, properties, and applications

Journal of Applied Physics 100, 051606 (2006); 10.1063/1.2336999

Journal of Applied Physics 68, 6463 (1998); 10.1063/1.346845

Applied Physics Letters 89, 253108 (2006); 10.1063/1.2408650

Journal of Applied Physics 44, 3379 (2003); 10.1063/1.1662770

voltage with ferroelectric HfO2 thin film

AIP Advances 6, 025113 (2016); 10.1063/1.4942427

Applied Physics Letters 99, 112901 (2011); 10.1063/1.3636417

Physics of the ferroelectric nonvolatile memory field effect transistor

S. L. Miller and P. J. McWhorter

Sandia National Laboratories, Albuquerque, New Mexico 87185

(Received 29 June 1992; accepted for publication 9 September 1992)

The operation of the ferroelectric nonvolatile memory field effect transistor is theoretically

examined extensively for the first time. The ferroelectric transistor device properties are derived

by combining the silicon charge-sheet model of metal-oxide-semiconductor field-effect transistor

device operation with Maxwell’s first equation which describes the properties of the ferroelectric

film. The model we present describes ferroelectric transistor 1-V and C-V behavior when

time-dependent voltages are applied which result in hysteresis due to ferroelectric switching. The

theoretical results provide unique insight into the effects of geometrical and material parameters

on the electrical properties of the transistor. These parameters include the ferroelectric

spontaneous and remanent polarization, the coercive field, and dielectric layer thicknesses. We

have found that the conventional concept of threshold voltage is no longer useful, and that

increasing the spontaneous polarization has only a minor impact on memory operation due to

reverse dipole switching of the ferroelectric layer. The application of the model to optimize

design and fabrication parameters is illustrated with a virtual prototyping example. The model

is also used to develop a practical testing methodology for this unique device.

development. The successful design of nonvolatile memo-

The hysteresis in the polarization of ferroelectric ma- ries implementing the ferroelectric transistor requires a

terials makes possible their use as electrically switchable thorough understanding of how electrical performance is

nonvolatile data storage elements.lb5 The more commonly related to design parameters. To characterize this relatively

implemented ferroelectric data storage element is a capac- unfamiliar device, new electrical characterization tech-

itor consisting of a thin ferroelectric film sandwiched be- niques must be developed which measure the fundamental

tween two conductive electrodes.677 The direction of the device properties. In order to rapidly optimize design and

ferroelectric polarization vector is set by a voltage pulse to fabrication parameters, and develop relevant characteriza-

the capacitor. The stored bit is read by applying another tion techniques, we need to quantitatively model the elec-

voltage pulse and determining whether or not the polariza- trical performance as a function of these parameters. This

tion switched direction. This method of nonvolatile mem- is a capability that has not been previously developed.

ory implementation suffers from the fact that data are de- To address this modeling need, we have derived and

stroyed during the reading process. Consequently the bit solved the equations governing the operation of the ferro-

must be reprogrammed after each read, resulting in the electric field effect transistor. The derivation of the model

accumulation of large numbers of read/write cycles. Dur- is presented in Sec. II. Numerical analysis techniques used

ing the read process data storage is volatile, i.e., data could to solve the resulting equations in a practical and efficient

be lost if power is lost during the read. The ferroelectric manner are described in Sec. III. Theoretical results are

memory field-effect transistor ( FEMFET) 8-’’ data storage presented and discussed in Sec. IV for a range of relevant

element offers a significant advantage over the ferroelectric device parameters. We focus on the basic (often nonintu-

capacitor approach: reading the data does not require the itive) device properties of this novel structure. In Sec. V,

memory to be reprogrammed. an example of technology optimization through the appli-

The ferroelectric memory field effect transistor consists cation of virtual prototyping is given. A testing methodol-

of a field-effect transistor (FET) whose gate dielectric is ogy, based on the model, is also presented and discussed.

comprised of a ferroelectric material, or a stack of dielec- Finally, the paper is summarized in Sec. VI.

trics with one ferroelectric layer.s-” The application of a

voltage pulse to the gate sets the direction of the polariza- II. THEORY

tion, and hence the value of the drain current of the tran-

sistor. The electrically programmable drain current can be A. Approach

used to define two logic states, much like other semicon- To develop the ferroelectric transistor model, we com-

ductor nonvolatile memories,12 such as the silicon-nitride- bine the switching physics of ferroelectric capacitors with

oxide-semiconductor (SNOS) nonvolatile memory transis- the silicon physics of metal-oxide-semiconductor (MOS)

tor.13 FETs. Brews developed a successful model of MOSFET

A comprehensive, quantitative model of ferroelectric transistor device operation14”* based on the charge-

transistor operation has not been previously developed, sheet16”” approximation. This approach assumes that the

and is now needed for several reasons. Understanding the inversion layer of the silicon can be approximated by a

dependence of the electrical properties on fabrication and conducting plane of zero thickness. In Brews’ model, there

5999 J. Appl. Phys.72(12),15 December1992 0021-8979/92/245999-12$04.00 @ 1992 American institute of Physics 5999

20 -

Ferroelectric 72

5 IO-

Id(t) g o-

v, s

B -10 -

drain / ~ s

B -20 -

N,

@ms I

Vb

ELECTRIC FIELD (kV/cm)

The gate dielectric stack consists of a switching ferroelectric sandwiched FIG. 2. The dipole switching contribution to the ferroelectric polariza-

between two nonswitching dielectric layers. tion is a function of the history of the electric field. The polarization must

lie on or within the saturated hysteresis loop.

lateral electric field, which is determined by the drain- directly applied to a p-channel device by making the stan-

source bias) and diffusion (governed by the carrier con- dard sign transformations.

centration, which is a function of the quasi-Fermi poten- The ferroelectric dielectric layer is assumed to have a

tial). Miller et al. is*19 have developed a model that dipole polarization that is a function of the history of the

accurately describes ferroelectric switching in capacitor electric field internal to the ferroelectric. The basic hyster-

structures by solving Maxwell’s first equation in the dielec- etic nature of the ferroelectric polarization is illustrated in

tric stack. We combine these two approaches to derive the Fig. 2, where the switched polarization (the linear contri-

equations governing the operation of the ferroelectric tran- bution to the polarization is omitted in this figure) is plot-

sistor. ted as a function of the ferroelectric field. Minor hysteresis

The transistor drain current is physically determined loops, along with the saturated loop, are shown. We note

by the quasi-Fermi potential at the surface of the silicon that the polarization must lie on or within the saturated

along the length of the channel. The quasi-Fermi potential polarization hysteresis loop.

is related to the electrostatic potential at the silicon surface,

which in turn is related to the applied gate voltage; it is a

function of the properties of the dielectric layers on top of C. Capacitor equations

the silicon, and of the silicon itself. Our approach now is to

first derive the equations governing the polarization, field, The silicon physics of a MOS device (capacitor or

and silicon surface potential as a function of gate voltage transistor) is independent of the dielectric structure that

for a ferroelectric capacitor on silicon. Using these results, exists above the surface of the silicon. The structure above

we then solve the basic transistor equations to obtain an the silicon simply determines the relationship between the

expression for the drain current. applied gate-to-substrate voltage Vgb and the silicon sur-

face potential 4, For most MOS devices, once this rela-

tionship is determined, the device characteristics can be

B. Definitions

expressed directly in terms of V86’The same is true for a

Before proceeding with the derivation of the relevant ferroelectric capacitor or transistor, except that the rela-

equations, we define the physical structure being modeled, tionship between Y86 and (p, depends on the electrical his-

along with the associated terminology. tory of the device. In this section, we derive the equations

The structure being modeled is shown in Fig. 1. (The relating the silicon surface potential to the gate-to-

definition of the physical parameters are given in the Ap- substrate voltage as a function of the properties of the

pendix.) A stack of three dielectrics exists between the dielectric layers on top of the silicon.

silicon and conductive gate. The central dielectric consists The electrostatic equations for the capacitor structure

of a switching ferroelectric dielectric layer, while the outer illustrated in Fig. 1 are derived starting with Maxwell’s

two layers are nonswitching dielectrics. The thickness and equation

linear dielectric constants for each layer are independent.

For this derivation we assume that there is no space charge

V-D =p, (1)

in the dielectric layers; free charge exists only on the gate where p is the free charge density and D, the displacement

and in the silicon. This capacitor structure, with the addi- vector, is given by D =e,,E+ P,,. (Vector quantities are

tion of the source and drain regions, comprise the FEM- signified by bold symbols, and are taken to be positive in

FET. We derive the equations for an n-channel device (p- the direction pointing downward from the top electrode, as

type substrate, n-type source and drain). The results can be shown in Fig. 1.) The total polarization is the sum of the

6000 J. Appl. Phys., Vol. 72, No. 12, 15 December 1992 S. L. Miller and P. J. McWhorter 6000

linear contribution and the contribution resulting from the lateral electric field resulting from the source-drain

switching dipoles. Thus bias. The other contribution is diffusion of carriers due to

the carrier concentration gradient. The relative contribu-

D=E,,E+E,,xE+P~=E~E+P~, (2)

tions of the two mechanisms to the total current may vary

where E= 1 +x is the linear dielectric constant for a given along the length of the channel. However, the total current

dielectric layer, and Pd, the contribution to the polarization itself (steady state) clearly must be independent of posi-

due to switching dipoles, is nonzero only in the ferroelec- tion, otherwise charge would build up in the channel. The

tric layer. Since Pd is a function of the electric field in the carrier density automatically adjusts to result in the same

ferroelectric layer (as well as the field history), it is written total current. This variation of carrier density with channel

as PJ E2). Using Eqs. ( 1) and (2) in conjunction with the position is physically explained in terms of an adjustment

definition E= -VI$, where 4 is the electrostatic potential, of the Fermi level. Specifically, the conventional Fermi

and recalling that the dielectric layers contain no trapped level is replaced by a quasi-Fermi level that varies along the

charge, we arrive at length of the channel, resulting in a total current that is

4

-pd(Ed

~04, (3)

constant.

Taking into account the mechanisms of drift and dif-

fusion, the current can be expressed in terms of the quasi-

where Fermi potential asl’

(4)

and the field is given by where the derivative is along the length of the channel, and

x is the distance from the source.

E2= - [as+pd(E2) 1 The goal now is to find an expression for the inversion

652 * charge density IV1 and the derivative of the quasi-Fermi

The silicon charge a, is given as a function of the silicon potential dd,/dx.

surface potential c$, by”

2. Inversion charge N,

a,(A) = -SGN(&) fi(e&lfiL~J [ (e-B4s+P#s- 1) The determination of the inversion charge layer is fa-

+ (nJNJ2(P+34s- 1) Y2, (6) cilitated by making a simple observation. The inversion

charge layer is typically a very thin sheet of charge located

where the bulk Debye length LB is given by at the silicon surface. Thus, the inversion layer is approx-

LJy= ( Eo$@qNJ 1’2. (7) imated by a sheet of charge. This approximation eliminates

the need to obtain complex solutions to the electrostatic

Equations (3), (5), and (6) together completely describe equations in the silicon.

the capacitor operation of the device illustrated in Fig. 1, The total silicon charge density is just the sum of the

when the function Pd(E2) is known. These equations are charge in the inversion layer -qN, and the charge in the

valid for accumulation, depletion, and inversion. The solu- depletion layer -qN,w, i.e.,

tion to this set of equations will be addressed later.

a,= -qNr-qN,w, (9)

D. Transistor equations: General formulation where the depletion width w is given by

Having derived the equations relating the silicon sur- w = JzLB( pep,, 1’2. (10)

face potential to the applied voltage, we now proceed to

derive the transistor equations. This derivation follows Eliminating w from Eqs. (9) and (lo), one obtains the

closely that given by Brewst4*t5 for the nonferroelectric desired result

MOSFET. Since the polarization is related to the silicon c stack es

surface potential and charge [see Eq. (3)], Brews’ equa- q&=7 -4~w2-~ (11)

tions are rewritten to properly take into account the effects ( stack

are derived below for n-channel transistors; application to

0= & 6J’%&~stack). (12)

p-channel devices can be made with the standard sign

changes.

3. Quasi-Fermi potential &,,

1. Basic current equation

A suitable expression for the quasi-Fermi potential is

When the surface potential is sufficiently large to form needed to evaluate Eq. (8) for the current. The equation

an inversion region at the surface of the silicon, an electri- relating the silicon charge and surface potential can be

cal channel connecting the source and drain is formed. The expressed in terms of the quasi-Fermi potential by”

current that flows through this channel consists of two

contributions, each caused by fundamentally different as= -OF [ p$+ (~)‘@L l)&%+bp] 1’2. (13)

mechanisms. One contribution is drift of the carriers due to

6001 J. Appt. Phys., Vol. 72, No. 12, 15 December 1992 S. L. Miller and P. J. McWhorter 6001

Equation ( 13) is strictly valid only for the range of surface This expression may be simplified considerably by making

potentials resulting in depletion and strong inversion. The the following observations. The first two terms of Eq. ( 17)

complete expression that is also valid for accumulation is are simply PqN/Cstack Thus the third term of Eq. (17)

not necessary for the analysis of transistor operation, since contributes significantly to the current only when N1 is

negligible current flows in accumulation. Equation ( 13) is small, i.e., near pinch-off. Consequently, we replace the

inverted to obtain the quasi-Fermi potential third term of Eq. (17) by its value near pinch-off. Using

Eq. ( 15) to do this, IQ. ( 17) becomes

( -fld~c,tack)2-fl#s

* (14)

Idx=

The 1 in the denominator can typically be dropped since

exp(&,)>l when not in accumulation.

It can be inferred from Eq. ( 14) that there is a value of (18)

@$, that cannot be exceeded. As the surface potential &$,

increases, the numerator in the log term approaches zero, The current is obtained by integrating the above ex-

and hence /3+F,, diverges to positive infinity. The value of 4, pression along the length of the channel, from the source to

at which $Fn diverges is called &, and is given by the drain. We designate the effective channel length by L,

and the silicon surface potential at the source and drain by

-&(&at>~&ack= (Pdsat)1’2* (15)

+d) and 4sL, respectively. Since the current is constant

In I$. ( 15) we indicate the explicit dependence of the along the channel, the left-hand side of Eq. ( 18) becomes

charge a, on the surface potential. For fixed gate and IL. All terms on the right-hand side of Eq. (18) can be

source voltages, increasing the drain voltage will increase integrated directly except those that contain a,. We recall

the silicon surface potential at the drain. This potential that o, is a function of @, and is given by [see Eq. (3)]

asymptotically approaches &; this is the condition that

results in pinch-off of the channel. The term pinch-off is

used because at this point the inversion layer vanishes [see -‘;““)

stack

=&y-&b,+P,(E2)

2 . (19)

Eqs. (11) and (15)], and the channel is “pinched-off.” The

value of the drain voltage V,,, that results in saturation of If the drain-to-source bias V,, is kept sufficiently low (typ-

the surface potential at the drain (pinch-off) is defined by ically < -0.5 V), the FE polarization will not vary signif-

V,, = I$,,~ - I&,, where & is the surface potential at the icantly along the length of the channel, and Pd( E2) can be

source end of the channel. treated as a constant for the purpose of integration. Inte-

Finally, a useful expression for d/3 $F,,/dx is obtained. grating Eq. ( 18) using Eq. ( 19), we obtain

This is done by taking the derivative of Eq. ( 14). The

result is

I= -$‘+ [ (1+&++z f%E,))(@$s~-&)

l- [2&d(~~stack)2] (~~~s@~s)

&Fn=( 1+ (-&d~cstack)

2

+‘#%

been defined [see Eqs. ( 11) and ( 16)]. These quantities

+a[. wsLY2- pAilY21 *

1 (20)

cannot be evaluated directly to obtain the current. How- determined using the boundary conditions15

ever, if Eq. (8) is integrated from the source to the drain,

the current can be determined. +F&ource) =‘#‘F+ vbs (21)

and

4. Determining the current #Fn(drain)=&+ VbYt- vds. (22)

Now that the inversion charge N1 and the derivative of

The potentials #a and & are then given [combining Eq.

the quasi-Fermi potential d&$&dx have been determined,

( 14) with Eqs. (21) and (22)] by solving the transcenden-

we proceed to evaluate Eq. (8) to obtain the current. Sub-

tal equations

stituting Eqs. ( 11) and ( 16) into Eq. (8)) we obtain

- w@stack -@s l/2

I=

p2 c,,, - ‘(“‘)

+

a(1 - [2~q/(~~,,,,k)21

[ ( -&duCstack)

(%J-~~~~~s)~

+ (8h)1’21

-fvK+ (23)

(17) and

6002 J. Appl. Phys., Vol. 72, No. 12, 15 December 1992 S. L. Miller and P. J. McWhorter 6002

Wz TABLE I. FEMFET deviceparameters.

Pv.b+Gpd(EZ)

Parameter Value Unit

p* 1.0 &/cm2

(24) p/p, 0.8

EC 100 kV/cm

The ferroelectric dipole polarization in Eqs. (20), (23), 4 300 A

and (24) is evaluated at the source end of the channel. EI 3.9

Brews’ original raUlt iS recovered by Setting Pd=O. 4 1000 A

4 10

In order to solve Eqs. (20), (23 ), and (24) for the 10 .A

4

drain current, explicit definitions of the dipole polarization 63

Pd(E2) must be given. We discuss this in the following NC 3;ik cmm3

section, after first making a few comments regarding the P 0.08 m’/(V s)

treatment of interfacial charge. W 8 w

L 4 Pm

We note that the derivation presented here is in a form -1.15 V

4,

that allows the quantitative treatment of interface states at vd 0.1 V

the silicon surface, the occupancy of which is a function of V* 0 V

the difference between the surface potential and quasi- vb 0 V

Fermi potential. The inclusion of interfacial charge results

in slight modifications to Eqs. (3) and (5); these changes

are then carried through the remainder of the analysis.

Care must be taken when integrating the equation analo- The equations have thus been given that govern the

gous to Fq. ( 17) since both the surface potential and quasi- ferroelectric transistor drain current as a function of the

Fermi potential are functions of position along the channel applied voltage history, geometry, and material properties.

length. The detailed treatment of interface states is omitted In the following section we discuss some issues associated

with the numerical evaluation of the above equations.

in the present paper.

E. Dipole polarization Since the polarization (and hence the surface potential

The value of the dipole polarization depends on the and current) depend on the history of the electric field in

previous history of the ferroelectric electric field. Thus the the ferroelectric, the drain current is calculated as a func-

polarization is determined by integrating dP,(E,)/dE, tion of the applied gate voltage by integrating the polariza-

from some specified initial condition. Since the form of tion from known initial conditions. The procedure to ac-

dPd(E)/dE (we drop the subscript 2 for notational conve- complish this is outlined below.

nience) has been extensively discussed previously for arbi- A. initial condition computations

trary field histories, 18V19

the results are simply stated here.

The saturated polarization hysteresis loop is defined by ( 1) Define the constants required for the computa-

tions. These include P,, P, E. T, N,, p, W, L, d,, d2, d3, el,

P&(E)=P&.anh[ (E-E,)/2S], (25) E2, E3, v, vb, and v,.

where

the loop. The negative-going branch of the loop is given by

P;,(E) = -P&( -E). (27)

The derivative of the polarization, whether or not the

polarization lies on or within the saturated hysteresis loop,

is given by

(28)

where

0

I’=l-tanh[ (E)1’2], (29) time

and c= + 1 when dE/dt > 0 and ,$= - 1 when dE/dt < 0. FIG. 3. The time-dependent voltage Vg applied to the transistor.

6003 J. Appl. Phys., Vol. 72, No. 12, 15 December 1992 S. L. Miller and P. J. McWhotter 6003

(2) Define the initial conditions, i.e., the initial gate solve Eqs. (3), (5), (6), and (28) must be developed. The

voltage Ve and initial polarization Pa Using these values, approach we pursue is to compute the mth value of the

the silicon surface potential +S and silicon charge density a, relevant quantities, and numerically integrate. In order to

are calculated by simultaneously solving Eqs. (3) and (6). avoid confusion, we drop the subscript 2 on the ferroelec-

The initial value of the ferroelectric field is then calculated tric electric field. We now introduce a new subscript, m,

using Eq. (5). The derivative dP,(E)/dE is also evaluated which signifies that the given quantity is evaluated at the

[using Eq. (28)]. Note that the initial choice of Ve and Pd mth integration increment.

must satisfy the physical requirement that the polarization First, select an mth value for 4, Calculate the mth

lie on or within the saturated hysteresis loop. value of a,( 4,) from Eq. (6). Write the dipole polarization

(3) Finally, the initial current is computed. If 4, < +p as

then the channel is off and the drain current is effectively

zero. If #$> 4p then the current is computed as follows.

Calculate fl+d) and p+SL using Eqs. (23) and (24). Then

substitute these values into Eq. (20) to give the drain cur- PcAEm)

=P~&,+I) + (-%--Em-,) -& [P&3 11~~~~

,

rent. The value of Pd used to evaluate Eqs. (23), (24)) and (30)

(20) is that used in step 2 above.

B. Numerical integration

where the vertical bar signifies that the derivative is eval-

To perform the integration from the initial conditions uated at the field E,,+ i. Using Eq. (5) to eliminate E,, E~J.

to a new set of conditions, a technique to simultaneously (30) becomes

(31)

Using Eq. (3 1) in conjunction with Eq. (28), compute the maximum and minimum field for each curve are different

mth value of the dipole polarization. Next, calculate Y86 in magnitude due to the non-zero flatband voltage.

from Eq. (3). Using the above results, solve Eqs. (23) and The ferroelectric polarization Pd is shown as a function

(24) for the silicon surface potential at the source and of the applied gate voltage Vg in Fig. 5 for several values of

drain end of the channel. Finally, evaluate Eq. (20) to PF Note that at Vg=O, the polarization is less than the

obtain the mth value of the drain current. remanent polarization P, This nonintuitive result occurs

Though the numerical implementation of the equa- because the ferroelectric field reverses direction when the

tions to obtain the drain current as a function of an arbi- gate voltage is reduced from a saturating value back to 0 V.

trary time-dependent gate voltage may appear somewhat This field-reversal results in the additional polarization re-

complex, it is actually quite straightforward. duction observed in Fig. 5. It also results in the fact that

the polarization at zero gate bias is relatively insensitive to

IV. MODEL RESULTS the spontaneous polarization when it is increased beyond

The behavior of a FEMFET device is now investigated -0.5 ,uC/cm2. The nature of the electrostatic boundary

using the equations derived above. The parameters used to conditions that must be satisfied at the dielectric layer in-

perform the analyses are given in Table I, unless otherwise terfaces is the physical origin of this behavior. For com-

specified. The initial conditions are ?‘a= Vfb and Pd=O. pleteness, we show the dependence of the ferroelectric field

The applied voltage history is shown in Fig. 3. To maintain on the applied gate voltage in Fig. 6. Note that the direc-

clarity in the following figures, only the quantities associ- tion of the path taken around the hysteresis loop is opposite

ated with the portion of the voltage history indicated by to that of the polarization shown in Figs. 4 and 5. We also

the heavy line in Fig. 3 are shown. point out that the changing depletion layer capacitance of

For reference, we first show the “standard” polariza- the silicon is the origin of the “kink” that disrupts the

tion hysteresis loop, i.e., the contribution to the ferroelec- symmetry in Figs. 5 and 6.

tric polarization due to the switching dipoles as a function The electric field in the non-switching layers (or the

of the ferroelectric field. This is plotted in Fig. 4 for several silicon) can become quite large if the ratio of the dielectric

values of P, while maintaining a constant ratio P/P, The constant of the ferroelectric layer to that of the nonswitch-

arrows indicate the direction of the hysteresis path in this ing dielectric layers (or the silicon) is not close to unity.

and the following figures. Though the amplitude of the We illustrate this by plotting the field in the bottom non-

applied signal is the same for all three cases, the maximum switching layer as a function of the gate voltage in Fig. 7.

ferroelectric field decreases with increasing P,. In fact, for The rate at which the field increases with voltage scales

P,= 1.0 &/cm2, the hysteresis loop is unsaturated. The with P, during switching, and is independent of P, after

6004 J. Appl. Phys., Vol. 72, No. 12, 15 D&ember 1992 S. L. Miller and P. J. McWhorter 6004

0.8

0.4

0.2

z

g 0

V

N

w -0.2

-0.8l’ ’ s ” “I ”

-500 -250 0 250 500 -12 -8 -4 0 4 8 12

E, (kV/cm) vg(V)

FIG. 4. The ferroelectric polarization P,+as a function of the ferroelectric FIG. 6. The direction of the hysteresis of the ferroelectric field vs the gate

field is hysteretic due to the applied signal shown in Fig. 3. voltage is oppositethat of the polarization, resulting in field reversal when

the gate bias is reduced to 0.

ing switching is a direct consequence of the boundary con- and surface potential. The silicon surface potential (with

ditions associated with this stacked dielectric structure. no drain bias) is shown in Fig. 8 as a function of gate

The polarization of the FE layer reduces the electric field voltage for several values of Pr (Note that increasing P, by

internal to the FE film, and hence increases the field in the a factor of four has only a minor impact on the gate voltage

dielectric layers external to the FE film. Spontaneous po- at which the transition from accumulation to inversion

larization values that are not very small can result in fields occurs.) The occurrence of ferroelectric switching not only

exterior to the ferroelectric that can easily become compa- results in hysteresis of the d,( Vg) curve, but also results in

rable to the breakdown field for such films, and can cer- a change in shape relative to that of a non-switching de-

tainly result in parasitic effects such as charge injection or vice. In particular, when the gate voltage passes through

transport through the films. the range where switching occurs (see Fig. 5), the slope

Since the transistor drain current is a function of the dt&/dV, increases due to the changing polarization. These

silicon surface potential, the I-V characteristic of the tran- results significantly impact our intuition regarding such

sistor depends on the relationship between the gate voltage concepts as threshold voltage.

0.8

3

0.4 2

E 1

Ni

0 O Y

2

is O

ci?

-0.4 w” -1

-2

-0.8

, * 1 * * * * ” a ’ 1 ’ ” I”” a ‘3

-12 -8 -4 0 4 8 12 -3

vg09 -12 -8 -4

vgW)

0 4 8 12

k’s demonstrates the reverse switching due to field reversal in the ferro- FIG. 7. The field in the non-switching dielectric layers is amplified by the

electric. The “kink” in the curves disrupting the symmetry is due to the switching polarization of the ferroelectric layer. Depending on the geom-

changing capacitance of the silicon. etry, it can easily reach values comparable to the breakdown field.

6005 J. Appl. Phys., Vol. 72, No. 12, 15 December 1992 S. L. Miller and P. J. McWhorter 6005

0.25

0.8

-12 -8 -4 0 4 8 12

vg W) 120 ,

hysteretic, resulting in distorted transistor Z-V characteristics exhibiting 80 -

hysteresis.

can be defined as the gate voltage that results in the silicon

surface potential at the source being equal to 2+P The

subthreshold region corresponds to gate biases resulting in ‘fl Ps = 0.0 yC/cm’

+F < +S< 2#F The #,( Vg) hysteresis curves in Fig. 8 are

those for saturating (in the sense that the polarization sat- -2 0 2 4 6 a 10 12

urates) or nearly saturating gate biases. Minor hysteresis vg (V)

loops can take any path within the corresponding saturated

loop. Consequently, the notion of threshold voltage is com- FIG. 9. Transistor Z-V curves exhibit hysteresis due to ferroelectric

pletely ambiguous; the gate voltage that corresponds to switching. The same data are plotted in both (a) and (b); the only

$,=21$~ depends on the voltage history. Moreover, all as- difference is current scale. The apparent “threshold” voltage shift is gov-

pects of the transistor I-V curve (e.g., subthreshold swing erned by EO while P, governs the current offset at large voltages.

and k’) depend on the voltage history due to the fact that

the ferroelectric polarization depends on the internal field

history. of P,. The boundary conditions are such that the onset of

Transistor I-V curves for several values of P, are strong inversion corresponds to a relatively small value of

shown in Fig. 9; Fig. 9(b) is identical to 9(a) except for ferroelectric polarization. This polarization is relatively in-

the scale on which the current is plotted. The amplitude of dependent of P, (as is clearly seen in Fig. 5) as long as P,

the gate bias is sufficient to saturate the polarization (see is larger than some very small critical value (which de-

Fig. 4). The “subthreshold slopes” of the switching tran- pends on the geometry of the device). The “apparent”

sistors are greater than that for the nonswitching transistor threshold voltage shift, rather than being dependent on the

( PS=O); this occurs because of the greater sensitivity of the spontaneous polarization, is directly proportional to the co-

surface potential to the gate voltage during the switching ercive field E,

process. In addition, the maximum transistor current is The dependence of the flatband (or equivalently,

greater due to the larger fields resulting from the switched “threshold voltage”) shift on E, is clearly illustrated by the

dipoles (see the discussion associated with Fig. 7). C-V curves in Fig. 10. Recall that the C-V curves only

Figure 9(b) highlights some additional striking prop- sample the range in surface potential corresponding to the

erties of FEMFET hysteresis. The apparent slope of the formation of the depletion layer, i.e., - 0 < 4, < - 24,+ This

“on” I-V curves has two components; the larger slope re- corresponds to a very limited range of the FE polarization

sults when dipole switching is still occurring, while the Pd, as can be inferred from Figs. 8 and 5. As noted earlier,

smaller slope results when switching is complete. Note that the gate biases corresponding to this range of polarization

for voltages large enough for switching to be complete, the are relatively independent of the spontaneous polarization

slope is the same as that of a nonswitching transistor, and P, To summarize, the apparent flatband shift of the C-V

the actual current is proportional to the spontaneous po- hysteresis curves is proportional to the coercive field. The

larization P,. In addition, the “apparent” threshold voltage shape of the C-V hysteresis curves is governed by the de-

shift associated with the hysteresis is relatively independent pendence of the FE polarization on gate voltage for a range

6006 J. Appl. Phys., Vol. 72, No. 12, 15 December 1992 S. L. Miller and P. J. McWhorter 6006

Ps = 1 .o j.lc/cm*

decreases with thickness

2

0 0.8

3

0.7

0.6

0 0.5 1 1.5

d2 W-d

vgw FIG. 11. Following a positive voltage pulse, the transistor drain current

is significant only for a finite range of ferroelectric film thicknesses. This

virtual prototyping approach can be used to rapidly optimize a number of

FIG. 10. Capacitor C-Y curves exhibit hysteresis; the flatband voltage design and fabrication parameters.

shift is proportional to E, The shape of the C-Y curves results from the

ferroelectric polarization sweeping through only a small range in polar-

ization.

in polarization where this dependence is a very weak func- technology optimization, as well as reduce the number of

tion of the spontaneous polarization.

design iterations.

We illustrate a virtual prototyping application using

V. DISCUSSION the above FEMFET model. A fabrication parameter that

The above analyses reveal a number of unique and impacts the electrical performance of a FEMFET memory

nonintuitive aspects of the behavior of FEMFET devices device is the thickness of the ferroelectric layer. In our

that are not observed with either fixed-threshold FET de- virtual prototyping example, we determine the optimum

vices or other types of conventional silicon-based nonvol- ferroelectric layer thickness to maximize the transistor

atile memories. It is not possible to measure a “conven- drain current after a programming voltage pulse to the

tional” C&-threshold transistor I-V curve. The act of gate. The physical parameters associated with the device of

performing the measurement changes the ferroelectric po- interest are those listed in Table I. For the sake of illustra-

larization, and the resulting curve depends on the previous tion, we assume that the polarization Pd is zero immedi-

electrical history. The concept of a well-defined threshold ately before the programming voltage pulse. A positive 10

voltage does not exist; the gate voltage resulting in #s=2r$F V pulse is then applied to the gate, after which the gate-

depends on the voltage path taken due to the changing to-substrate voltage is maintained at 0 V. Immediately af-

ferroelectric polarization. In addition, the “subthreshold” ter the pulse, the polarization will be different from zero,

portion of the I-Y curve is always steeper than that of a resulting in a change in the transistor drain current. The

similar nonswitching FET. Specifically, as the gate voltage desired information is the value of the drain current (im-

is increased (decreased), the transistor turns on (off) mediately after the pulse) as a function of the ferroelectric

faster due to the ferroelectric switching; this is why the 1-V layer thickness.

hysteresis occurs in the counter-clockwise direction (see The conventional way to determine this information is

Fig. 9). to develop the appropriate fabrication processes, fabricate

These types of behavior present some interesting prob- devices with different ferroelectric thicknesses, and then

lems regarding FEMFET technology development and de- perform electrical measurements. Instead, we perform vir-

vice characterization. Since much of our standard intuition tual prototyping to determine the same information within

and characterization approaches are not applicable to minutes.

FEMFET devices, we show how the model developed The results of the virtual prototyping analysis are

above can facilitate the design and electrical characteriza- shown in Fig. 11, where the drain current at zero gate bias

tion of these devices. is plotted as a function of the ferroelectric film thickness.

Note that the transistor is on after the pulse for only a

A. Virtual prototyping application

limited range of thicknesses. For large thicknesses, the field

Virtual prototyping is the application of predictive resulting from the applied voltage is not sufficient to switch

models to answer questions that would normally be ad- the polarization, and the transistor remains off (as it was

dressed by designing, fabricating, and testing devices (i.e., with zero polarization). For slightly thinner films, the field

physical prototyping ). Virtual prototyping can signifi- is sufficient to switch the polarization. However, when the

6007 J. Appl. Phys., Vol. 72, No. 12, 15 December 1992 S. L. Miller and P. J. McWhorter 6007

gate voltage is reduced to zero after the pulse, reverse

switching of the dipoles occurs due to the field reversal in

the ferroelectric film (see Fig. 5 and the associated discus-

sion). Consequently, the transistor current after the pulse

is reduced to a value that is less than it was during the

pulse. For very thin films, the current again drops to zero.

This is because the impact of the ferroelectric polarization

on the silicon surface potential is roughly proportional to

the film thickness [see Eq. (3)]. We note that after negative

gate pulses, the transistor is turned off.

Though we have considered a single application of vir-

tual prototyping here, it is clear that the FEMFET device

model may be used to rapidly optimize a number of design

and fabrication parameters associated with the FEMFET 0.2 0.3

voltage, bit line capacitance, and FE film properties such as

E. P,, P, and E. FIG. 12. The computed current vs polarization curve can be used to infer

the ferroelcctric polarization from drain current measurements at zero

8. Testing methodology gate bias. The polarization is thus not disturbed during the measurement

process.

There are several physical properties of the ferroelec-

tric film that are relevant to the successful design, fabrica-

tion, and delivery of FEMFET devices. These include the

polarization versus field hysteresis loop (impacts design device parameters such as channel doping, channel length

parameters and material selection), the relaxation of the and width, film thicknesses, and dielectric constants must

polarization with time (determines data retention), and be known or determined using other standard techniques.

the change in these properties with repeated reprogram- Data retention is governed by the rate at which the

ming (endurance). The polarization vs field hysteresis loop polarization relaxes with time after the programming

of FE capacitors is typically obtained using a Sawyer- pulse. To determine the polarization as a function of time

Tower circuit;” unfortunately, the standard analysis typi- after a positive gate pulse, the drain current at zero gate

cally performed is not valid due to the highly nonlinear bias is measured as a function of time. Note that this mea-

relationship between the applied voltage and ferroelectric surement process does not disturb the polarization pro-

electric field. Data retention in conventional silicon-based vided the drain bias is kept low. To determine the time

nonvolatile memories is typically characterized by measur- dependence of the polarization, the drain current as a func-

ing the change in threshold voltage with time; this cannot tion of the polarization (and at zero gate bias), is com-

be done for FEMFET devices since changing the gate volt- puted using the previously determined physical parame-

age changes the “threshold voltage.” Characterization of ters. Figure 12 illustrates the results of such a computation

endurance simply involves measuring the above properties, for the parameters listed in Table I. Using Fig. 12, a given

for example, as a function of accumulated reprogramming current value is mapped directly to the ferroelectric film

cycles. Clearly, a new approach must be taken to electri- polarization. We note that this technique permits polariza-

cally characterize FEMFET devices. tion measurements for a limited range of values due to the

The development of a testing methodology must be fact that the transistor must have a measurable drain cur-

performed with extreme care due to the unique properties rent at zero gate bias. To measure the decay of polarization

of the FEMFET device. It requires a quantitative under- having a different range, one may perform the same mea-

standing of the relationship between measured quantities surements on an identical n-channel transistor having a

(such as currents and voltages) and basic device parame- threshold-adjust implant, or test a p-channel transistor fol-

ters in order to electrically characterize the relevant phys- lowing a negative gate pulse.

ical properties. We discuss below how the FEMFET device Using the above approach, the basic ferroelectric pa-

model is used to develop a relevant testing methodology. rameters may be determined after various numbers of ac-

The first step is to determine the basic ferroelectric cumulated reprogramming cycles. In this way, the endur-

hysteresis loop parameters P,, P, and EC We recall from ance of the ferroelectric film is characterized.

Fig. 9(b) that these parameters are directly related to the The testing methodology described above may be di-

saturated I-V hysteresis loop. The model parameters are rectly extended using the FEMFET device model to de-

determined by adjusting them so that the model 1-V curve velop additional characterization techniques.

matches the experimental I-V data; EC is adjusted to match

the apparent “threshold voltage” shift, P, is adjusted to

give the correct parallel offset for the saturated portion of VI. SUMMARY

the 1-V curve, the dielectric constant e2 is adjusted to give

the correct saturated slope, and P, is adjusted to give the The device properties of a ferroelectric memory field

correct curvature during switching. To do this, the other effect transistor (FEMFET) have been theoretically inves-

6008 J. Appl. Phys., Vol. 72, No. 12, 15 December 1992 S. L. Miller and P. J. McWhorter 6008

tigated. This was done by solving Maxwell’s first equation strates two characteristic slopes. At high voltages when

for the stacked dielectric structure in conjunction with the switching is complete, the slope is governed by the same

charge-sheet approximation to the silicon inversion layer. parameters as a normal nonswitching FET (but the cur-

The resulting equations allow the determination of the rent itself is higher by an amount proportional to the spon-

transistor drain current, ferroelectric polarization, and di- taneous polarization). At lower voltages the slope is larger,

electric layer fields as functions of arbitrary time- and is impacted by the shape of the ferroelectric P-E hys-

dependent gate voltages. It was found that the polarization teresis curve. Having two different slopes renders the nor-

at zero gate bias (which is relevant to device applications) mal concept of k’ somewhat ambiguous. Hence, we have

is relatively insensitive to the spontaneous polarization due quantitatively shown that most aspects of FEMFET device

to reverse switching, a result that can significantly impact operation differ significantly from those of standard MOS-

the development of the FEMFET technology. This reverse FET operation.

switching is caused by field reversal in the ferroelectric Because of these differences, the FEMFET device

layer; boundary conditions derived from Maxwell’s first model was applied to develop a viable testing methodology

equation for a ferroelectric film on silicon require this to that allows the experimental determination of relevant

occur. It was quantitatively demonstrated that the fields in physical properties of the ferroelectric film. Use of the

nonswitching films comprising the dielectric stack can eas- model was essential because quantitative relationships be-

ily become comparable to the breakdown field for such tween measured quantities and physical device properties

films, another result that impacts FEMFET technology are required.

development. Depending on the properties of the film, par- The application of the FEMFET device model to per-

asitic effects such as charge injection could easily result. form technology optimization was illustrated with an ex-

The FEMFET I-V curves were extensively investi- ample of virtual prototyping. The drain current as a func-

gated. The I-V hysteresis occurs in a counter-clockwise tion of the ferroelectric film thickness was computed for a

direction (this is opposite to that of other silicon-based specific programming pulse. It was found that the transis-

nonvolatile memories such as floating gate or SNOS) due tor is in a high current state after the pulse for only a

to polarization switching. The well-defined features nor- narrow range of thicknesses, allowing the optimum choice

mally associated with fixed-threshold FET I-V curves are of ferroelectric layer thickness without costly fabrication

dependent on the gate voltage history, and are thus ambig- iterations.

uous. For example, the concept of a well-defined threshold

voltage is no longer relevant since the gate voltage at which ACKNOWLEDGMENTS

+,=24F is history dependent. Also, the “subthreshold

slope” is steeper than that of an equivalent fixed-threshold We thank D. Lampe at Westinghouse Electric Corpo-

device due to dipole switching. The coercive field governs ration for stimulating discussions. We are also grateful to

the apparent threshold voltage shift of saturated I-V B. Filter and T. Meisenheimer for critically reviewing this

curves. The spontaneous polarization plays only a minor manuscript.

role in determining the apparent threshold voltage shift This work performed at Sandia National Laboratories

(provided it is larger than some critical value), contrary to supported by the U.S. Department of Energy under Con-

normal intuition and contrary to the way such data is com- tract No. DE-AC04-76DPOO789.

monly interpreted. In the triode region of operation (often

referred to as the linear region), the I-V curve demon- APPENDIX

The physical parameter and symbol definitions are

given below, along with their associated MKS units.

Silicon di, d,, d3, = dielectric layer thicknesses (m) .

Surface el, Q, e3, =linear dielectric constant (unitless).

tc l ,=linear dielectric constant of the silicon (unitless).

eo=permittivity of free space -8.85X 10-l’ (F/m).

P,=remanent polarization [C/m’], i.e., the ferroelec-

tric dipole polarization occurring at zero electric field on a

saturated hysteresis loop.

P,=spontaneous polarization [C/m*], i.e., the maxi-

E

Fn mum ferroelectric dipole polarization occurring on a satu-

rated hysteresis loop.

&=coercive field (V/m), i.e., the electric field at

which the ferroelectric dipole polarization is zero on a sat-

urated hysteresis loop.

V,=applied transistor or capacitor gate voltage (V).

V,= applied transistor drain voltage (V).

V,=applied transistor source voltage (V).

FIG. 13. A band diagram illustrating the definitions of the relevant po- Vb= applied transistor or capacitor substrate voltage

tentials in the silicon. 09.

6009 J. Appl. Phys., Vol. 72, No. 12, 15 December 1992 S. L. Miller and P. J. McWhorter 6009

v,,= v,- v, 4~=[Ei(~0)-E&q=P-‘log(N,/n~)=Fermi poten-

V,,= - ( V,- V,). The sign of V,, is chosen so that V,, tial (V).

is a positive number when the source/substrate diode is #F,, = [Ei( 00 ) - EFn]/q = quasi-Fermi potential (V).

reversed biased. n=n,exp[(E,,-Ei)/k~=n,exp[P(~-~Fn)]=carrier

vgs= vg- v, concentration ( mm3).

Vgb= Va- V, = I&+ V,, In order to account for con-

tributions to the flatband voltage not explicitly addressed

in the following derivation, such as the gate-to-substrate ‘J. Moll and Y. Tarui, IEEE Trans. Electron Devices ED-IO, 338

work function difference 4, or fixed trapped dielectric (1963).

charge, VBbshould be replaced in the equations that follow *R. Zuleeg and H. H. Wieder, Solid-State Electron. 9, 657 ( 1966).

‘P. M. Heyman and G. H. Heilmeier, Proc. IEEE 54, 842 (1966).

with Vgb- Vu, where Vu, is the additional contribution to ‘J. C. Crawford and F. L. English, IEEE Trans. Electron Devices ED-

the flatband voltage. For example, Vn, = 4,, when no other 16, 525 (1969).

charges are present, and Vgb+ Vgb- Vfb= Vgb-~ms ‘C. A. Araujo, L. D. McMillan, B. M. Melnick, J. D. Cuchiaro, and J.

W=electrical channel width (m). F. Scott, Ferroelectrics 104, 241 ( 1990).

6J. F. Scott and C. A. Araujo, Science 246, 1400 (1989); in Molecular

L = electrical channel length (m). Electronics, edited by M. Borisson (World Scientific, Singapore, 1986),

,u=channel mobility [m2/(V s)]. pp. 206-214.

ni=intrinsic carrier concentration ( mm3). ‘J. T. Evans and R. Womack, IEEE J. Solid-State Circuits 23, 1171

N, = substrate doping concentration (assumed to be (1988).

8S. Y. Wu, IEEE Trans. Electron Devices ED-21, 499 (1974).

uniform) [mm3]. 9K. Sugibuchi, Y. Kurogi, and N. Endo, J. Appl. Phys. 46,2877 (1975).

n =free carrier concentration ( me3). ‘OS. Y. Wu, Ferroelectrics 11, 379 (1976).

q=charge unit - 1.6~ lo-i9 (C). ‘ID. R. Lampe, D. A. Adams, S. Sinharoy, and H. Buhay, Presented at

T= absolute temperature (K) . the 4th International Symposium on Integrated Ferroelectrics, Mon-

terey CA, 1992.

k=Boltzmann’s constant - 1.38~ 1O-123(J/K). “Y. Nishi and H. Iizuka, in Applied Solid State Science, edited by D.

8=q/(kT) (V-l). Kahng (Academic, New York, 1981), Suppl. 2A, pp. 121-251.

Figure 13 contains a band diagram illustrating the fol- “S. L. Miller, P. J. McWhorter, T. A. Dellin, and G. T. Zimmerman, J.

Appl. Phys. 67, 7115 (1990); S. L. Miller and P. J. McWhorter, ibid.

lowing definitions: 70, 4569 (1991).

Ei= intrinsic level (J) . 14J. R. Brews, Solid-State Electron. 21, 345 (1977).

EF= Fermi level (J) . I5 J . R . Brews, in Applied Solid State Science, edited by D. Kahng (Aca-

EFn=electron quasi-Fermi level (J). In a capacitor, demic, New York, 1981), Suppl. 2A, pp. 11-120.

16J. A. Guerst, Solid-State Electron. 9, 129 ( 1966).

this is typically equal to the Fermi level. “H. W. Loeb, R. Andrew, and W. Love, Electron. Lett. 4, 352 ( 1968).

N,= inversion layer charge density ( mW2). “S. L. Miller, R. D. Nasby, J. R. Schwank, M. S. Rodgers, and P. V.

a,= charge density in the silicon ( C/m2). Dressendorfer, J. Appl. Phys. 68, 6463 ( 1990).

4 = [Ei( CO) - Ei]/q = band bending (function of posi- 19S. L. Miller, J. R. Schwank, R. D. Nasby, and M. S. Rodgers, J. Appl.

Phys. 70, 2849 ( 1991).

tion) (V). ‘OS. M. Sze, Physics of Semiconductor Devices (Wiley, New York, 1981),

4S= [Ei( co ) - Ei]/q = band bending (at the silicon sur- p. 368.

face) (V). 2’C. B. Sawyer and C. H. Tower, Phys. Rev. 35, 269 (1930).

6010 J. Appl. Phys., Vol. 72, No. 12, 15 December 1992 S. L. Miller and P. J. McWhorter 6010

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