Code No: 114DT R13

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

B.Tech II Year II Semester Examinations, October/November - 2016
SWITCHING THEORY AND LOGIC DESIGN
(Electrical and Electronics Engineering)
Time: 3 Hours Max. Marks: 75

Note: This question paper contains two parts A and B.

Part A is compulsory which carries 25 marks. Answer all questions in Part A.
Part B consists of 5 Units. Answer any one full question from each unit.
Each question carries 10 marks and may have a, b, c as sub questions.

PART - A (25 Marks)

1.a) Convert the following to the required form.

i) (101001.001)2= ( )10 ii) (1264)8 = ( )10 [2]
b) Show that the dual of the Exclusive – OR is equal to its complement. [3]
c) Simplify the Boolean function F(X,Y,Z)=∑m(3,4,6,7) using K-map. [2]
d) What is a Decoder? Construct a 4×16 decoder with two 3×8 Decoders. [3]
e) Compare Latch and Flip-Flop. [2]
f) Define Level trigger, Edge trigger, Clock skew. [3]
g) Define State Table and State Diagram. [2]
h) Explain about Ring counter with a neat diagram. [3]
i) Compare Mealy and Moore machines. [2]
j) Construct an ASM chart for the SR Flip-flop. [3]

PART - B (50 Marks)

2.a) Encode the message bits (1110)2 into 7-bit even parity hamming code.
b) Perform the following arithmetic using 2’s complement method.
i) 101111-100110 ii) 111001-011010 [5+5]
OR
3.a) Convert the following expression into sum of products and product of sums.
X'+X(X+Y')(Y+Z')
b) Implement the following Boolean function with NAND gates only.
F(X, Y, Z) = ∑m (1, 2, 3, 4, 5, 7) [5+5]

4. Simplify the following function using K-Map method

F(A,B,C,D)= Σ(0,1,2,3,4,6,9,10)+d(7,11,12,13,15) [10]
OR
5. Design a code converter that converts a decimal digit from the 8,4,-2,-1 code to
BCD. [10]

6. What is race around condition? How does it get eliminated in a Master–slave JK

flip-flop? [10]
OR
7. Obtain the characteristic equations of JK, SR, D and T flip-flops. Also explain
excitation tables of all these flip-flops. [10]
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8. Design a Fintie State machine which can detect the sequence 1111 by using
JK Flip-flops. (Overlapping output) [10]
OR
9. Design a 4-bit up/down Synchronous binary counter. Explain with a neat timing
diagram. [10]

10. Reduce the number of states in the following state table using an implication table
method and tabulate the reduced state-table. [10]
PS NS Output
x=0 x=1 x=0 x=1
A F B 0 0
B D C 0 0
C F E 0 0
D G A 1 0
E D C 0 0
F F B 1 1
G G H 0 1
H G A 1 0
OR
11. Design a binary multiplier and its control logic by drawing ASM chart and realize
the same using decoder, MUX and D Flip-Flops. [10]

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