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Product Specifications

PART NO: VL393T2863M-E6S REV: 1.1

General Information
1GB 128Mx72 DDR2 SDRAM ECC REGISTERED DIMM 240-PIN

Description The VL393T2863M is a 128M X 72 DDR2 SDRAM high density DIMM. This memory module consists of
nine CMOS 128MX8 bit with 8 banks DDR2 Synchronous DRAMs in BGA packages, a 25-bit Registered
buffers in BGA package, a zero delay PLL clock in BGA package, and a 2K EEPROM in an 8-pin TSSOP
package. This module is a 240-pin registered dual in-line memory module and is intended for mounting into a
connector socket. Decoupling capacitors are mounted on the printed circuit board for each DDR2 SDRAM.

Features
. 240-pin, registered dual in-line memory module (RDIMM) Pin Name Function
. Fast data transfer rate: PC2-5300
. Supports ECC error detection and correction A 0 ~ A 13 Address Inputs
. VDD = VDDQ = 1.8V
BA0 ~ BA2 Bank Address Inputs
. VDDSPD = 1.7V to 3.6V
. JEDEC standard 1.8V I/O (SSTL_18 compatible) DQ0 ~ DQ63 Data Input/Output
. Differential data strobe (DQS, DQS# ) option C B0 ~ C B7 Check Bits
. Differential clock inputs (CK, CK#)
DQS0 ~ DQS8 Data Strobes
. Four-bit pre-fetch architecture
. DLL aligns DQ and DQS transition with CK DQS0# ~ DQS8# Data Strobes Complement
. Support duplicate output strobe (RDQS/RDQS#) ODT0 On-die Termination Control
. Programmable CAS# latency (CL): 5 (DDR2-667)
C K 0, C K 0# Differential Clock Input
. Write latency = Read latency - 1tCK
. Eight internal component banks for concurrent operation C KE0 Clock Enables
. Programmable burst; length (4, 8) C S 0# Chip Selects
. Adjustable data-output drive strength
RAS# Row Address Strobes
. On-die termination (ODT)
. Auto & self refresh, (8K/64ms refresh) C AS# Column Address Strobes
. Serial presence detect (SPD) with EEPROM WE# Write Enable
. Gold edge contacts
RESET# Register Reset Input
. Lead-free RoHS
. PCB: Height 30.00mm (1.181”), double sided components VD D Voltage Supply 1.8V +/- 0.1V
. PCB chamfer VD D Q I/O Power 1.8V +/- 0.1V

VSS Ground
Order Information SA0~SA2 SPD Address

SD A SPD Data Input/Output


VL393T2863M-E6 S X SC L SPD Clock Input
DRAM DIE (Option) DM0~DM8/ Data Masks/
DQS9~DQS17 Data Strobes (Read)
DRAM MANUFACTURER
DQS9#~DQS17# Data Strobes Complement (Read)
S - SAMSUNG
A10/AP Address input/Autoprecharge

MODULE SPEED VREF SSTL_18 Reference Voltage


E6: PC5300 @ CL5
VD D SPD SPD Voltage Supply 1.7V to 3.6V

NC No Connect

VL : Lead-free/RoHS

Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688


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PAGE 1 OF 10
Product Specifications
PART NO: VL393T2863M-E6S REV: 1.1

Pin C onfiguration
240-PIN D D R 2 RD IMM FR ON T 240-PIN D D R 2 RD IMM B AC K

Pin N ame Pin N ame Pin N ame Pin N ame Pin N ame Pin N ame Pin N ame Pin N ame

D M5/
1 VREF 31 D Q19 61 A4 91 VSS 121 VSS 151 VSS 181 VD D Q 211
D QS14

NC /
2 VSS 32 VSS 62 VD D Q 92 D QS5# 122 D Q4 152 D Q28 182 A3 212
D QS14#

3 D Q0 33 D Q24 63 A2 93 D QS5 123 D Q5 153 D Q29 183 A1 213 VSS

4 D Q1 34 D Q25 64 VD D 94 VSS 124 VSS 154 VSS 184 VD D 214 D Q46

D M0/ D M3/
5 VSS 35 VSS 65 VSS 95 D Q42 125 155 185 C K0 215 D Q47
D QS9 D QS12

NC / NC /
6 D QS0# 36 D QS3# 66 VSS 96 D Q43 126 156 186 C K 0# 216 VSS
D QS9# D QS12#

7 D QS0 37 D QS3 67 VD D 97 VSS 127 VSS 157 VSS 187 VD D 217 D Q52

8 VSS 38 VSS 68 NC 98 D Q48 128 D Q6 158 D Q30 188 A0 218 D Q53

9 D Q2 39 D Q26 69 VD D 99 D Q49 129 D Q7 159 D Q31 189 VD D 219 VSS

10 D Q3 40 D Q27 70 A10/AP 100 VSS 130 VSS 160 VSS 190 BA1 220 NC

11 VSS 41 VSS 71 BA0 101 SA2 131 D Q12 161 C B4 191 VD D Q 221 NC

12 D Q8 42 C B0 72 VD D Q 102 NC 132 D Q13 162 C B5 192 RAS# 222 VSS

D M6/
13 D Q9 43 C B1 73 WE# 10 3 VSS 133 VSS 163 VSS 193 C S 0# 223
D QS15

D M1/ D M8/ NC /
14 VSS 44 VSS 74 C AS# 104 D QS6# 134 164 194 VD D Q 224
D QS10 D QS17 D QS15#

NC / NC /
15 D QS1# 45 D QS8# 75 VD D Q 105 D QS6 135 165 195 OD T0 225 VSS
D QS10# D QS17#

16 D QS1 46 D QS8 76 NC/C S1# 106 VSS 136 VSS 166 VSS 196 A 13 226 D Q54

17 VSS 47 VSS 77 NC/ OD T1 107 D Q50 137 NC 167 C B6 197 VD D 227 D Q55

18 RESET# 48 C B2 78 VD D Q 108 D Q51 138 NC 168 C B7 198 VSS 228 VSS

19 NC 49 C B3 79 VSS 109 VSS 139 VSS 169 VSS 199 D Q36 229 D Q60

20 VSS 50 VSS 80 D Q32 110 D Q56 140 D Q14 170 VD D Q 200 D Q37 230 D Q61

21 D Q10 51 VD DQ 81 D Q33 111 D Q57 141 D Q15 171 NC/C KE1 201 VSS 231 VSS

D M4/ D M7/
22 D Q11 52 C KE0 82 VSS 112 VSS 142 VSS 172 VD D 202 232
D QS13 D QS16

NC / NC /
23 VSS 53 VD D 83 D QS4# 113 D QS7# 143 D Q20 173 NC 203 233
D QS13# D QS16#

24 D Q16 54 BA2 84 D QS4 114 D QS7 144 D Q21 174 NC 204 VSS 234 VSS

25 D Q17 55 NC 85 VSS 115 VSS 145 VSS 175 VD D Q 205 D Q38 235 D Q62

D M2/
26 VSS 56 VD D Q 86 D Q34 116 D Q58 146 176 A 12 206 D Q39 236 D Q63
D QS11

NC /
27 D QS2# 57 A11 87 D Q35 117 D Q59 147 177 A9 207 VSS 237 VSS
D QS11#

28 D QS2 58 A7 88 VSS 118 VSS 148 VSS 178 VD D 208 D Q44 238 VD DSPD

29 VSS 59 VD D 89 D Q40 119 SD A 149 D Q22 179 A8 209 D Q45 239 SA0

30 D Q18 60 A5 90 D Q41 120 SC L 150 D Q23 180 A6 210 VSS 240 SA1

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Product Specifications
PART NO: VL393T2863M-E6S REV: 1.1

Functional Block Diagram


RCS0#

DQS0# DQS4#
DQS0 DQS4
DM0 DM4

DM/ CS# DQS DQS# DM/ CS# DQS DQS#


RDQS RDQS
DQ0 DQ DQ32 DQ
DQ1 DQ DQ33 DQ
DQ2 DQ DQ34 DQ
DQ3 DQ DQ35 DQ
DQ4 DQ
D0 DQ36 DQ
D4
DQ5 DQ DQ37 DQ
DQ6 DQ DQ38 DQ
DQ7 DQ DQ39 DQ

DQS1# DQS5#
DQS1 DQS5
DM1 DM5
DM/ CS# DQS DQS# DM/ CS# DQS DQS#
RDQS RDQS
DQ8 DQ DQ40 DQ
DQ9 DQ DQ41 DQ
DQ10 DQ DQ42 DQ
DQ11 DQ DQ43 DQ
DQ12 DQ
D1 DQ44 DQ
D5
DQ13 DQ DQ45 DQ
DQ14 DQ DQ46 DQ
DQ15 DQ DQ47 DQ

DQS2# DQS6#
DQS2 DQS6
DM2 DM6
DM/ CS# DQS DQS# DM/ CS# DQS DQS#
RDQS RDQS
DQ16 DQ DQ48 DQ
DQ17 DQ DQ49 DQ
DQ18 DQ DQ50 DQ
DQ19 DQ DQ51 DQ
DQ20 DQ
D2 DQ52 DQ
D6
DQ21 DQ DQ53 DQ
DQ22 DQ DQ54 DQ
DQ23 DQ DQ55 DQ

DQS3# DQS7#
DQS3 DQS7
DM3 DM7
DM/ CS# DQS DQS# DM CS# DQS DQS#
RDQS RDQS
DQ24 DQ DQ56 DQ
DQ25 DQ DQ57 DQ
DQ26 DQ DQ58 DQ
DQ27 DQ DQ59 DQ
DQ28 DQ
D3 DQ60 DQ
D7
DQ29 DQ DQ61 DQ
DQ30 DQ DQ62 DQ
DQ31 DQ DQ63 DQ

DQS8#
DQS8
DM8
DM/ CS# DQS DQS#
Serial PD VDDSPD Serial PD
RDQS
CB0 DQ
CB1 DQ SCL VDD/VDDQ D0-D8
CB2 DQ SDA
WP A0 A1 A2
CB3 DQ VREF D0-D8
CB4 DQ
D8
CB5 DQ SA0 SA1 VSS D0-D8
VSS VSS
CB6 DQ
CB7 DQ

1:1
CS0# R RCS0# -> CS#: DDR2 SDRAMs D0-D8 CK0 PCK0 ~ PCK8 -> CK : DDR2 SDRAMs D0-D8
A0-A13 E RA0-RA13 -> A0-A13: DDR2 SDRAMs D0-D8 P
BA0-BA2 RBA0-RBA2 -> BA0-BA2: DDR2 SDRAMs D0-D8 L
G CK0# L PCK0# ~ PCK8# -> CK# : DDR2 SDRAMs D0-D8
RAS# I RRAS# -> RAS#: DDR2 SDRAMs D0-D8
PCK9 -> CK : Register
CAS# S RCAS# -> CAS#: DDR2 SDRAMs D0-D8 RESET # OE
PCK9# -> CK# : Register
WE# T RWE# -> WE#: DDR2 SDRAMs D0-D8
CKE0 E RCKE0 -> CKE0: DDR2 SDRAMs D0-D8
ODT 0 R RODT 0 -> ODT 0: DDR2 SDRAMs D0-D8

RESET # RST #

PCK9 Notes:
PCK9# 1. Unless otherwise noted, resistor value are 22 ohm +/-5%

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Product Specifications
PART NO: VL393T2863M-E6S REV: 1.1

Absolute Maximum Ratings


Symbol Parameter MIN MAX Unit

VDD Voltage on VDD pin relative to VSS -1.0 2.3 V

VDDQ Voltage on VDDQ pin relative to VSS -0.5 2.3 V

VDDL Voltage on VDDL pin relative to VSS -0.5 2.3 V

VIN, VOUT Voltage on any pin relative to VSS -0.5 2.3 V


0
TSTG Storage temperature -55 100 C
Address, BA,
-5 5 uA
RAS#, CAS#, WE#
Input leakage current; Any input 0V<VIN<VDD; CS#, CKE, ODT -5 5 uA
IL VREF input 0V<VIN<0.95V;
Other pins not under test = 0V CK, CK# -250 250 uA

DM -5 5 uA
Output leakage current;
IOZ DQ, DQS, DQS# -5 5 uA
0V<VOUT<VDDQ; DQs and ODT are disabled
IVREF VREF supply leakage current; VREF = Valid VREF level -18 18 uA

DC Operating Conditions
Symbol Parameter Min Typical Max Unit Notes
VDD Supply voltage 1.7 1.8 1.9 V 1

VDDQ I/O supply voltage 1.7 1.8 1.9 V 4

VDDL VDDL supply voltage 1.7 1.8 1.9 V 4

VREF I/O reference voltage 0.49 x VDDQ 0.50 x VDDQ 0.51 x VDDQ V 2

VTT I/O termination voltage VREF-0.04 VREF VREF+0.04 V 3

Note:
1. VDD, VDDQ must track each other. VDDQ must be less than or equal to VDD.
2. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on
VREF may not exceed +/-1percent of the DC value. Peak-to-peak AC noise on VREF may not exceed +/-2 percent of VREF. This
measurement is to be taken at the nearest VREF bypass capacitor.
3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and
must track variations in the DC level of VREF.
4. VDDQ tracks with VDD; VDDL tracks with VDD.

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Product Specifications
PART NO: VL393T2863M-E6S REV: 1.1

Operating Temperature Condition


Symbol Parameter Rating Units Notes
0
TOPER Operating temperature 0 - 95 C 1,2

Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions,
please refer to JEDEC JESD51.2
2. At 0 to 850C, operation temperature range, all DRAM specifications will be supported. The refresh rate is required to double when
85°C < TOPER <= 95°C

Input DC Logic Level


All voltages referenced to VSS

Symbol Parameter Min Max Unit

VIH(DC) Input High (Logic 1) Voltage VREF + 0.125 VDDQ + 0.300 V

VIL(DC) Input Low (Logic 0) Voltage -0.300 VREF - 0.125 V

Input AC Logic Level


All voltages referenced to VSS

Symbol Parameter Min Max Unit

VIH(AC) Input High (Logic 1) Voltage VREF + 0.200 - V

VIL(AC) Input Low (Logic 0) Voltage - VREF - 0.200 V

Input/Output
0
Capacitance
TA=25 C, f=100MHz

Parameter Symbol Min Max Unit

Input capacitance (A0~A13, BA0~BA2, RAS#, CAS#, WE#) CIN1 6.5 7.5 pF

Input capacitance (CKE0, ODT0, CS0#) CIN2 6.5 7.5 pF

Input capacitance (CK0, CK0#) CIN3 6 7 pF

Input/Output capacitance (DQ, DQS, DQS#, DM, CB) CIO 6.5 7.5 pF

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Product Specifications
PART NO: VL393T2863M-E6S REV: 1.1

IDD Specification
Condition Symbol -E6 Unit

Operating one bank active-precharge;


tCK = tCK(IDD) ; t RC= t RC(IDD) ; t RAS = tRAS MIN(IDD); CKE is HIGH, CS# is HIGH between valid IDD0* 930 mA
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING

Operating one bank active-read-precharge;


IOUT = 0mA; BL = 4; CL = CL(IDD);t CK= t CK(IDD); t RC= t RC(IDD); t RAS= t RAS MIN(IDD); CKE is HIGH,
IDD1* 1020 mA
CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus
inputs are SWITCHING; Data pattern is same as IDD4W.

Precharge power-down current;


All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; IDD2P** 435 mA
Data bus inputs are FLOATING

Precharge quiet standby current;


All banks idle; tCK = tCK(IDD); CKE is HIGH; CS# is HIGH; Other control and address bus inputs IDD2Q** 570 mA
are STABLE; Data bus inputs are FLOATING

Precharge standby current;


All banks idle; tCK = tCK(IDD); CKE is HIGH; CS# is HIGH; Other control and address bus inputs IDD2N** 615 mA
are STABLE; Data bus inputs are SWITCHING.

Active power-down current; Fast PDN Exit MRS(12) = 0mA 615 mA


All banks open; t CK= t CK(IDD); CKE is LOW; Other control
IDD3P**
and address bus inputs are STABLE; Data bus inputs
are FLOATING. Slow PDN Exit MRS(12) = 1mA 462 mA

Active standby current;


All banks open;t CK= t CK(IDD); t RC= t RC(IDD); t RAS= t RAS MIN(IDD));CKE is HIGH, CS# is HIGH between
IDD3N** 750 mA
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING.

Operating burst write current;


All banks open; Continuous burst writes; BL = 4; CL = CL(IDD); AL = 0; t CK= t CK(IDD);
IDD4W* 1245 mA
tRAS = tRAS MAX(IDD) ; t RP= tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address
bus inputs are SWITCHING; Data bus inputs are SWITCHING.

Operating burst read current;


All banks open; Continuous burst reads; IOUT = 0mA; BL = 4; CL = CL(IDD); AL = 0;
IDD4R* 1380 mA
tCK = tCK(IDD); t RAS= t RAS MAX(IDD) ; t RP= t RP(IDD); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W.

Burst auto refresh current;


t CK=t CK(IDD); Refresh command at every t RFC(IDD) interval; CKE is HIGH; CS# is HIGH between
IDD5** 1560 mA
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs
are SWITCHING.

Self refresh current;


CK and CK# at 0V; CKE < 0.2V; Other control and
Normal IDD6** 135 mA
address bus inputs are FLOATING; Data bus inputs are
FLOATING.

Operating bank interleave read current;


All bank interleaving reads; IOUT = 0mA; BL = 4; CL = CL(IDD); AL = t RCD(IDD) - 1*t CK(IDD);
tCK = tCK(IDD); t RC= t RC(IDD) ; t RRD = tRRD(IDD) ; tRCD = 1*tCK(IDD) ; CKE is HIGH; CS# is HIGH between IDD7* 2370 mA
valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are
SWITCHING.

Notes: IDDs were calculated using Samsung Q-die component.


*: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P ( CKE LOW) mode.
**: Value calculated reflects all module ranks in this operating condition.

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Product Specifications
PART NO: VL393T2863M-E6S REV: 1.1

AC Timing Parameters & Specifications


-E6
Parameter Symbol
Min Max U nit

C L=5 tCK (5) 3000 8000 ps

C lock cycle ti me C L=4 tCK (4) - - ps

C L=3 tCK (3) - - ps


Clock

C K hi gh-level wi dth tCH(AVG) 0.48 0.52 tCK

C K low-level wi dth tCL(AVG) 0.48 0.52 tCK

MIN
Half clock peri od tHP ps
(tCH,tCL)

C lock ji tter tJIT -125 125 ps

D Q output access ti me from C K/C K# tAC -450 +450 ps

D ata-out hi gh i mpedance wi ndow from C K/C K# tHZ tAC (MAX) ps

D ata-out low-i mpedance wi ndow from C K/C K# tLZ tAC (MIN) tAC (MAX) ps

D Q and D M i nput setup ti me relati ve to D QS tDS 100 ps


Data

D Q and D M i nput hold ti me relati ve to D QS tDH 175 ps

D Q and D M i nput pulse wi dth (for each i nput) tDIPW 0.35 tCK

D ata hold skew factor tQHS 340 ps

D Q–D QS hold, D QS to fi rst D Q to go nonvali d,


tQH tHP - tQHS ps
p e r a cce ss

D ata vali d output wi ndow (D VW) tDVW tQH - tDQSQ ns

D QS i nput hi gh pulse wi dth tDQSH 0.35 tCK

D QS i nput low pulse wi dth tDQSL 0.35 tCK

D QS output access ti me fromC K/C K# tDQSCK -400 +400 ps

D QS falli ng edge to C K ri si ng – setup ti me tDSS 0.2 tCK

D QS falli ng edge from C K ri si ng – hold ti me tDSH 0.2 tCK


Data Strobe

D QS–D Q skew, D QS to last D Q vali d, per group,


tDQSQ 240 ps
p e r a cce ss

D QS read preamble tRPRE 0.9 1.1 tCK

D QS read postamble tRPST 0.4 0.6 tCK

D QS wri te preamble setup ti me tWPRES 0 ps

D QS wri te preamble tWPRE 0.35 tCK

D QS wri te postamble tWPST 0.4 0.6 tCK

Wri te command to fi rst D QS latchi ng transi ti on tDQSS WL-0.25 WL+0.25 tCK

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Product Specifications
PART NO: VL393T2863M-E6S REV: 1.1

AC Timing Parameters & Specifications ( cont')


-E6
Parameter Symbol
Min Max U nit

Address and control i nput pulse wi dth for each i nput tIPW 0.6 tCK

Address and control i nput setup ti me tIS 200 ps

Address and control i nput hold ti me tIH 275 ps

C AS# to C AS# command delay tCCD 2 tCK

AC TIVE to AC TIVE (same bank) command tRC 60 ns


Command and Address

AC TIVE bank a to AC TIVE bank b command tRRD 7.5 ns

AC TIVE to READ or WRITE delay tRCD 15 ns

Four Bank Acti vate peri od tFAW 37.5 ns

AC TIVE to PREC HARGE command tRAS 45 70,000 ns

Internal READ to precharge command delay tRTP 7.5 ns

Wri te recovery ti me tWR 15 ns

Auto precharge wri te recovery + precharge ti me tDAL tWR+tRP tCK

Internal WRITE to READ command delay tWTR 7.5 ns

PREC HARGE command peri od tRP 15 ns

LOAD MOD E command cycle ti me tMRD 2 tCK

C KE low to C K,C K# uncertai nty tDELAY tIS+tCK+tIH ns

REFRESH to Acti ve or Refresh to Refresh command


tRFC 127.5 70,000 ns
Self Refresh

i nterval

Average peri odi c refresh i nterval tREFI 7.8 us

Exi t self refresh to non-READ command tXSNR tRFC(MIN)+10 ns

Exi t self refresh to READ tXSRD 200 tCK

Exi t self refresh ti mi ng reference tISXR tIS ps

OD T turn-on delay tAOND 2 2 tCK

tAC(MAX)+
OD T turn-on tAON tAC(MIN) ps
700

OD T turn-off delay tAOFD 2.5 2.5 tCK

tAC(MAX)+
OD T turn-off tAOF tAC(MIN) ps
ODT

600

tAC(MIN)+ 2 x tCK + tAC(MAX)+


OD T turn-on (power-down mode) tAONPD ps
2000 1000

tAC(MIN)+ 2.5 x tCK + tAC(MAX)+


OD T turn-off (power-down mode) tAOFPD ps
2000 1000

OD T to power-down entry latency tANPD 3 tCK

OD T power-down exi t latency tAXPD 8 tCK

Exi t acti ve power-down to READ command,


tXARD 2 tCK
Power-Down

MR[bi t12=0]

Exi t acti ve power-down to READ command,


tXARDS 7-AL tCK
MR[bi t12=1]

Exi t precharge power-down to any non-READ


tXP 2 tCK
command.

C KE mi ni mum hi gh/low ti me tCKE 3 tCK

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Product Specifications
PART NO: VL393T2863M-E6S REV: 1.1

Package Dimensions

FRONT VIEW
3.95
MAX
133.35
3.00 (4X)
TYP.

4.00 +/- 0.10 (4X)

+ 0.50
30.00
- 0.15

17.80
TYP.
A

PIN 1 1.27 +/- 0.10


5.175 (2X) 1.50
TYP. 1.00 0.80 TYP. 10.00
TYP.
123.00
PIN 120
TYP.

BACK VIEW

0.20 ( Max )
(2X)
0.05 ( Min )

(2X) 0.20 ( Max )


0.05 ( Min )

DETAIL A

PIN 240 PIN 121


5.00 TYP.
3.80
TYP. 55.00 63.00
TYP. TYP.

NOTE:
All dimensions are in millimeters with tolerance +/- 0.15mm unless otherwise specified.

Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688


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Product Specifications
PART NO: VL393T2863M-E6S REV: 1.1

Revision History:

D ate R ev. P ag e C h an g es
07/31/09 1.0 All Spec release

Update information for using Samsung DRAM F-die page 1


08/28/10 1.1 1,4,5 Update Input leak current of CK, CK# = +/-250 page 4
Update Input/Output capacitance page 5

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