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4/12/2018 Time borrowing in latches

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Setup And Hold – The

Device Perspective You and 1 o
Time borrowing in latches
Design Problem:
Clock Gating For A What is time borrowing: Latches exhibit the property of being transparent when clock is asserted to a
Shift Register required value. In sequential designs, using latches can enhance performace of the design. This is
possible due to time borrowing property of latches. We can define time borrowing in latches as follows:
MOS Transistor
Structure Time borrowing is the property of a latch by virtue of which a path ending at a latch can
borrow time from the next path in pipeline such that the overall time of the two paths
What Is The remains the same. The time borrowed by the latch from next stage in pipeline is, then,
Difference Between A subtracted from the next path's time.
Normal Buffer And
Clock Buffer? The time borrowing property of latches is due to the fact that latches are level sensitive; hence, they
can capture data over a range of times than at a single time, the entire duration of time over which
Performance Gain they are transparent. If they capture data when they are transparent, the same point of time can
With Latches
launch the data for the next stage (of course, there is combinational delay from data pin of latch to
output pin of latch).
How Delay Of A
Standard Cell
Changes With Drive
Let us consider an example wherein a negative latch is placed between two positive edge-triggered
Strength registers for simplicity and ease of understanding. The schematic diagram for the same is shown in
figure 1 below:
What Is Meant By
Drive Strength Of A
Standard Cell

Setup/Hold – The
State Machines

Design Problem: How

Can You Convert An
Figure 1: Negative level-sensitive latch between two positive edge-triggered registers
XOR Gate Into A
Buffer Or An Inverter?
Figure 2 below shows the clock waveform for all the three elements involved. We have labeled the
Minimum Pulse Width clock edges for convenience. As is shown, latB is transparent during low phase of the clock. RegA and
Violation Example
RegC (positive edge-triggered registers) can capture/launch data only at positive edge of clock; i.e., at
Edge1, Edge3 or Edge5. LatB, on other hand, can capture and launch data at any instant of time
Popular po
Recent Posts Widget between Edge2 and Edge3 or Edge4 and Edge5.

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in an IC le
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4/12/2018 Time borrowing in latches

Setup and hold


Positive, form of win

negative and
zero setup time

STA problem :
Hold time
manipulation required to

negative and
zero hold time Figure 2: Clock waveforms

DFT basics and p...

The time instant at which data is launched from LatB depends upon the time at which data launched
from RegA has become stable at the input of latB. If the data launched at Edge1 from RegA gets
stable before Edge2, it will get captured at Edge2 itself. However, if the data is not able to get stable,
even then, it will get captured. This time, as soon as the data gets stable, it will get captured. The
latest instant of time this can happen is the latch closing edge (Edge3 here). One point here to be
noted is that at whatever point data launches from LatB, it has to get captured at RegC at edge3. The especially
more time latch takes to capture the data, it gets subtracted from the next path. The worst case setup modes....
check at latB is at edge2. However, latch can borrow time as needed. The maximum time borrowed,
ideally, can be upto Edge3. Figure 3 below shows the setup and hold checks with and without time
borrow for this case:

used to sh

Also read


Figure 3: Setup check with and without time borrow

The above example consisted of a negative level-sensitive latch. Similarly, a positive level-sensitive
latch will also borrow time from the next stage, just the polarities will be different.

Also read:
Also read
Can a net have
negative Lockup latch - principle, application and timing
propagation Setup check and hold check for register to latch timing paths
False paths - basics and example scenarios
Can hold be frequency dependent
inversion –
concept and
phenomenon This post was useful Yes (0) Maybe (0) No (0)

Can hold check

Labels: hold time, Latch setup and hold, STA, Static timing analysis, time borrow, Time borrowing
be frequency

C function that
value to decimal
value. 2/4
4/12/2018 Time borrowing in latches

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