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Multilevel inverter

Multilevel inverter

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6, December 2011

Multilevel Inverter

P. Thongprasri

Abstract—This paper presents a 5-level three-phase cascaded hardware, also the control will be more complicated. It is a

hybrid multilevel inverter that consists of a standard 3-leg (one tradeoff between price, weight, complexity and a very good

leg for each phase) and H-bridge in series with each inverter leg output voltage with lower THD. Fig. 1 shows single phase

with separate DC voltage sources, 24V and 48V. The control

signals for this hybrid multilevel inverter are implemented by a

topology of the diode Clamped, flying capacitor, a cascaded

FPGA controller using PWM signal modulated technique and H-bridge, and cascade hybrid multilevel inverter that they

digital technique. A 5-level three-phase cascaded hybrid have the number of switches, diodes, and capacitors as shown

multilevel inverter model based on PSCAD/EMTDC is in table I (a 5- level multilevel inverter).

presented in this paper. The proposed hybrid multilevel

inverter is described in detail that it is verified experimentally S1 S1

in three types of load; 18W fluorescent lamp-ballast, RL, and C1 C1

S2 C5 S2

1HP 3-phase induction motor; without filtering. Results of the

S3 C8 S3

experiment; the output waveform of line-line and phase C2 C2

voltages has 5 levels that percent of THD is between 15.6% and S4 Vo C6 C10 S4 Vo

18.3%, the output waveform of phase current is close to Vdc S5 Vdc C9 S5

sinusoidal that percent of THD is between 2.7% and 4.2%. C3 S6 C3 C S6

7

S7 S7

Index Terms—Hybrid multilevel inverter, PSCAD/EMTDC, C4 S8 C4 S8

FPGA controller, h-bridge.

(a) Diode Clamped (b) Flying capacitor

multilevel inverter multilevel inverter

I. INTRODUCTION

Vdc S1 S2 Vo V S1 S2 Vo

A multilevel inverter is a power electronic converter built dc

2

to synthesize a desired AC voltage from several levels of DC S3 S4 S3 S4

voltages which the DC levels were considered to be identical

in that all of them were batteries, solar cells, capacitors, etc. S5

Vdc S5 S6 Vdc C1

The multilevel inverter has gained much attention in recent

years due to its advantages in lower switching loss better S7 S8 C2 S6

electromagnetic compatibility, higher voltage capability, and (c) Cascaded H-bridge (d) Cascaded Hybrid

lower harmonics [1]-[3]. Several topologies for multilevel multilevel inverter multilevel inverter

inverters have been proposed; the most popular being the

Fig. 1. One phase of a 5-level multilevel inverter.

diode-clamped [4], [5], flying capacitor [6], and cascade H-

bridge [7] structures. Besides the three basic multilevel TABLE I: COMPONENTS OF ONE PHASE OF A-5 LEVEL

inverter topologies; other multilevel converter topologies MULTILEVEL INVERTER

have been proposed, most of these are hybrid circuits that are Types of multilevel Number of Number of Number of

combinations of two of the basic multilevel topologies. The inverter switches diodes capacitors

schemes of multilevel inverters are classified in to two types Diode Clamped 8 12 4

the multicarrier sub-harmonic pulse width modulation (MC- Flying capacitor 8 - 10

Cascaded H-bridge 8 - -

SH PWM) and the multicarrier switching frequency optimal

Cascade hybrid 6 - 2

pulse width modulation (MC-SFO PWM) [8], [9]. The

MC-SH PWM cascaded multilevel inverter strategy reduced

total harmonic distortion and the MC-SFO PWM cascade In this paper, the proposed a 5-level three-phase cascaded

multilevel inverter strategy enhances the fundamental output hybrid multilevel inverter includes a standard 3-leg inverter

voltage [10]. (one leg for each phase) and H-bridge in series with each

The THD will be decreased by increasing the number of inverter leg as shown in Fig. 2. To develop the model of a

levels. It is obvious that an output voltage with low THD is 5-level cascaded hybrid multilevel inverter, a simulation is

done based on PSCAD/EMTDC. All signals for controlling

Manuscript received August 4, 2011; revised September 31, 2011.This the hybrid multilevel inverter are created by a FPGA

work was supported by the Department of Electrical Engineering, Faculty of controller using PWM signal modulated technique and digital

Engineering at Si Racha, Kasetsart University Si Racha Campus, and

Thailand.

technique. The prototype is tested with 3 types of load; a 18W

P. Thongprasri is with the Department of Electrical Engineering, Faculty fluorescent lamp-ballast, RL (R is 265 Ω , L is 0.125 H ),

of Engineering at Si Racha, Kasetsart University Si Racha Campus, and a 1HP 3-phase induction motor (no load); without

Chonburi, Thailand (e-mail: sfengprt@ src.ku.ac.th).

filtering.

789

International Journal of Computer and Electrical Engineering, Vol. 3, No. 6, December 2011

THE HYBRID MULTILEVEL INVERTER Vdc i

2 v2 v

Sa2 Sa4

Va Vc

LOAD

Vb

Sa1 Sa3 Sb1 Sb3 Sc1 Sc3 S1

Vdc v1

Vdc Vdc S Vdc S Sc4

Sa2 Sa4 b2 Sb4 c2 S2

2 2 2

Fig. 3. Single phase topology of the hybrid multilevel inverter.

S1 S3 S5

Vdc

S2 S4 S6 +vdc

v =v1 +v2

Fig. 2. Topology of a 5-level three-phase cascaded hybrid

+vdc/2 i

multilevel inverter.

π 2π

Fig. 2 shows the topology of the proposed a 5-level

−vdc/2

3-phase cascaded hybrid multilevel inverter. Single phase

topology of the hybrid multilevel inverter is shown in Fig. 3; −vdc

the bottom is one leg of a standard 3-leg inverter with a dc

Fig. 4. Output waveform of the hybrid multilevel inverter.

power source ( Vdc ), the top is a hybrid in series with each

standard inverter leg that the H-bridge inverter can use a Fig. 6 shows the relationship between the sinusoidal

separate dc power source ( Vdc / 2 ). Considering the output reference signal and the triangular signal which used to create

the PWM signal; the output of the PWM signal is either 1,

voltage v1 of this leg is either +Vdc / 2 when S1 closed or when Vctrl > Vtri or 0 when, Vctrl < Vtri , and the PWM signal

−Vdc / 2 when S2 closed. This leg is connected in series with width can be written as equation (1).

a full H-bridge inverter, then the output voltage v2 of the

TPWM = Actrl ⋅ Ttri ;0 ≤ Actrl ≤ 1 (1)

H-bridge inverter is either +Vdc / 2 when S a1 , S a 4 closed, 0

when Sa1 , Sa3 or Sa2 , Sa4 closed, or −Vdc / 2 when Sa2 , Sa3 Nomenclature:

closed. An example output waveform that this topology can TPWM Width of the PWM signal.

achieve as shown in the Fig. 4, when the output voltage Actrl Height of the control signal.

v = v1 + v2 is required to be zero, one can either set

Ttri Period of the triangular signal.

v1 = +vdc / 2 and v2 = −vdc / 2 or v1 =−vdc / 2, and v2 =+vdc/2.

In [11], several different two-level multilevel carrier-based

Vctrl Output voltage of the control signal.

PWM techniques have been extend for controlling the active Vtri Output voltage of the triangular signal.

devices in a multilevel converter, the most popular and

easiest technique to implement uses several triangle carrier 2

signals and one reference, or modulation, signal per phase. In 1

order to achieve better dc link utilization at high modulation

0

indices, the sinusoidal reference signal can be injected by a

third harmonic with a magnitude equal to 25% of −1

fundamental. −2

Fig. 5 shows MC-SH PWM of a 5-level inverter, m-1 Fig. 5. MC-SH PWM of a 5-level inverter.

carriers with the same frequency f c and the same amplitude Vcontrol Vtri

Ttri

Ac are dispose such that the bands they occupy are

contiguous, The reference waveform has peak-to-peak Ar

Tctrl

compared with each of the carrier signals. If the reference is Vctrl >Vtri

greater than a carrier signal, then the active device 1

PWM

corresponding to that carrier is switched on, and if the 0

reference is less than a carrier signal, then the active device Fig. 6. The relationship between the sinusoidal referencesignal and the

corresponding to that carrier is switched off. triangular signal.

790

International Journal of Computer and Electrical Engineering, Vol. 3, No. 6, December 2011

+Vdc/2

0

The simulation model based on PSCAD/EMTDC is shown

−Vdc/ 2 in appendix; Vdc are 24V and 48V, RL load (R is 265 Ω , L

Signals for 3 − phase inverter

+Vdc/2

0 is 0.125 H ), sinusoidal reference signal frequency is 50Hz,

−Vdc / 2

carrier signal frequency is 2,500Hz, and ma is 0.8.

Output waveform of hybrid inverter

+Vdc

+Vdc/2

0

−Vdc /2

Mod.

− V dc

0 π /6 5π / 6 π 7π / 6 10π / 6 2π

Fig. 7. Output waveform of the 5-level hybrid multilevel inverter. PWM

(v3 )

Vdc

0 v 2

− Vdc Output

1

Mod.

0

v1

PWM (v3)

1

0

1 Fig. 9. Simulation result of v1 , v2 , v3 , and modulated signal.

0 v2

1 v1

0

0 π 5π π 7π 10π 2π Results of the simulation; Fig. 9 shows modulated signal, v1 ,

6 6 6 6

Fig. 8. Signals for controlling the hybrid multilevel inverter. v2 , and PWM (v3 ) signals. Fig. 10 shows all control signals

Fig. 7 shows output waveform of the 5-level cascaded for the power electronic switches. Fig. 11 shows the output

hybrid multilevel inverter that it is used to be the pattern to waveform of phase voltage and phase current.

create the control signal for hybrid multilevel inverter. PWM

(v3 ), v1 , and v2 signals shown in Fig. 8 are the parameters S1

S2

shown in table II. Modulated signal is created as equation (2)

and (3), amplitude modulation index ma can be found at the S a1

Sa3

⎧ π

⎪ 0 ≤ ωt < 6 Sa 4

TPWM = maTtri (1 − 2 sin(ωt )) ; ⎨ (2)

5π

⎪ < ωt ≤ π Fig. 10. Simulation result of all control signals for electronic switch

⎩6 devices (IGBTs).

π 5π

TPWM = maTtri ( 2 sin(ωt ) − 1) ; ≤ ωt ≤ (3)

Va

6 6

Vb

V

ma = ctrl (4)

Vtri Vc

ia ib i c

TABLE II: DIGITAL PROCESS OF THE CONTROL SIGNALS.

Electronic switch devices Digital process

s1 v1

Fig. 11. Simulation result of phase voltage and phase current when load is

s2 v1 RL (R is 265 Ω , L is 0.125 H ).

sa 2 Fig. 12 shows the topology of the hybrid multilevel

v3 ⋅ ((v1 ⋅ v2 ) + (v1 ⋅ v2 ))

inverter with separate DC voltage sources ;24V and 48V; that

sa 3 v3 ⋅ ((v1 ⋅ v2 ) + (v1 ⋅ v2 )) the IGBTs (GT60M303) are used to be power electronic

switches in the H-bridge inverter, and the IGBT modules

sa 4 v3 ⋅ ((v1 ⋅ v2 ) + (v1 ⋅ v2 )) (CM75DU-12H) are used to be power electronic switches in

the 3-phase inverter. The output voltage of the hybrid

791

International Journal of Computer and Electrical Engineering, Vol. 3, No. 6, December 2011

multilevel inverter is connected to a 3-phase step up including output waveform of line-line voltage that line-line

transformer (55/380V/50Hz, Y-Y) rated 1.5kW. Prototype of voltage THD is 17.9%, 17.4%, and 18.3%.

the 1kW 5-level three-phase cascaded hybrid multilevel

inverter as shown in Fig. 13 has been built in order to verify

the proposed hybrid multilevel inverter. The control signals

in this paper are created by the field programmable gate array

(FPGA, discovery–III XC3S200 model) controller. Fig. 14

shows three signals; PWM (v3 ) , v1 , and v2 ; for the hybrid

multilevel inverter, modulation index is 0.8.

step up transformer

Va

Vb Y −Y R

s

v3

Vc 55 / 380V T

N

H − bridge inverter v2

Sa1 Sa3 Sb1 Sb3 Sc1 Sc3

24V 12V 12V

S1 S3 S5

48V

S2 S4 S6 Fig. 14. The control signals for hybrid multilevel inverter are created by

FPGA ( ma =0.8).

3 − phase inverter

Fig. 12. Topology of the hybrid multilevel inverter with separate DC voltage

sources; 24V and 48V.

H − bridge inverter

Fig. 15. Prototype of the 1kW 5-level three-phase cascaded hybrid multilevel

inverter with 3 fluorescent lamp-ballast loads.

cascaded hybrid multilevel inverter with a 3-phase induction

motor load (no load). Fig. 23 shows the experimental results

including phase voltage and phase current; the output phase

dc sources and voltage waveform has 5 levels that its rms voltage is 206V,

3 − phase step up transforme r

and the phase current waveform is close to sinusoidal that its

Fig. 13. Prototype of the 5-level 3-phase cascaded hybrid multilevel inverter.

rms current is 786mA, and the output frequency is 50Hz. Fig.

Fig. 15 shows prototype of the 1kW 5-level three-phase 24 shows the experimental result including the phase voltage

cascaded hybrid multilevel inverter with a 18W fluorescent THD of 16%, and phase current THD of 4.2%. Fig. 25 shows

lamp-ballast load. Fig. 16 shows the experimental results the experimental result including output waveform of

including phase voltage and phase current; the output phase line-line voltage that line-line voltage THD is 16.2%, 15.6%,

voltage waveform has 5 levels that its rms voltage is 225V, 16.7%, and the output frequency is 50 Hz.

and the phase current waveform is close to sinusoidal that its

rms current is 360mA. Fig. 17 shows the experimental result

including output waveform of line-line voltage and line-line

that voltage THD is 17.4%, 16.6%, and 18%.

Fig. 18 shows prototype of the 1kW 5-level three-phase

cascaded hybrid multilevel inverter with RL load (R is 265

Ω, L is 0.125 H ). Fig. 19 shows the experimental results

including phase voltage and phase current; the output phase

voltage waveform has 5 levels that its rms voltage is 195V,

and the phase current waveform is close to sinusoidal that its

rms current is 708mA. Fig. 20 shows the experimental result

Fig. 16. The output waveform of phase voltage and phase current (The top is

including the phase voltage THD of 17% and phase current phase voltage that its rms voltage is 225V, the bottom is phase current that its

THD of 2.7%. Fig. 21 shows the experimental result rms current is 360mA).

792

International Journal of Computer and Electrical Engineering, Vol. 3, No. 6, December 2011

Fig. 22. Prototype of the 1kW 5-level three-phase cascaded hybrid multilevel

Fig. 17. The output waveform of line-line voltage that line-line voltage THD inverter with a 3-phase induction motor rated 1HP load (no load).

is 17.4%, 16.6%, and 18%. The output frequency is 50Hz.

Fig. 23 . The output waveform of phase voltage and phase current (The top is

Fig. 18. Prototype of the 1kW 5-level three-phase cascaded hybrid multilevel phase voltage that its rms voltage is 206V, the bottom is phase current that its

inverter with RL load (R is 265 Ω , L is 0.125 H ). rms current is 786mA).

Fig. 24. The output waveform of phase voltage THD of 16%, phase current

THD of 4.2%. The output frequency is 50 Hz.

Fig. 19. The output waveform of phase voltage and phase current (The top is

phase voltage that its rms voltage is 195V, the bottom is phase current that its

rms current is 708mA).

Fig. 25. The output waveform of line-line voltage that line-line voltage THD

is 16.2%, 15.6%, 16.7%. The output frequency is 50Hz.

Fig. 20. Phase voltage THD of 17%, phase current THD of 2.7%, the output V. CONCLUSION

frequency is 50 Hz. (RL load, R is 265 Ω , L is 0.125 H ). Prototype of the 5-level three-phase cascaded hybrid

multilevel inverter consists of a 3-phase inverter and 3

H-bridge inverters that it uses separate dc power sources;

24V and 48V. The control signals for power electronic

switches are created by FPGA controller using PWM signal

modulated technique and digital technique. The prototype is

tested with three types of load; 18W fluorescent ballast-lamp,

RL, and 3-phase induction motor rated 1HP; without filtering.

Results of the test; the output line-line and phase voltages has

5 levels that its THD voltage is between 15.6% and 18.3%,

the output waveform of phase current is close to sinusoidal

Fig. 21. The output waveform of line-line voltage that line-line voltage THD

is 17.9%, 17.4%, and 18.3%. The output frequency is 50Hz. that its THD current is between 2.7% and 4.2%.

793

International Journal of Computer and Electrical Engineering, Vol. 3, No. 6, December 2011

converters for large electric drives,” “IEEE Trans. Ind. Applica.”,

APPENDIX vol.35, no.1, pp. 36-44, Jan./Feb.1999.

[3] K. A. Corzine, M. W. Wielebski, F. Z. Peng, and J. Wang, “Control

of Cascaded Multilevel Inverters,” IEEE Trans. power electron,

vol.19, no.3, pp. 732-738, May 2004.

[4] M. Fracchia, T. Ghiara, M. Marchesoni, and M. Mazzucchelli,

“Optimized modulation techniques for the gemeralized N-level

converter,” in proc. IEEE power electronics specialist conf,

1205-1213, Madrid, Spain, 1992.

[5] K. A. Corzine and J. R. Baker, “Reduced parts-count multilevel

retifiers,” “IEEE Trans. Ind. Electron.” vol.49, no.3, pp. 766-774,

Aug. 2002.

[6] F. Z. Peng, “A generalized multilevel inverter topology with self

voltage balancing,” “IEEE Trans. Ind. Applica,” vol. 37, pp.

611-618, Mar./April 2004.

[7] M. D. Manjrekar, P. K. Steimer, and T. A. Lipo, “Hybrid

multilevel power conversion system: a competitive solution for

high-power applications,” “IEEE Trans. Ind. Applica,” vol. 36, pp.

834-841, May/June 2000.

[8] L. M. Tolber and T. G. Habetler, “Novel Multilevel Inverter

Carrier based PWM Method,” IEEE Trans. Ind. Applic, vol. 35,

pp. 1098-1107, Sep/Oct 1999.

[9] B. P.McGrath and Holmes, “Multicarrier PWM strategies for

multilevel inverter,” IEEE Trans. Ind. Electron, vol. 49, no. 4, pp.

834-841, Aug 2002.

[10] A. M.Hava, R. J.Kerman, and T.A.Lipo “Carrier-based PWM-VSI

Fig. 26. The simulation model of a 5-level three- phase cascaded

Overmodulation Strategies: Analysis, Comparison, and Design,”

multilevel inverter based on pscad/emtdc (single phase).

IEEE Trans. Power Electron, vol. 13, no. 4, pp. 834-841, Jul.

1998.

[11] S. Khomfoi, L. M. Tolbert, “Multilevel Power Converters,” “2nd ed.

ACKNOWLEDGMENT Power Electronics Handbook,” Elsevier, 2007, ch. 31, pp. 1-50.

Engineering at Si Racha, Kasetsart University Si Racha

P. Thongprasri was born in Suphanburi,

Campus, THAILAND, for instrument support on this Thailand, on June 19, 1971. He received the

research. B.Eng. degree in electronic engineering and

M.Eng. degree in electrical Engineering from

King Mongkut Institute of Technology

REFERENCES Ladkrabang, Thailand, in 1995 and 2005,

[1] J. S. Lai and F. Z. Peng, “Multilevel converters – A new breed of respectively. He is currently lecturer at the

power converters,” IEEE Trans. Ind. Applica, vol. 32, no. 3, pp. Department of Electrical Engineering, Faculty of Engineering at Si Racha,

509-517, May/June 1996. Kasetsart University Si Racha Campus, Thailand. His research interests

are Power Converters, Power Electronics, Robotics, Applications of

Microcontroller and FPGA controller.

794

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