Laboratory Manual for

LINEAR ELECTRONICS-I

B. E.
SEM. III (EC)

January 2010

Faculty of Technology
Dharmsinh Desai University
Nadiad
 TABLE OF CONTENTS

Sr. No. Title Page No.

1. Characteristics of PN Junction Diode. 4

2. Characteristics of Zener Diode. 6

3. Study of Clipper Circuit. 8

4. Study of Clamper Circuit. 9

5. Four-Diode Bridge Sampling Gate circuit. 11

6. Input and Output Characteristics of a CE Configuration. 13

7. Input and Output Characteristics of a CC Configuration. 17

8. Frequency Response of RC Coupled CE Amplifier. 21

9. Drain and Transfer Characteristics of FET. 23

10.Square Wave Response of CE Amplifier. 25

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 2
 LAB MANUAL

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 3
 LAB 1
Characteristics of PN Junction Diode.
AIM: To verify the characteristics of PN Junction diode under forward bias & reverse bias.

APPARATUS: Bread board, D.C. Power Supply, Digital Multimeter, Diode IN4001,
Resistor 1KOhm.

THEORY:

The diode has a very important property, it permits only unidirectional conduction. It
conducts well in the forward direction and poorly in the reverse direction. An ideal diode acts
as a closed switch, when forward biased and as an open switch when reverse biased. In
practical case the diode conducts when voltage across the diode is more than the barrier
voltage i.e. 0.7 V for Silicon Diode and 0.3 V for Germanium diode and a current of few milli
Ampere flows through the Diode.
In reverse bias a small current of a few microamperes flows through the diode. Care
should be taken that the reverse voltage applied is not greater than the specified
breakdown voltage otherwise the diode will get permanently damaged.

CIRCUIT DIAGRAM:

Fig 1. Forward Biased Diode

Fig2. Reverse Biased Diode

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 4
PROCEDURE:
1. For Forward Characteristics Connect the circuit as shown in Figure.1
2. Vary Vs in steps of 0.2 V up to 1.0 V.
3. After 1 V go in steps of 1 V up to 10 V
4. Measure the voltage drop across the diode (Vd) and Resistance (Vr) for each value
of Vs.
5. Calculate the current through the diode by Vr/R. where Vr is the drop across the
resistance and R is the value of the resistance.
6. Note down the readings in the observation table.
7. For Reverse Characteristics connect the circuit as shown in fig 2.
8. Adjust the Reverse voltage to 20 V, Note down the reverse current.
9. Plot the graph of Vs vs I

OBSERVATION TABLE:

Vs(Volts) Vd(Volts) I= VR/R(mA)

CONCLUSION:

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 5
 LAB 2

Characteristics of Zener Diode.

AIM: To verify the characteristics of Zener diode under reverse bias.

APPARATUS: Bread board, D.C. Power Supply, Digital Multimeters, Zener Diode, Resistor

THEORY:

Zener diodes are designed to operate in the reverse biased breakdown region without
damage. By varying the doping levels it is possible to produce zener diodes with breakdown
from about 2 V to 200V. In forward bias it acts a normal P –N junction diode. In the case of
reverse bias large amount of current flows after the input voltage has increased its
breakdown voltage.This is because of two effects (1) Zener Effect and (2) Avalanche effect.
If the applied reverse voltage exceeds the breakdown voltage, a zener diode acts like a
constant voltage source.
The most common application of zener diode is voltage regulator.

CIRCUIT DIAGRAM:

Fig: Reverse Biased Zener Diode

PROCEDURE:
1. Connect the circuit as shown in Figure for studying the reverse characteristics.
2. Increase Vs in steps of 2 V up to 20 V insteps of 2 V.
3. Measure the current through the diode IZ and the voltage drop across the diode VZ.
4. Connect the circuit so that the Zener Diode is forward biased. Note down the
readings of Vz and Iz by increasing supply voltage from 0. 1 to 10 V. from 0.1 to 1 V
increase in steps of 0.2 V
5. Plot the V-I characteristics for forward and reverse bias and note down your
conclusion.

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 6
OBSERVATION TABLE:

Vs(Volts) VZ(Volts) IZ

CONCLUSION:

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 7
 LAB 3

Study of Clipper Circuit

AIM: To Observe the clipping waveform in different clipping configurations using diode.

APPARATUS: Bread Board, CRO, DC power supply, millimeters, resistors, diode.

THEORY:

Once the input voltage exceeds V1 the diode D1 starts conducting but diode D2 does not,
since it is in reverse bias. As a result the output voltage does not go above V1. On the
negative swing of input, the diode D2 conducts, but D1 does not, hence it clips the input
voltage at negative side, so that the output does not exceed above V2.The clipping levels are
adjusted by the voltages V1 and V2. The source resistance Rs should be much larger than
the forward resistance of diode but should be smaller than the reverse resistance of diode.

CIRCUIT DIAGRAM:

Fig: Two voltage level clipper

PROCEDURE:
1. Connect the circuit as shown in fig.
2. Apply sine wave of 1 kHz signal from function generator.
3. Observe the output waveform on CRO.
4. Draw the input and output waveform on graph with scale.

CONCLUSION:

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 8
 LAB 4
Study of Clamper Circuit
AIM: To study the negative clamper circuit.

APPARATUS: Bread board, Diode IN4001, Resistor 10 K , Capacitor 1 F, Signal

generator (0-100kHz), CRO.

THEORY:

A simple RC coupling circuit blocks direct current but lets the alternating current pass
unchanged. So to restore the DC component along with AC, we need a clamper circuit as
shown in figure above. Under the ideal conditions, during positive cycle of the sinusoidal
signal having peak amplitude Vm, the diode will conduct and hence the capacitor gets
charged to the peak value of the input signal (i.e. Vm).When the input voltage becomes
positive again, then the output voltage will be input voltage minus the voltage across the
charged capacitor and hence in our case maximum output voltage during positive
cycle will be (Vm – Vm) = 0. This means the diode will not conduct after the capacitor is fully
charged. The charged capacitor has the same effect as a battery of voltage Vm in series with
input.
Using the principle of superposition, the output voltage is the ac input voltage minus
a dc value of Vm. The shape of the output voltage and the maximum negative output voltage
depends on the time constant R1C1.
If input frequency f = 10 kHz, then T = 1/f = 10-2 sec = R1C1
Assume C1 = 1µF then R1 = 10 KΩ

CIRCUIT DIAGRAM:

Fig: Negative clamper circuit

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 9
PROCEDURE:
1. Connect the circuit as per the circuit diagram on the bread board.
2. Set the input signal voltage (say 5V, 10 kHz sine wave) using the signal generator.
3. Observe the output waveform using CRO (DC-mode).
4. Sketch the observed waveform with reference to the input waveform.
5. Modify the input frequency (below and above 10 kHz) and see the effect on the
output waveform.
6. Now connect the diode in reverse manner and repeat all steps from 1) to 5).

CONCLUSION:

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 10
 LAB 5

Four-Diode Bridge Sampling Gate circuit

AIM: To observe the output of a four-diode bridge sampling gate circuit.

APPARATUS: Bread board, two Signal generators, C.R.O., Diodes, Resistors.

THEORY:

An ideal sampling gate is a transmission circuit in which the output is an exact reproduction
of an input waveform during a selected time interval and is zero otherwise. The time interval
for transmission is selected by an externally impressed signal, called control or gating signal
and is usually square wave with different duty cycle. These sampling gates are also referred
to as transmission gates or time-selection circuits. A four diode sampling gate is shown in
figure. In this circuit the sinusoidal signal is applied to the point where anode of D4 and
cathode of D3 are joined and the control voltage is applied through the resistance R1 = R2. In
most practical systems the period of control signal should be equal or be an integral multiple
of input signal.
During the positive cycle of control voltage, all the four diodes conduct and hence the
output voltage will be same as input signal. During the negative cycle of the control voltage,
all the four diodes are non-conducting and hence the current through R3 is zero, so output
voltage is zero. To ensure that all four diodes conduct during positive cycle of control
voltage, the minimum value of control voltage should be equal to [2 + (R 1/R3)] time signal
voltage.

CIRCUIT DIAGRAM:

Fig: Sampling gate circuit

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 11
PROCEDURE:
1. Connect the circuit on bread board as shown in circuit diagram.
2. Apply the sinusoidal signal of 1 kHz (say 3 V peak) to the terminals as shown in
figure.
3. Apply the square wave of 1 kHz (having positive amplitude of three times peak
sinusoidal voltage) with proper duty cycle (say 70%) to the resistors R1 and R2 as
shown in figure.
4. Observe the output waveform on C.R.O.
5. Vary the duty cycle of the control voltage and see the effect on the output wavefrom.

OBSERVATION:

Plot the output waveform with reference to the input sinusoidal signal and control
voltage.

CONCLUSION:

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 12
 LAB 6
Input and Output Characteristics of a CE Configuration
AIM: Plot the input and output characteristics of a CE configuration and to determine its h-
parameters.

APPARATUS: Bread board,resistors, capacitors, transistor(BC 547), DC power supply(0-15

V), Signal generator(0-1Mhz), DMM, CRO.

THEORY:

Input characteristics:
Input current IB is plotted as a function of VBE and VCE. The VCE is held constant and
then IB is plotted versus VBE. The model graph shows that the input characteristics are those
of a forward biased PN junction. For a given value of VBE, IB reduced when higher VCE levels
are employed. This is because higher VCE produces greater depletion region penetration into
the base reducing the effective base region.
Output characteristics:
IC is plotted as a function of IB and VCE. First VCE is held constant and IC is plotted
versus IB. As IB is increased, IC increases linearly up to a certain level than IC gets saturated
and it does not increase with increase in IB. The output chacteristics curves are not exactly
horizontal because as VCE increases α increases and as a result β increases. So, for a
constant value of IB as VCE increases IC increases slightly.

CIRCUIT DIAGRAM:

Fig: CE configuration

THEORY:
Input characteristics:
Input current IB is plotted as a function of VBE and VCE. The VCE is held constant and
then IB is plotted versus VBE. The model graph shows that the input characteristics are those
of a forward biased PN junction. For a given value of VBE, IB reduced when higher VCE levels
are employed. This is because higher VCE produces greater depletion region penetration into
the base reducing the effective base region.
Output characteristics:

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 13
 IC is plotted as a function of IB and VCE. First VCE is held constant and IC is plotted
versus IB. As IB is increased, IC increases linearly up to a certain level than IC gets saturated
and it does not increase with increase in IB. The output chacteristics curves are not exactly
horizontal because as VCE increases α increases and as a result β increases. So, for a
constant value of IB as VCE increases IC increases slightly.

PROCEDURE:

Input characteristics:
1. Connect the circuit as per the circuit diagram.
2. Set VCE at 5V, vary VBB in steps of 1V to 20V and note down the corresponding IB and
VBE. Repeat the above procedure for 10V, 15V etc.
3. Plot the graph: VBE vs IB for a constant VCE.
4. Find the h-parameters:
a) hie = input impedance of a transistor = ΔVBE/ΔIB|VCE constant. = (VBE2-VBE1)/(IB2-IB1)
| VCE constant.
b) hre: reverse voltage gain { hre = ΔVBE/ΔVCE|IB constant = (VBE2-VBE1)/(VCE2-VCE1) |IB
constant.

Output characteristics:
1. Connect the circuit as per the circuit diagram.
2. Set IB at 20 µA, vary VCC in steps of 1V and note down the corresponding IC
and VCE. Repeat the above procedure for 40µA, 60µA, 80µA.
3. Plot the graph: VCE vs IC for a constant IB.
4. Find the h-parameters:
a) hfe = forward current gain { hfe = ΔIC/ΔIB| VCE constant = (IC2-IC1)/(IB2-IB1)| VCE
constant
b) hoe: output admittance { hoe = ΔIC/ΔVCE|IB constant = (IC2-IC1)/(VCE2-VCE1) |IB
constant.

OBSERVATION TABLE:

Input characteristics:

VCE(Volt) VBE(volt) IB(µA)

VCE1

VCE2

VCE3

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 14
 Output characteristics:

IB(µA) VCE(volt) IC(mA)

IB1

IB2

IB3

RESULT:

Parameters Practical readings

hfe

hie

hre

hoe

CONCLUSION:

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 15
MODEL GRAPH:

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 16
 LAB 7
Input and Output Characteristics of a CC Configuration
AIM: To Plot the input and output characteristics of a CC configuration and to determine its
h-parameters.

APPARATUS: Bread board, resistors, capacitors, transistor (BC 547), DC power supply (0-
15 V), Signal generator(0-1Mhz), DMM, CRO.

THEORY:

Input characteristics:
The common collector input characteristics as shown in model graph, are quite
different from either common-base or common emitter input characteristics. The difference is
due to the fact that input voltage (VBC) is largely determined by the VEC level.
VEC = VEB + VBC Or VEB = VEC – VBC
Increasing the level of (input voltage ) VBC with VEC held constant , reduces the level of VEB,
and thus reduces IB.
Output characteristics:
To obtain the output characteristics IE is plotted vs. VCE for several fixed values of IB.
Because IC is approximately equal to IE, the common-collector output and current gain
characteristics are practically identical to those of the common-emitter.

CIRCUIT DIAGRAM:

Fig: CC configuration

PROCEDURE:

Input characteristics:
1. Connect the circuit as per the circuit diagram.
2. Set VEC at -5V(say), vary VBB in steps of -1V to -20V and note down the
corresponding IB and VBC. Repeat the above procedure for VEC -10V, -15V etc.
3. Plot the graph: VBC vs IB for a constant VEC.
4. Find the h-parameters:
a) hic = input impedence of transistor = ΔVBC/ΔIB|VEC constant. = (VBC2-VBC1)/(IB2-IB1) |
VEC constant.

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 17
 b) hrc: reverse voltage gain { hrc = ΔVBC/ΔVEC|IB constant = (VBC2-VBC1)/(VCE2-VCE1) |IB
constant.
Output characteristics:
1. Connect the circuit as per the circuit diagram.
2. Set IB at 20 µA, vary VEE in steps of 1V and note down the corresponding IC and
VCE. Repeat the above procedure for 40µA, 60µA, 80µA.
3. Plot the graph: VEC vs. IC for a constant IB.
4. Find the h-parameters:
5. Find the h-parameters:
a) hfc = forward current gain { hfc = ΔIE/ΔIB| VEC constant = (IE2-IE1)/(IB2-IB1)| VCE
constant
b) hoe: output admittance { hoe = ΔIE/ΔVEC|IB constant = (IE2-IE1)/(VCE2-VCE1) |IB
constant.

OBSERVATION TABLE:

Input characteristics:

VEC(Volt) VBC(volt) IB(µA)

VEC1

VEC2

VEC3

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 18
 Output characteristics:

IB(µA) VEC(volt) IC(mA)

IB1

IB2

IB3

RESULT:

Parameters Practical readings

hfe

hie

hre

hoe

CONCLUSION:

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 19
MODEL GRAPH:

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 20
 LAB 8
Frequency Response of RC Coupled CE Amplifier
AIM: To plot the frequency response of RC coupled CE amplifier and to determine the cut-
off frequencies and bandwidth.

APPARATUS: Bread board, resistors, capacitors, transistor (2N2222A / BC547), D.C.

poser supply( 0-15 V),Signal Generator (0-1MHz), C.R.O.

THEORY:

One of the most important functions of electronic circuit is amplification. Almost all
electronic systems use amplifier. Generally people think that amplifier amplifies the signal of
all frequencies by the same amount. But real fact is that at some low and high
frequencies the gain provided by the amplifiers is less than the mid-band gain (maximum
gain in between lower cutoff frequency and higher cut-off frequency). At low frequency the
gain is reduced due to the coupling and bypass capacitors which are present in series state
as we look from input to output (in worst condition act as open circuit at very low
frequencies).At high frequency the gain is reduced due to the internal parasitic capacitance
which are virtually present in parallel as we look from input to output (in worst condition act
as short circuit at very high frequency). The frequencies, at lower side and higher side,
where the gain of the amplifier is 0.707 times of maximum mid-band gain is are
known as lower cut-off frequency (fL) and higher cut-off frequency respectively (fH). The
difference between fH and fL is known as bandwidth of the amplifier.

CIRCUIT DIAGRAM:

Fig: RC coupled single stage CE Amplifier.

PROCEDURE:
1. Connect the circuit on the bread board as shown in the figure
2. Set input signal ac voltage to 20 mV (peak to peak) using the signal
generator.

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 21
 3. Keeping the input voltage constant, vary the frequency from 0 Hz to 1 MHz in
regular steps and note down the corresponding output voltage.
4. Plot the frequency response: Gain (dB) vs. Frequency (Hz) on semilog
graph paper.
5. Calculate the bandwidth from the graph.

OBSERVATION TABLE:

vi (p-p) = 20mV

Frequency(Hz) vo(p-p) (V) Gain = vo/vi Gain(dB) = 20 log(vo/vi)

CONCLUSION:

LAB 9

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 22
 Drain and Transfer Characteristics of FET
AIM: To plot the drain for the given JFET and determine the drain resistance.

APPARATUS: FET (BFW10) , bread board, power supply, volt meter, variable resister,
resistors.

THEORY:

Like BJT, FET is also three terminal semiconductor device and basically as an amplifier but
unlike BJT, a FET is a unipolar device (i.e. the current is carried by only one type of charge
carrier either electrons and holes). FET has very high input impedance compared to BJT.
JFET can be a n channel FET and p channel FET. The important parameter of JFET are
defined below :-
Mutual Conductance g(m ) = Id / Vgs  Vgs is const.
Amplification factor µ = Vds / Vgs -- Id is constant
rd = gm * µ

CIRCUIT DIAGRAM:

Fig: CS configuration

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 23
PROCEDURE:
1. Note down the type number of JFET used.
2. Connect the circuit as shown in fig.
3. Fix VGS say zero, increase drain voltage VDS from zero and note down
corresponding values of ID.
4. Repeat the same procedure for different value of VGS
5. Plot the graph of ID  VGS for constant VGS.
6. Calculate mutual conductance gm = ID /VGS for constant VDS from graph.
7. Calculate Amplification factor µ= VDS /VGS for constant ID from graph.
8. Finally, rd =µ/gm.

OBSERVATION TABLE:

VGS = -------

Sr. No. VDS (Volts) ID (mA)

CHARACTERISTIC:

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 24
 CONCLUSION: Make your own conclusion.

LAB 10

Square Wave Response of CE Amplifier

AIM: To plot the of square wave response of CE amplifier and determine the rise time and
fall time.

APPARATUS: Transistor, Resistors, Capacitors, DC Power Supply, Function Generator,

CRO, Bread Board, Connecting Wires.

THEORY:

A sense for the frequency response of an amplifier can be determined by applying a square
wave signal to the amplifier and observing the output response. The shape of the output
waveform will revel whether the high frequency or low frequencies are properly amplified.

If the response of an amplifier to an applied square wave is an undistorted replica of

the input, the frequency response of the amplifier is obviously sufficient for the applied input.
If the output waveform is distorted at the horizontal edge of the output waveform then the
low frequencies are not being amplified properly and lower cut-off frequency is investigated
and if the output waveform is distorted at vertical edges of the output waveform then the high
frequencies are not being amplified properly.

The high frequency can be determined from the output waveform by carefully
measuring the rise time defined between 10% and 90% of the peak value.

CIRCUIT DIAGRAM:

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 25
 Fig: CE amplifier

PROCEDURE:
1. Implement the components on the bread board as per circuit diagram.
2. Apply square wave input of 50KHz. from the function generator.
3. Observe the output on the CRO.
4. Measure the rise time of output square waveform.
5. Also measure the amplitude at the trailing edge and leading edge of the out
put square waveform and calculate percentage of tilt.

OBSERVATION TABLE:

Plot the square wave response and determine the rise time and tilt from the graph.

CONCLUSION: Make your own conclusion.

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 26
 BC546/547/548/549/550

Datasheet of BJT BC 547

Symbol Parameter Value Units

VCBO Collector-Base Voltage : BC546 : BC547/550 : 80 50 30 VVV
BC548/549

VCEO Collector-Emitter Voltage : BC546 : BC547/550 : 65 45 30 VVV

BC548/549

VEBO Emitter-Base Voltage : BC546/547 : BC548/549/550 65 VV

IC Collector Current (DC) 100 mA

PC Collector Power Dissipation 500 mW
TJ Junction Temperature 150 °C
TSTG Storage Temperature -65 ~ 150 °C

Symbo Unit
Parameter Test Condition Min. Typ. Max.
l s
ICBO Collector Cut-off Current VCB=30V, IE=0 15 nA

hFE DC Current Gain VCE=5V, IC=2mA 110 800

VCE Collector-Emitter Saturation
IC=10mA, IB=0.5mA 90 250 mV
(sat) Voltage
IC=100mA, IB=5mA 200 600 mV
VBE Base-Emitter Saturation
IC=10mA, IB=0.5mA 700 mV
(sat) Voltage
IC=100mA, IB=5mA 900 mV
VBE (on) Base-Emitter On Voltage VCE=5V, IC=2mA VCE=5V, 580 660 700 mV
IC=10mA 720 mV
Current Gain Bandwidth VCE=5V, IC=10mA, 300 MHz
fT
Product f=100MHz
Cob Output Capacitance VCB=10V, IE=0, f=1MHz 3.5 6 pF

Cib Input Capacitance VEB=0.5V, IC=0, f=1MHz 9 pF

NF Noise Figure : BC546/547/548 VCE=5V, IC=200µA 2 10 dB

: BC549/550 : BC549 f=1KHz, RG=2KΩ VCE=5V, 1.2 44 dB

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 27
 • Low current (max. 100
mA) FEATURES PINNING
• Low voltage (max. 65
V).
PIN DESCRIPTION
1 emitter
2 base
APPLICATIONS
3 collecto
• General purpose switching and amplification. r

DESCRIPTION
NPN transistor in a TO-92; SOT54 plastic package.
PNP complements: BC556 and BC557.

hFE Classification

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 28
 THERMAL CHARACTERISTICS

SYMBO
PARAMETER CONDITIONS MIN. MAX. UNIT
L
VCBO collector-base voltage open emitter
1. Transistor mounted on an FR4 printed-circuit board.
BC546 − 80 V
BC547
CHARACTERISTICS − 50 V
VCEO
Tj=25 °C collector-emitter voltage
unless otherwise specified. open base
BC546 − 65 V
BC547 − 45 V
VEBO emitter-base voltage open collector
BC546 − 6 V
BC547 − 6 V
IC collector current (DC) − 100 mA
ICM peak collector current − 200 mA
LIMITING
IBM VALUES
peak base current − 200 mA
InPaccordance
tot total
with power dissipation
the Absolute Tamb
Maximum Rating System ≤ 134).
(IEC 25 °C; note 1 − 500 mW
Tstg storage temperature −65 +150 °C
Tj junction temperature − 150 °C
Tamb operating ambient temperature −65 +150 °C

SYMBOL PARAMETER CONDITIONS VALUE UNIT

thermal resistance from junction to
Rth j-a note 1 0.25 K/mW
ambient

Note
1. Transistor mounted on an FR4 printed-circuit board.

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 29
 MAX UNI
SYMBOL PARAMETER CONDITIONS MIN. TYP.
. T
ICBO collector cut-off current IE = 0; VCB =30V − − 15 nA
IE = 0; VCB = 30 V; Tj = 150
− − 5 µA
°C
IEBO emitter cut-off current IC = 0; VEB =5V − − 100 nA
hFE IC =10 µA; VCE =5V; see Figs
DC current gain BC546A 2, 3 and 4
− 90 −
BC546B; BC547B − 150 −
BC547C − 270 −
DC current gain IC = 2 mA; VCE =5V;
BC546A see Figs 2, 3 and 4 110 180 220
BC546B; BC547B 200 290 450
BC547C 420 520 800
BC547 110 − 800
BC546 110 − 450
VCEsat collector-emitter saturation IC = 10 mA; IB = 0.5 mA − 90 250 mV
voltage IC = 100 mA; IB =5mA − 200 600 mV
base-emitter saturation IC = 10 mA; IB = 0.5 mA; note
VBEsat − 700 − mV
voltage 1
IC = 100 mA; IB = 5 mA; note
− 900 − mV
1
VBE base-emitter voltage IC = 2 mA; VCE = 5 V; note 2 580 660 700 mV
IC = 10 mA; VCE =5V − − 770 mV
IE =ie = 0; VCB = 10 V; f = 1
Cc collector capacitance − 1.5 − pF
MHz
IC =ic = 0; VEB = 0.5 V; f = 1
Ce emitter capacitance − 11 − pF
MHz
IC = 10mA; VCE = 5 V; f = 100
fT transition frequency 100 − − MHz
MHz
F noise figure IC = 200 µA; VCE =5V; RS − 2 10 dB
=2kΩ; f = 1 kHz; B = 200 Hz

Notes
1. VBEsat decreases by about 1.7 mV/K with increasing
temperature.
2. VBE decreases by about 2 mV/K with increasing
temperature.

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h
FE
h
FE

200

400

100
200

50

0 10−2 10−1 1 10 102 103

IC (mA)

BC546A.

Fig.2 DC current gain; typical values.

300

200

100

0 10−2 10−1 1 10 102 103

IC (mA)
BC546B; BC547B.

Fig.3 DC current gain; typical values.

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