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#Explain concept of cross talk?

Switching of the signal in one net can interfere neigbouring net due to cross
coupling capacitance.This affect is known as cros talk. Cross talk may lead setup
or hold voilation
-- --------
#How can you overcome cross talk problem?
-Double spacing=>more spacing=>less capacitance=>less cross talk
-Multiple vias=>less resistance=>less RC delay
-Shielding=> constant cross coupling capacitance =>known value of crosstalk
-Buffer insertion=>boost the victim strength
#what is shielding? how it avoid avoids crosstalk problem?
High frequency noise (or glitch)is coupled to VSS (or VDD) since shilded layers are
connected to either VDD or VSS.
Coupling capacitance remains constant with VDD or VSS.
The IC Compiler tool implements clock shielding using nondefault routing rules. You
choose either to shield clock nets before routing signal nets or vice versa. The
of shielding clock nets before routing signal nets yields better shielding coverage
but can
cause more DRC violations during signal net routing compared to the methodology of
routing signal nets before shielding clock nets.
#how spacing h reducing crosstalk noise?
width is more=>more spacing between two conductors=>cross coupling capacitance is
less=>less cross talk
#Why double spacing and multiple vias are used related to clock?
Why clock?-- because it is the one signal which chages it state regularly and more
compared to any other signal. If any other signal switches fast then also we can
use double space.
Double spacing=>width is more=>capacitance is less=>less cross talk
Multiple vias=>resistance in parellel=>less resistance=>less RC delay
#where do you insert buffer to avoid crosstalk? how buffer insertion solve the
Buffer increase victims signal strength; buffers break the net length=>victims are
more tolerant to coupled signal from aggressor
#Difference between Chip Design and Block level design?
Chip design has I/O pads; block design has pins.
Chip design uses all metal layes available; block design may not use all metal
Chip is generally rectangular in shape; blocks can be rectangular, rectilinear.
Chip design requires several packaging; block design ends in a macro.
#What are the ways to place macros in a full chip design?
First check flylines i.e. check net connections from macro to macro and macro to
standard cells.
If there is more connection from macro to macro place those macros nearer to each
other preferably nearer to core boundaries.
If input pin is connected to macro better to place nearer to that pin or pad.
If macro has more connection to standard cells spread the macros inside core.
Avoid criscross placement of macros.
Use soft or hard blockages to guide placement engine
#what are the differences between Hierarchical Design and flat design?
Hierarchial design has blocks, subblocks in an hierarchy; Flattened design has no
subblocks and it has only leaf cells.
Hierarchical design takes more run time; Flattened design takes less run time.
#Why 500 MHz clock design is complex than 48Mhz design?
500 MHz; because it is more constrained (i.e.lesser clock period) than 48 MHz
#What all tools used in physical verification?
Herculis from Synopsys, Caliber from Mentor Graphics.
#what are the inputs you will give in physical verification

#how will you solve the congestion between two macros?

Provide soft or hard blockage
#what all parameters you will consider while estimating die size?
By checking the total area of the design you can decide die size.
#What is each macro size and number of standard cell count?
#Depends on your design.
#What are the input needs for your design?
For synthesis: RTL, Technology library, Standard cell library, Constraints
For Physical design: Netlist, Technology library, Constraints, Standard cell
#What does SDC (Synopsys design contraint) file contains?
Clock definitions
Timing exception-multicycle path, false path
Input and Output delays
#how will give Clock definitions ?
#what are timing Timing exception, how will you constraint them?
#what is Input and Output delays, what are prime time commands for it?
#How did you do power planning?
#Explain, how will you find number of power pad and IO power pads?
#How the number of power straps calculate?
Get the total core power consumption; get the metal layer current density value
from the tech file; Divide total power by number sides of the chip; Divide the
obtained value from the current density to get core power ring width. Then
calculate number of straps using some more equations. Will be explained in detail
#How to find total power of chip, What are the problems you can faced with respect
to timing?
Total chip power=standard cell power consumption,Macro power consumption pad power
Prelayout: Setup, Max transition, max capacitance
Post layout: Hold
#what is setup and hold problem, how will you solve it?
#which is preferable layer for clock routing and why?
Next lower layer to the top two metal layers(global routing layers). Because it has
less resistance hence less RC delay.
#what do you mean by IR drop problem, how will you overcome by this problem?
Increase power metal layer width.
Go for higher metal layer.
Spread macros or standard cells.
Provide more straps.
#what is antenna effect, how does it impact the and how would you resolve antennae
effect problem?
Increased net length can accumulate more charges while manufacturing of the device
due to ionisation process. If this net is connected to gate of the MOSFET it can
damage dielectric property of the gate and gate may conduct causing damage to the
MOSFET. This is antenna problem.
Decrease the length of the net by providing more vias and layer jumping.
Insert antenna diode.
#How are the PVT conditions? Describe using graph?
P increase->delay increase
P decrease->delay decrease
V increase->delay decrease
V decrease->delay increase
T increase->delay increase
T decrease->delay decrease
#Describe the physical design flow?

#what all the and inputs and outputs for each step of physical design?
#What is cell delay and net delay, how will you reduce this delays?
Gate delay
Transistors within a gate take a finite time to switch. This means that a change on
the input of a gate takes a finite time to cause a change on the output.[Magma]
Gate delay =function of(i/p transition time, Cnet+Cpin).
Cell delay is also same as Gate delay.

Cell delay
For any gate it is measured between 50% of input transition to the corresponding
50% of output transition.
Intrinsic delay
Intrinsic delay is the delay internal to the gate. Input pin of the cell to output
pin of the cell.
It is defined as the delay between an input and output pair of a cell, when a near
zero slew is applied to the input pin and the output does not see any load
condition.It is predominantly caused by the internal capacitance associated with
its transistor.
This delay is largely independent of the size of the transistors forming the gate
because increasing size of transistors increase internal capacitors.

Net Delay (or wire delay)

The difference between the time a signal is first applied to the net and the time
it reaches other devices connected to that net.
It is due to the finite resistance and capacitance of the net.It is also known as
wire delay.
Wire delay =fn(Rnet , Cnet+Cpin)

#What are the different timing delay models available?

Linear Delay Model (LDM)
Non Linear Delay Model (NLDM)

#What is wire load model (WLM)?

Wire load model is NLDM which has estimated R and C of the net.

#Why higher metal layers are preferred for power?

Because it has less resistance and hence leads to less IR drop

#What do you mean by logic optimization techniques, how it will work?

a part of logic synthesis in electronics, is the process of finding an equivalent
representation of the specified logic circuit under one or more specified
constraints. Generally the circuit is constrained to minimum chip area meeting a
prespecified delay.
Buffer insertion
Buffer relocation
Dummy buffer placement

#what is slack, how will you calculate slack?

#what are the parameters on which slack depends on?
#What do you mean by of negative slack, how will u make it positive?
#What is EM and it effects?
Due to high current flow in the metal atoms of the metal can displaced from its
origial place. When it happens in larger amount the metal can open or bulging of
metal layer can happen. This effect is known as Electro Migration.
Affects: Either short or open of the signal line or power line.
#What are types of routing ?
Global Routing
Track Assignment
Detail Routing
#What do you mean by clock latency? what are the types of clock latecies?
Source Latency
It is known as source latency also. It is defined as “the delay from the clock
origin point to the clock definition point in the design”.
Delay from clock source to beginning of clock tree (i.e. clock definition point).
The time a clock signal takes to propagate from its ideal waveform origin point to
the clock definition point in the design.
Network latency
It is also known as Insertion delay or Network latency. It is defined as “the delay
from the clock definition point to the clock pin of the register”.
The time clock signal (rise or fall) takes to propagate from the clock definition
point to a register clock pin.
#What is track assignment in routing stage?
Second stage of the routing wherein particular metal tracks (or layers) are
assigned to the signal nets.
Physical Design Interview Question Part 2
#How many blocks/chips designed in your total years of Experience?
#What is the latest project you finished? Was it block/full-chip?
#What is the design application?
#Input is RTL or gate level netlist?
#Explain Netlist(or RTL)-gdsii flow?
#What are the input needs for your design?
#In which field are you interested?
#What is the most challenging task you handled?
#What is the most challenging job in P&R flow?
#What parameters (or aspects) differentiate Chip Design and Block level design?
#List down difference between a flat and hierarchical design?
#What is the difference between soft macro and hard macro?
#What are the challenges seen as technology shrinks?
#What scan techniques being used?
#Experience with timing closure & congestion issues?
#Any experience with ECO (functional or timing ECO).
#what are issues you face during tapeout time?
#If you have shifted from one tool to another one, how long did it take to ramp up
#on the new tool?
#What is the difference between a latch and a flip-flop?
#what all the parameters on which clock frequency depends in design?
#Define threshold voltage?
#How do you size NMOS and PMOS transistors to increase the threshold voltage?
#how threshold voltage is dependent on temperature?
#What is the effect of gate voltage on mobility?
#What is the effect of temperature on mobility?
#Design a circuit to divide input frequency by 2?
Physical Design Interview Question Part 3
1. How many blocks/chips designed in your total years of Experience?
2. What is the latest project you finished? Was it block level implementation or
full-chip implementation?
3. What is the design application?
4. Input is RTL or gate level netlist?
5. Explain Netlist(or RTL)-gdsii flow?
6. What are the input needs for your design?
7. In which field are you interested?
8. What is the most challenging task you handled?
9. What are the challenges you faced in P&R flow?
10. What parameters (or aspects) differentiate Chip Design and Block level design?
12. Differentiate between a Hierarchical Design and flat design?
13. What is the difference between soft macro and hard macro?
14. What are Ips?
15. What are the challenges you will see in lower technology?
16. What scan techniques being used?
17. Experience with timing closure & congestion issues?
18. Any experience with ECO (functional or timing ECO).
19. Towards the end of the project, what are some of the issues that can pop up ,
20. how can they be fixed?
21. If you have shifted from one tool to another one, how long did it take to ramp
up on the new tool?
22. What is the difference between a latch and a flip-flop?
23. On what basis we decide the clock frequency in any design?
24. Define threshold voltage?
25. How does the size PMOS & NMOS transistors increases the threshold voltage?
26. What is the effect of temperature on threshold voltage?
27. What is the effect of gate voltage on mobility?
28. What is the effect of temperature on mobility?
29. If we invert o/p of D flip-flop in the ip how does it will behave?
30. Design a circuit to divide input frequency by 2?
31. What is the maximum drive strength of standard buffers and inverters are
available in your design?
32. Why we increase the size and strength of inverters in buffer design? What will
happen if you user inverter or buffer of maximum strength and size?
33. What does lef and lib file contains?
34. What is generally in the x axis and y axis and what is linear line in any
35. What are the high speed and low speed cells?
36. What is the exact meaning of a capacitance?
Physical design Interview Questions Part 6
Below are interview questions asked by one of the product based company
1. Have you ever worked on on lower nodes, like 14nm or 10nm?
2. what is difference between bulk MOS and FINFET?
3. How conduction takes place in MOS and FINFET transistors?
4. Is Antennae violation is functional failure or Manufacturing error? how can you
fix antennae violation
5. What is short circuit current, and how will you overcome this problem?
6. What is difference between static IR drop and dynamic IR drop?
7. On what all parameters does IR drop and Dynamic IR drop depends on?
8. Have you worked on Physical Verification?
9. What is soft checks in Physical verification?
10. How soft checks different from ERC?
11. What is difference between ERC and PERC?
12. What all the Physical verification test you perform during each stage of
Physical design?
13. what XOR checks will do?
14. have you ever worked in STA?
15. have you involved in top level timing or your role limited to block level
16. How OCV (onchip variation diffrent from ) AOCV (advance on chip variation)?
17 what is difference between AOCV and POCV?
18 how timing related with PTC (postive temperature coefficient) and NTC (negative
temperature coefficient)
19 how derates varies in ocv, aocv and pocv?
20. what all parameter of uncertainty value in STA depends upon pre cts and post
Physical Design Interview Part 7
• Tell me about yourself in brief
• Inputs to PNR
• Do you have knowledge on synthesis
• What are the validations and sanity checks you do on the outputs received from
synthesis team
• Which file will you need to check if you see black box in the screen
• Which file you need to check if you see any floating pins and whom should you
report in such case
• What does .tf file, .db file, .sdc file, .spef file .v files include
• What is floor plan and what is done as part of floor plan
• How do you fix placement of RAMs
• What is utilization factor and Area
• What is fly line analysis
• How do you decide the spacing between the macros and standard cells
• What are tie cells and can the size of array of tie cells be either increased or
decreased? –No
• Which layers are preferred for power routing and why?
• Which is preferred to be the outer most layer or top layer
• What is the UF in floor plan
• What is the skew achieved in your project and what is the allowed skew
• What is local skew and global skew difference
• What are the tools used for PNR
• What is high fan out synthesis
• What is placement and what do we do in this step
• What is NLDM
• What is congestion and timing closure
• What special physical cells are used in your project
• Purpose of power domains, level shifter cells, isolation cells, Always on cell
• Where do we use Always On buffers
• How is drive strength and delay relation
• What is inversion temperature
• How is delay and temperature relation
• How is threshold voltage and temperature variations related
• What happens when you do congestion driven placement
• Where are the buffers placed? What is the functionality of buffers
• How do buffers speed up the signal in data or in clock even if it adds delay to
the path
• What is set up and hold violation
• What are the ways to fix the set up violation
• Ways to fix hold violation
• What is STA and which tool is being used for STA
• What are the optimizations done in placement stage
• What are the power domains in your project
• What is switchable power domain
Physical design Interview Question part 8
• What are well tap cells, what are end cap cells and its usage
• What are the inputs to CTS
• What sanity checks are to be done in SDC file
• What is de-rating
• What is clock skewing and what is a useful skew
• how many clocks are used in your project
• what is the maximum frequency
• what is latency
• what is clock generation point, clock distribution point, clock end point
• why is the setup check in next cycle and hold checked at same time
• what is the width and spacing rules for clocks
• what are the NDR for clocks
• what are NDR and DRC checks done at each stage of project
• what is OCV, antenna violation and what are measures taken
• what is antenna ratio
• what is RC extraction and when do you do this
• if you have congestion after CTS and you are not allowed to change the placement
how do you proceed
• does set up fixes cause hold issues and vice versa
• what is slack
• what happens if there is any floating pin and it is left without any care
• what is electro migration
• what is signal integrity and cross talk
• what are the preventions taken at each stage to resolve cross talk issue
• what is shielding
• what is Physical verification, formal verification
• what are the DRC checks made in project
• what is LVS what information is obtained from LVS
• what are the signoff checks and which tools are used for it
• what are the inputs to STAR RC and prime time
• what is cloning
• what happens if any of the input files are missed to IC compiler
• what is RTL , gate level differences
• What does synthesis team do?
• What are libraries needed for tool, what is difference between logic and physical
• What is a UPF file, is it used in your project
• What ae filler cells
• What are ECOs , how many Eco are implemented
• What ae the DRC fixed
• What is low power design
• What is clock and power gating
#How to fix max trans violation?
There are several ways to fix the transition time violations.
1) Increase the driver size.
2) Break the nets in the case of long nets.
3) Break the large fanout by duplicating drivers or with buffering.
4) Change the VT if option available(changing drivers from hvt to svt or lvt).
5) Reduce the load by downsizing the cells(special cases) after the looking the
timing impact on the design.
6) Change the Load to hvt because hvt has higher lib limit.
Questions Related to Power Planning, IR drop and Low power

what is powerplanning, How you use to do i. Power estimation ii. power pads
estimation (core & IO) iii. core ring width calculation iv. EMIR v. SSO
What are preroutes in your design?
How to power route multiVDD design?
Power domains, partitioning, power routing for multi domains, placement of power
What are the various views of a macro or a cell?
What is the macro placement guidelines?
What all checks will you perform after Floor planning?
What if you allow the cell to be placed in the halo region around macro? Can you
do that? Why?
If you import a LEF for a macro and you find out that the macro pins are moved from
boundary to center, what will be your approach?
How did you define your power structure for full chip?
How will you start power planning for your design?
EMIR & low power:
How power is related with clock frequency?
Can we achieve lower power with more than one voltage supply?
Different low power techniques?
methods of leakage reduction?
What are the vectors of dynamic power?
How can you reduce dynamic power?
If you have both IR drop and congestion how will you fix it?
Is increasing power line width and providing more number of straps are the only
solution to IR drop?
Why higher metal layers are preferred for Vdd and Vss?
What is IR drop? How it affects timing?
What is EM and it effects? how to resolve EM?
Techniques to avoid IR problems? Dynamic & Static
Do we have inactive blocks that we can shut off to reduce leakage power?
What are Retention registers?
Give the various techniques you know to minimize power consumption for CMOS logic?
Give the expression for CMOS switching power dissipation?
List out the factors affecting power consumption on a chip?
Any custom routes of analog/power? What were the requirements of custom routes?
Any experience in low power techniques?
Any experience with multi Vt libraries?
What is total Static & dynamic power consumption in your design?
Questions Related to Clock Tree Synthesis

What is the goal of CTS?

What are clock trees?
What are clock tree types?
How many clocks were there in this project?
How will you use to take care of all clocks used in your project?
Are they come from seperate external resources or PLL?
How will you synthesize clock tree?
Why double spacing and multiple vias are used related to clock?
In which layer do you prefer for clock routing and why?
What is latency? Give the types?
Is it possible to have a zero skew in the design?
What are the difference between High Fanout synthesis and Clock tree synthesis?
Why CTS not done in synthesis?
why we prefer clock buffer during cts, how they are different with normal buffer?
what is the target clock skew, clock latency target in your project?
Does the design have a PLL? How many clocks generated from PLL.
Are there derived clocks or complex clock generation circuitry?
what do you mean by gated clocks, how many gated clocks were there in your project?
Is the clock gate used for timing or power?
Available cells for clock tree?
Are there any special clock repeaters in the library?
Are there any EM, slew or capacitance limits on these repeaters?
Will the clock tree be shielded? If so, what are the shielding requirements?
why buffers having balanced rise and fall delays are preferred in CTS
Define Clock Skew, Negative Clock Skew, Positive Clock Skew?
Explain the concept clock domains crossing, how will you synchronize clock in that
What is useful-skew mean?
What is skew, how will you minimize it, if you dont minimize what all problem you
can face because of it?
Any special clock planning for block.
How do you account for clock tree insertion for scan?
Any clock generation block?
Have you used shielding rules for clock nets in your design?
How did you performed CTS for your block? How will you fix the clock latency