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REGN
PGND
PVCC
•
BTST
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2007–2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
bq24751A
SLUS756C – SEPTEMBER 2007 – REVISED MARCH 2009............................................................................................................................................. www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
The bq24751A controls external switches to prevent battery discharge back to the input, connect the adapter to
the system, and to connect the battery to the system using 6-V gate drives for better system efficiency. For
maximum system safety, inrush-power limiting provides instantaneous response to high input voltage multiplied
by current. This AC Over-Power protection (ACOP) feature limits the input-switch power to the programmed level
on the ACOP pin, and latches off if the high-power condition persists to prevent overheating.
The bq24751A features Dynamic Power Management (DPM) and input power limiting. These features reduce
battery charge current when the input power limit is reached to avoid overloading the AC adapter when supplying
the load and the battery charger simultaneously. A highly-accurate current-sense amplifier enables precise
measurement of input current from the AC adapter to monitor the overall system power.
ADAPTER + SYSTEM
R10 RAC C6 C7
ADAPTER - 2Ω P P 0.010 Ω 10 µF 10 µF
Q1 (ACFET) Q2 (ACFET)
C1 SI4435 SI4435
2.2 µF
C2 C3
0.1 µF ACN PVCC
0.1 µF
C8
ACP
0.1 µF
ACDRV
BATDRV Q3(BATFET)
R1
ACDET SI4435
R2 P
432 kΩ HIDRV
Q4
1% 66.5 kΩ AGND FDS6680A
VREF
1% N
R5 L1 RSR
10 kΩ bq24751A PH
8.2 µH 0.010 Ω
BTST PACK+
ACGOOD ACGOOD
R3 D1 C9 C12
OVPSET C11 PACK-
BAT54 0.1 µF 10 µF
422 kΩ R4
REGN 10 µF
1% 71 kΩ C10
1% 1 µF
C13
SRSET 0.1 µF
DAC LODRV
Q5
ACSET FDS6680A C14
N 0.1 µF
VREF PGND
C4
HOST 1 µF SRP
LEARN SRN
GPIO CELLS
BAT
CHGEN C15
ACOP 0.1 µF
VDAC
C16
DAC 0.47 µF
VADJ
ADAPTER + SYSTEM
R10 RAC C6 C7
ADAPTER - 2Ω P P 0.010 Ω 10 µF 10 µF
Q1 (ACFET) Q2 (ACFET)
C1 SI4435 SI4435
2.2 µF
C2 C3
0.1 µF ACN PVCC
0.1 µF
C8
ACP
0.1 µF
ACDRV
BATDRV Q3(BATFET)
R1
ACDET SI4435
R2 P
432 kΩ HIDRV
Q4
1% 66.5 kΩ AGND FDS6680A
VREF
1% N
R5 L1 RSR
10 kΩ bq24751A PH
8.2 µH 0.010 Ω
BTST PACK+
ACGOOD ACGOOD
R3 D1 C9 C12
OVPSET 0.1 µF C11 PACK-
VREF BAT54 10 µF
422 kΩ R4
REGN 10 µF
1% 71 kΩ R7 C10
VREF 100 kΩ 1 µF
1% R11 C13
R8 SRSET 0.1 µF
100 kΩ 43 kΩ LODRV
Q5
ACSET FDS6680A C14
R9 N 0.1 µF
66.5 kΩ VREF PGND
C4
HOST 1 µF SRP
LEARN SRN
GPIO CELLS
BAT
CHGEN C15
VREF ACOP 0.1 µF
VDAC
REGN C16
VADJ
0.47 µF
ORDERING INFORMATION
ORDERING NUMBER
PART NUMBER PACKAGE QUANTITY
(Tape and Reel)
bq24751ARHDR 3000
bq24751A 28-PIN 5 x 5 mm QFN
bq24751ARHDT 250
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
(2) This data is based on using the JEDEC High-K board and the exposed die pad is connected to a Cu pad on the board. This is
connected to the ground plane by a 2x3 via matrix.
VALUE UNIT
PVCC, ACP, ACN, SRP, SRN, BAT, BATDRV, ACDRV –0.3 to 30
PH –1 to 30
REGN, LODRV, VREF, VDAC, VADJ, ACSET, SRSET, ACDET, ACOP,
Voltage range –0.3 to 7
CHGEN, CELLS, STAT, ACGOOD, LEARN, OVPSET V
VREF, IADAPT –0.3 to 3.6
BTST, HIDRV with respect to AGND and PGND –0.3 to 36
Maximum difference voltage ACP–ACN, SRP–SRN, AGND–PGND –0.5 to 0.5
Junction temperature range –40 to 155
°C
Storage temperature range –55 to 155
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging
Section of the data book for thermal limitations and considerations of packages.
ELECTRICAL CHARACTERISTICS
7.0 V ≤ VPVCC ≤ 24 V, 0°C < TJ < +125°C, typical values are at TA = 25°C, with respect to AGND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OPERATING CONDITIONS
VPVCC_OP PVCC Input voltage operating range 5.0 24.0 V
CHARGE VOLTAGE REGULATION
VBAT_REG_RNG BAT voltage regulation range 4-4.512 V per cell, times 2,3,4 cells 8 18.04 V
8
VVDAC_OP VDAC reference voltage range 2.6 3.6 V
VADJ_OP VADJ voltage range 0 REGN V
8 V, 8.4 V, 9.024 V –0.5 0.5
Charge voltage regulation accuracy 12 V, 12.6 V, 13.536 V –0.5 0.5 %
16 V, 16.8 V, 18.048 V –0.5 0.5
Charge voltage regulation set to VADJ connected to REGN, 8.4 V, 12.6 V, –0.5 0.5
%
default to 4.2 V per cell 16.8 V
CHARGE CURRENT REGULATION
VIREG_CHG Charge current regulation differential VIREG_CHG = VSRP – VSRN 0 100 mV
voltage range
VSRSET_OP SRSET voltage range 0 VDAC V
VIREG_CHG = 40–100 mV –3 3
VIREG_CHG = 20 mV –5 5
Charge current regulation accuracy %
VIREG_CHG = 5 mV –25 25
VIREG_CHG = 1.5 mV (VBAT>4V) –33 33
TYPICAL CHARATERISTICS
(1) Test results based on Figure 2 application schematic. VIN = 20 V, VBAT = 3-cell LiIon, ICHG = 3 A, IADAPTER_LIMIT = 4 A,
TA = 25°C, unless otherwise specified.
VREF LOAD AND LINE REGULATION REGN LOAD AND LINE REGULATION
vs vs
Load Current LOAD CURRENT
0.50 0
0.40
-0.50
Regulation Error - %
Regulation Error - %
0.30
-1
PVCC = 10 V
0.20
-1.50
0.10 PVCC = 10 V
-2
0
PVCC = 20 V
-0.10 -2.50
PVCC = 20 V
-0.20 -3
0 10 20 30 40 50 0 10 20 30 40 50 60 70 80
VREF - Load Current - mA REGN - Load Current - mA
Figure 3. Figure 4.
17.6
7
17.4
6
17.2
5
17
4
16.8
3
16.6
16.4 2
16.2 1
16 0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
VADJ/VDAC Ratio SRSET/VDAC Ratio
Figure 5. Figure 6.
8
0.1
Regulation Error - %
6
0
5
4
3
-0.1
2
1
-0.2
0 0 2000 4000 6000 8000
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Charge Current - mA
ACSET/VDAC Ratio
Figure 7. Figure 8.
0.04
Regulation Error - %
4-Cell, no load -2
0.02 -3
0 -4
-0.02 -5
-6
-0.04
-7
-0.06
-8
-0.08 -9
-0.10 -10
16.5 17 17.5 18 18.5 19 0 2 4 6 8
V(BAT) - Setpoint - V I(CHRG) - Setpoint - A
INPUT CURRENT REGULATION (DPM) ACCURACY VIADAPT INPUT CURRENT SENSE AMPLIFIER ACCURACY
10 5
9 ACSET Varied
8 0
7
VI = 20 V, CHG = EN
Regulation Error - %
6 4-Cell, VBAT = 16 V -5
Percent Error
5 VI = 20 V, CHG = DIS
-10
4
3
2 -15
1
0 -20
Iadapt Amplifier Gain
-1
-2 -25
0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 8 9 10
Input Current Regulation Setpoint - A I(ACPWR) - A
System Current
Charge Current
2
0
0 1 2 3 4
System Current - A
Figure 13. Figure 14.
Vreg = 12.6 V
90 Vreg = 8.4 V
Efficiency - %
3
2
80
0
0 2 4 6 8 10 12 14 16 18 70
0 2000 4000 6000 8000
Battery Voltage - V
Battery Charge Current - mA
Figure 15. Figure 16.
2 V/div
Ch1
VACDET
20 V/div
Ch2
VBATDRV
5 V/div
Ch3
VACDRV
5 V/div
VACGOOD
Ch4
VBAT
Ch2
VSYS
VACDRV
Ch3
10 V/div
Ch4
VBATDRV
SYSTEM SELECTOR ON ADAPTER REMOVAL WITH SYSTEM SELECTOR LEARN TURN-ON WITH
390 µF SYS-TO-PGND SYSTEM CAPACITOR 390 µF SYS-TO-PGND SYSTEM CAPACITOR
10 V/div 20 V/div 20 V/div
Ch1
VBAT
Ch2
VSYS
Ch3
VACDRV
10 V/div
Ch4
VBATDRV
t − Time = 2 ms/div
Figure 21. Figure 22.
7.2 V
Ch1
Ch1
VACPWR
Ch2
VACDRV
Ch3
VACGOOD
IL
5 A/div
Ch4
VIN
Ch1
Ch1
VSYS
5 A/div 500 mV/div 5 V/div
VBAT
Ch4
Ch2
VACDRV
2 A/div
Ch3
VACOP
Ch4
IL
IIN
Ch3
10 V/div
VHIDRV
1.8 V
Ch1
Ch1
Ch1
VCHGEN
1 V/div
Ch2
VBAT
VPH
20 V/div
Ch2
Ch4
VPH
VLDDRV
Ch3
2 A/div
IL
Ch3
IBAT
SYNCHRONOUS TO NONSYNCHRONOUS TRANSITION NEAR 100% DUTY CYCLE BOOTSTRAP RECHARGE PULSE
20 V/div 20 V/div
Ch1
VPH
VPH
10 V/div
Ch2
Ch2
VHIDRV
VLODRV
5 V/div
Ch4
2 A/div 5 V/div
Ch3
VLODRV
2 A/div
IL
Ch3
Ch4
IL
Ch1
Ch4
VPH
VBAT
20 V/div
VHIDRV
Ch2
5 V/div
2 A/div
Ch3
Ch3
VLODRV
IL
5 A/div
Ch4
IL
20 V/div
Ch1
VPH
20 V/div
VHIDRV
Ch2
5 V/div
Ch3
VLODRV
2 A/div
Ch4
IL
t − Time = 1 ms/div
Figure 33.
700ms
0.6 V – ENA_BIAS
ACGOOD
+ 2.4 V – ADAPTER DETECTED
Delay Rising
ACDET +
VREF
ENA_SRC Isrc=K*V(PVCC-ACP) PVCC +
PVCC-6V
K=18 µA/V PVCC-6V PVCC
BAT – LDO
+
_
ACOP
+ ACOPDET 185 mV PVCC-BAT
– PVCC
5 µA ACOP_LATCH ENA_BIAS
+ S Q
ENA_SNK 2V –
ACDET Q
R SYSTEM POWER ACDRV
PVCC_UVLO SELECTOR
LOGIC
CHGEN PVCC-6V
ACN
ENA_BIAS
VREF 3.3V LDO EAI EAO BATDRV
PVCC
ACN-6V
ACP LEARN
FBO ACFET_ON
+ V(ACP-ACN)
20x – IIN_ER
–
IIN_REG + COMP
ERROR
ACN AMPLIFIER BTST
CHGEN
+
V(ACN-BAT) -
–
+
_
+
285 mV 1V BAT_OVP
BAT – BAT_ER LEVEL HIDRV
SHIFTER
CHG_OCP
VBAT_REG +
20 µA
ACOV
ACOP
SRP PH
V(ACN-BAT) DC-DC
3.5 mA CONVERTER
+ V(SRP-SRN) BAT_SHORT PWM LOGIC
20x – ICH_ER
–
IBAT_ REG + UVLO
20 µA PVCC 6V LDO REGN
SRN
3.5 mA
SYNCH ENA_BIAS
CHGEN
CHRG_ON
REFRESH LODRV
BTST – CBTST
+
V(SRP-SRN) + SYNCH 4V _+
– PH
ACSET + PGND
13 mV –
IC Tj + TSHUT
155°C –
ACP + V(IADAPT)
SRSET 20x IADAPT
BAT ACN –
+ BAT_OVP
VBATSET VBAT_REG
IBATSET 104% X VBAT_REG –
IINSET IBAT_REG
RATIO
VADJ PROGRAM V(SRP-SRN)
IIN_REG + CHG_OCP
145% X IBAT_REG –
VDAC +
ACOV
– BAT – BAT_SHORT
OVPSET 3.1 V +
–
+
2.9 V/cell +
–
CELLS
PVCC – UVLO
+
4V +
AGND –
bq24751A
DETAILED DESCRIPTION
The per-cell charge-termination voltage is a function of the battery chemistry. Consult the battery manufacturer to
determine this voltage.
The BAT pin is used to sense the battery voltage for voltage regulation and should be connected as close to the
battery as possible, or directly on the output capacitor. A 0.1-µF ceramic capacitor from BAT to AGND is
recommended to be as close to the BAT pin as possible to decouple high-frequency noise.
V 0.10
I ADAPTER + ACSET
VVDAC R AC (3)
The input voltage range of ACSET is between 0 and VDAC, up to 3.6 V.
The ACP and ACN pins are used to sense RAC with a default value of 10 mΩ. However, resistors of other values
can also be used. A larger sense-resistor value yields a larger sense voltage, and a higher regulation accuracy.
However, this is at the expense of a higher conduction loss.
discharge from the battery to the adapter when it is turned off. The p-channel FET with the drain connected to
the adapter input provides reverse battery discharge protection when off; and also minimizes system power
dissipation, with its low Rdson, compared to a Schottky diode. The other p-channel FET connected to ACP
separates the battery from the adapter, and provides both ACOC current limit and ACOP power limit to the
system. The BATDRV signal controls a p-channel power MOSFET placed between BAT and the system.
When the adapter is not detected, the ACDRV output is pulled to PVCC to turn off the ACFET, disconnecting the
adapter from system. BATDRV stays at ACN – 6 V to connect the battery to system.
At 700 ms after adapter is detected, the system begins to switch from the battery to the adapter. The PVCC
voltage must be 185 mV above BAT to enable the switching. The break-before-make logic turns off both ACFET
and BATFET for 10µs before ACFET turns on. This isolates the battery from shoot-through current or any large
discharging current. The BATDRV output is pulled up to ACN and the ACDRV pin is set to PVCC – 6 V by an
internal regulator to turn on the p-channel ACFET, connecting the adapter to the system.
When the adapter is removed, the system waits till ACN drops back to within 285 mV above BAT to switch from
the adapter back to the battery. The break-before-make logic ensures a 10-µs dead time. The ACDRV output is
pulled up to PVCC and the BATDRV pin is set to ACN – 6 V by an internal regulator to turn on the p-channel
BATFET, connecting the battery to the system.
Asymmetrical gate drive for the ACDRV and BATDRV drivers provides fast turn-off and slow turn-on of the
ACFET and BATFET to help the break-before-make logic and to allow a soft-start at turn-on of either FET. The
soft-start time can be further increased, by putting a capacitor from gate to source of the p-channel power
MOSFETs.
Converter Operation
The synchronous-buck PWM converter uses a fixed-frequency (300 kHz) voltage mode with a feed-forward
control scheme. A Type-III compensation network allows the use of ceramic capacitors at the output of the
converter. The compensation input stage is internally connected between the feedback output (FBO) and the
error-amplifier input (EAI). The feedback compensation stage is connected between the error amplifier input
(EAI) and error amplifier output (EAO). The LC output filter is selected for a nominal resonant frequency of 8
kHz–12.5 kHz.
fo + 1
The resonant frequency, fo, is given by: 2p ǸLoC o where (from Figure 1 schematic)
• CO = C11 + C12
• LO = L1
An internal sawtooth ramp is compared to the internal EAO error-control signal to vary the duty cycle of the
converter. The ramp height is one-fifteenth of the input adapter voltage, making it always directly proportional to
the input adapter voltage. This cancels out any loop-gain variation due to a change in input voltage, and
simplifies the loop compensation. The ramp is offset by 200 mV in order to allow a 0% duty cycle when the EAO
signal is below the ramp. The EAO signal is also allowed to exceed the sawtooth ramp signal in order to operate
Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s) :bq24751A
bq24751A
SLUS756C – SEPTEMBER 2007 – REVISED MARCH 2009............................................................................................................................................. www.ti.com
with a 100% duty-cycle PWM request. Internal gate-drive logic allows a 99.98% duty-cycle while ensuring that
the N-channel upper device always has enough voltage to stay fully on. If the BTST-to-PH voltage falls below 4 V
for more than 3 cycles, the high-side N-channel power MOSFET is turned off and the low-side N-channel power
MOSFET is turned on to pull the PH node down and recharge the BTST capacitor. Then the high-side driver
returns to 100% duty-cycle operation until the (BTST-PH) voltage is detected falling low again due to leakage
current discharging the BTST capacitor below 4 V, and the reset pulse is reissued.
The 300-kHz fixed-frequency oscillator tightly controls the switching frequency under all conditions of input
voltage, battery voltage, charge current, and temperature. This simplifies output-filter design, and keeps it out of
the audible noise region. The charge-current sense resistor RSR should be designed with at least half or more of
the total output capacitance placed before the sense resistor, contacting both sense resistor and the output
inductor; and the other half, or remaining capacitance placed after the sense resistor. The output capacitance
should be divided and placed on both sides of the charge-current sense resistor. A ratio of 50:50 percent gives
the best performance; but the node in which the output inductor and sense resistor connect should have a
minimum of 50% of the total capacitance. This capacitance provides sufficient filtering to remove the switching
noise and give better current-sense accuracy. The Type-III compensation provides phase boost near the
cross-over frequency, giving sufficient phase margin.
IRIPPLE_MAX
£ ISYN £ IRIPPLE_ MAX
2
and
VBAT 1 1
(VIN - VBAT )´ ´ VIN ´ (1- D )´ D ´
VIN fs fs
IRIPPLE = =
L L (4)
where:
VIN = adapter voltage
VBAT = BAT voltage
fS = switching frequency
L = output inductor
D = duty-cycle
IRIPPLE_MAX Happens when the duty-cycle(D) is mostly near to 0.5 at given VIN, fs, and L.
The ISYNSET comparator, or charge undercurrent comparator, compares the voltage between SRP-SRN and
internal threshold. The threshold is set to 13 mV on the falling edge, with an 8-mV hysteresis on the rising edge
with a 10% variation.
After 2 ms, ACOP is enabled. ACOP allows the ACFET to latch off before the ACFET can be damaged by
excessive thermal dissipation. The controller only latches if the ACOP pin voltage exceeds 2 V with respect to
AGND. In ACOP, a current source begins to charge the ACOP capacitor when the input current is being limited
by ACOC. This current source is proportional to the voltage across the source-drain of the ACFET (VPVCC-ACP) by
an 18-µA/V ratio. This dependency allows faster capacitor charging if the voltage is larger (more power
dissipation). It allows the time to be programmed by the ACOP capacitor selected. If the controller is not limiting
current, a fixed 5-µA sink current into the ACOP pin to discharge the ACOP capacitor. This charge and discharge
effect depends on whether there is a current-limit condition, and has a memory effect that averages the power
over time, protecting the system from potentially hazardous repetitive faults. Whenever the ACOP threshold is
exceeded, the charge is disabled and the adapter is disconnected from the system to protect the ACFET and the
whole system. If the ACFET is latched off, the BATFET is turned on to connect the battery to the system.
The capacitor provides a predictable time to limit the power dissipation of the ACFET. Since the input current is
constant at the ACOC current limit, the designer can calculate the power dissipation on the ACFET.
Power = Id × Vsd = IACOC _ LIM × V(PVCC - ACP)
The ACOC current Limit threshold is equal to .
The time it takes to charge to 2V can be calculated from
C × DVACOP C ACOP × 2V
Dt = ACOP =
i ACOP 18mA/V × V(PVCC - ACP) (5)
An ACOP fault latch off can only be cleared by bringing the ACDET pin voltage below 2.4 V, then above 2.4 V
(i.e. remove adapter and reinsert), or by reducing the PVCC voltage below the UVLO threshold and raising it.
ACOC, No Latch-off
Latch-off time accumulates
only when in current limit 1) bringing ACDET below
regulation, ACOC. The time 2.4V, then above 2. 4V; or
before latch-off is
programmable with Cacop, 2) bringing PVCC below
and is inversely proportional to UVLO, then above
700ms delay after source-drain voltage of UVLO.
ACDET, before allow ACFET (power). Cacop
ACDRV to turn-on charge/discharge per time
also provides memory for
power averaging over time.
700ms
2ms 8ms
Allow Charge to Turn-on
Vin
Vadapter
ACDET
0V
ACGOOD
BATDRV
ACDRV
Vadapter
Vsystem
Vbattery
Ilim = 1.5xIdpm
(100 mV max Input Current
Across ACP_ACN)
Allow Charge
Charge Current
V(ACOP)
A. ACFET overpower protection; initial current limit allows safe soft-start without system voltage droop.
Iin
Ilim = 1.5xIdpm
ACOC_REG
V(PVCC-ACP)
LATCH-OFF
Iacop_pin
LATCH-OFF
2V
ON OFF
ACDRV_ON
LATCH-OFF
Figure 35. ACOC Protection and ACOP Latch Off with Memory Effect Example
RAC
0.01 W
ADAPTER+
R10
2W P P
ADAPTER–
C1 Q1 (ACFET) Q2 (ACFET)
2.2 µF SI4435 SI4435
C2 C3
0.1 µF 0.1 µF ACSET
ACDRV_ON
ACOC ERROR
AMPLIFIER and
DRIVER Regulation
ACDRV Reference IDPM
– Lowest of IDPM_PRG Ratio-
+
1.5xIDPM_PRG metric
ACOCREG = or Program
(100 mV_max)
REGULATING 10 A (100 mV)
IIN
ACN Differential Amp
CSA
– V(ACP-ACN)
+
ACP IADAPT
–
+
PVCC
VDS
Differential Amp
C8 V(PVCC-ACP)
0.1 µF Isrc = K*V(PVCC-ACP)
K = 18 µA/V
APPLICATION INFORMATION
IIN VIN
Ri Li Rc
Vi
Ci Vc
Figure 38 (a) demonstrates a higher Ci helps dampen the voltage spike. Figure 38 (b) demonstrates the effect of
the input stray inductance Li upon the input voltage spike. Figure 38 (c) shows how increased resistance helps to
suppress the input voltage spike.
35 35
Ci = 20 mF Li = 5 mH
Ri = 0.21 W Ri = 0.15 W
30 30
Ci = 40 mF Li = 9.3 mH Ci = 40 mF
Li = 12 mH
Input Capacitor Voltage - V
20 20
15 15
10 10
5 5
0 0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Time - ms Time - ms
(a) Vc with various Ci values (b) Vc with various Li values
35
Ri = 0.15 W
Li = 9.3 mH
30
Ci = 40 mF
Input Capacitor Voltage - V
Ri = 0.5 W
25
20
15
10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Time - ms
(c) Vc with various Ri values
As shown in Figure 38, minimizing the input stray inductance, increasing the input capacitance, and adding
resistance (including using higher ESR capacitors) helps suppress the input voltage spike. However, a user often
cannot control input stray inductance and increasing capacitance can increase costs. Therefore, the most
efficient and cost-effective approach is to add an external resistor.
Figure 39 depicts the recommended input filter design. The measured input voltage and current waveforms are
shown in Figure 40. The input voltage spike has been well damped by adding a 2Ω resistor, while keeping the
capacitance low.
VIN VPVCC
2W Rext
(0.5 W, 1210 anti-surge)
2.2 mF C1 C2 0.1 mF
(25 V, 1210) (50 V, 0805, very close to PVCC)
Figure 39. Recommended Input Filter Design Figure 40. Adapter DC Side Hot Plug-in Test Waveforms
www.ti.com 10-Jun-2014
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
BQ24751ARHDR NRND VQFN RHD 28 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 BQ
& no Sb/Br) 24751A
BQ24751ARHDT NRND VQFN RHD 28 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 BQ
& no Sb/Br) 24751A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 10-Jun-2014
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Aug-2014
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Aug-2014
Pack Materials-Page 2
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