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Digital Logic and Circuits and Discrete Mathematical

Number Systems and Codes

1.Convert hexadecimal value 16 to decimal.


A. 2210
B. 1610
C. 1010
D. 2010
Answer: Option A

2 Convert the following decimal number to 8-bit binary.


. 187
A. 101110112
B. 110111012
C. 101111012
D. 101111002
Answer: Option A

3 Convert binary 111111110010 to hexadecimal.


. A. EE216
B. FF216
C. 2FE16
D. FD216
Answer: Option B

4 Convert the following binary number to decimal.


. 010112
A. 11
B. 35
C. 15
D. 10
Answer: Option A

5 Convert the binary number 1001.00102 to decimal.


. A. 90.125
B. 9.125
C. 125
D. 12.5
Answer: Option B

6 Decode the following ASCII message.


. 10100111010100101010110001001011001
01000001001000100000110100101000100
A. STUDYHARD
B. STUDY HARD
C. stydyhard
D. study hard
Answer: Option B

7 The voltages in digital electronics are continuously variable.


. A. True
B. False
Answer: Option B
8. One hex digit is sometimes referred to as a(n):
A. byte
B. nibble
C. grouping
D. instruction
Answer: Option B

9. Which of the following is the most widely used alphanumeric code for computer input and output?
A. Gray
B. ASCII
C. Parity
D. EBCDIC
Answer: Option B

10 If a typical PC uses a 20-bit address code, how much memory can the CPU address?
. A. 20 MB
B. 10 MB
C. 1 MB
D. 580 MB
Answer: Option C

11 Convert 59.7210 to BCD.


. A. 111011
B. 01011001.01110010
C. 1110.11
D. 0101100101110010
Answer: Option B

12 Convert 8B3F16 to binary.


. A. 35647
B. 011010
C. 1011001111100011
D. 1000101100111111
Answer: Option D

13 Which is typically the longest: bit, byte, nibble, word?


. A. Bit
B. Byte
C. Nibble
D. Word
Answer: Option D

14 Assign the proper odd parity bit to the code 111001.


. A. 1111011
B. 1111001
C. 0111111
D. 0011111
Answer: Option B

1 Convert decimal 64 to binary.


5. A. 01010010
B. 01000000
C. 00110110
D. 01001000
Answer: Option B

1 Convert hexadecimal value C1 to binary.


6. A. 11000001
B. 1000111
C. 111000100
D. 111000001
Answer: Option A

1 Convert the following octal number to decimal.


7. 178
A. 51
B. 82
C. 57
D. 15
Answer: Option D

1 Convert the following binary number to octal.


8. 0101111002
A. 1728
B. 2728
C. 1748
D. 2748
Answer: Option D

1 How many binary digits are required to count to 10010?


9. A. 7
B. 2
C. 3
D. 100
Answer: Option A

2 The BCD number for decimal 347 is ________.


0. A. 1100 1011 1000
B. 0011 0100 0111
C. 0011 0100 0001
D. 1100 1011 0110
Answer: Option B

2 The binary number for octal 458 is ________.


1. A. 100010
B. 100101
C. 110101
D. 100100
Answer: Option B
22 The sum of 11101 + 10111 equals ________.
. A. 110011
B. 100001
C. 110100
D. 100100
Answer: Option C

23 Convert the following binary number to decimal.


. 100110102
A. 154
B. 155
C. 153
D. 157
Answer: Option A

24 The decimal number 188 is equal to the binary number ________.


. A. 10111100
B. 0111000
C. 1100011
D. 1111000
Answer: Option A

25 Convert the following binary number to octal.


. 0011010112
A. 1538
B. 3518
C. 2538
D. 3528
Answer: Option A

26 How many bits are in an ASCII character?


. A. 16
B. 8
C. 7
D. 4
Answer: Option C

27 A binary number's value changes most drastically when the ________ is changed.
. A. MSB
B. frequency
C. LSB
D. duty cycle
Answer: Option A

28 Convert decimal 213 to binary.


. A. 11001101
B. 11010101
C. 01111001
D. 11100011
Answer: Option B
29 The decimal number for octal 748 is ________.
. A. 74
B. 60
C. 22
D. 62
Answer: Option B

30 The sum of the two BCD numbers, 0011 + 0011, is ________.


. A. 0110
B. 0111
C. 0011
D. 1100
Answer: Option A

31 Convert binary 01001110 to decimal.


. A. 4E
B. 78
C. 76
D. 116
Answer: Option B

32 Which is not a word size?


. A. 64
B. 28
C. 16
D. 8
Answer: Option B

33 The octal numbering system:


. A. simplifies tasks
B. groups binary numbers in groups of 4
C. saves time
D. simplifies tasks and saves time
Answer: Option D

34 The binary number 1110 is equal to the decimal number ________.


. A. 3
B. 1
C. 7
D. 14
Answer: Option D

35 Convert the following octal number to binary.


. 768
A. 1101112
B. 1111102
C. 1111002
D. 1001112
Answer: Option B
36 Convert 11001010001101012 to hexadecimal.
. A. 121035
B. CA35
C. 53AC1
D. 530121
Answer: Option B

37 Convert the following decimal number to octal.


. 281
A. 1348
B. 4318
C. 3318
D. 1338
Answer: Option B

38 When using even parity, where is the parity bit placed?


. A. Before the MSB
B. After the LSB
C. In the parity word
D. After the odd parity bit
Answer: Option A
39 Convert the following octal number to decimal.
. 358
A. 71
B. 17
C. 92
D. 29
Answer: Option D

40 Convert binary 11001111 to hexadecimal.


. A. 8F16
B. CE16
C. DF16
D. CF16
Answer: Option D

41 Convert 17318 to decimal.


. A. 216.4
B. 985
C. 3D9
D. 1123
Answer: Option B

42 An analog signal has a range from 0 V to 5 V. What is the total number of analog possibilities within this
. range?
A. 5
B. 50
C. 250
D. infinite
Answer: Option D
43 Hexadecimal letters A through F are used for decimal equivalent values from:
. A. 1 through 6
B. 9 through 14
C. 10 through 15
D. 11 through 17
Answer: Option C

44 Convert the following decimal number to 8-bit binary.


. 35
A. 000100102
B. 000100112
C. 001000112
D. 001000102
Answer: Option C

45 Convert the following hexadecimal number to binary.


. C916
A. 101110012
B. 101110112
C. 100111002
D. 110010012
Answer: Option D

46 Convert the following decimal number to hexadecimal.


. 125
A. 7D16
B. D716
C. 7C16
D. C716
Answer: Option A

47 A decimal 11 in BCD is ________.


. A. 00001011
B. 00001100
C. 00010001
D. 00010010
Answer: Option C

48 What is the resultant binary of the decimal problem 49 + 01 = ?


. A. 01010101
B. 00110101
C. 00110010
D. 00110001
Answer: Option C

49 The difference of 111 – 001 equals ________.


. A. 100
B. 111
C. 001
D. 110
Answer: Option D
50 Convert the binary number 1100 to Gray code.
. A. 0011
B. 1010
C. 1100
D. 1001
Answer: Option B

51 The binary number 11101011000111010 can be written in hexadecimal as ________.


. A. DD63A16
B. 1D63A16
C. 1D33A16
D. 1D63116
Answer: Option B

52 Which of the following is an invalid BCD code?


. A. 0011
B. 1101
C. 0101
D. 1001
Answer: Option B
Explanation:

53 What decimal number does 25 represent?


. A. 10
B. 31
C. 25
D. 32
Answer: Option D

54 Convert the Gray code 1011 to binary.


. A. 1011
B. 1010
C. 0100
D. 1101
Answer: Option D

55 Determine the decimal equivalent of the signed binary number 11110100 in 1's complement.
. A. 116
B. –12
C. 11
D. 128
Answer: Option C

56 What is the difference between binary coding and binary-coded decimal?


. A. BCD is pure binary.
B. Binary coding has a decimal format.
C. BCD has no decimal format.
D. Binary coding is pure binary.
Answer: Option D
57 Convert the following decimal number to BCD.
. 127
A. 011100100001
B. 111010001
C. 001010111
D. 000100100111
Answer: Option D

58 Digital electronics is based on the ________ numbering system.


. A. decimal
B. octal
C. binary
D. hexadecimal
Answer: Option C

59 An informational signal that makes use of binary digits is considered to be:


. A. solid state
B. digital
C. analog
D. non-oscillating
Answer: Option B

60 The 1's complement of 10011101 is ________.


. A. 01100010
B. 10011110
C. 01100001
D. 01100011
Answer: Option A

61 The binary number 101110101111010 can be written in octal as ________.


. A. 515628
B. 565778
C. 656278
D. 565728
Answer: Option D

62 Convert 45710 to hexadecimal.


. A. 711
B. 2C7
C. 811
D. 1C9
Answer: Option D

63 Convert the decimal number 151.75 to binary.


. A. 10000111.11
B. 11010011.01
C. 00111100.00
D. 10010111.11
Answer: Option D
64 Convert the following octal number to binary.
. 1048
A. 0010001002
B. 1000000012
C. 00101002
D. 10000012
Answer: Option A

65 3 × 101 + 7 × 100 is equal to ________.


. A. 3.7
B. 37
C. 10
D. 370
Answer: Option B

66 3428 is the decimal value for which of the following binary-coded decimal (BCD) groupings?
. A. 11010001001000
B. 11010000101000
C. 011010010000010
D. 110100001101010
Answer: Option B

67 The binary-coded decimal (BCD) system can be used to represent each of the 10 decimal digits as a(n):
. A. 4-bit binary code
B. 8-bit binary code
C. 16-bit binary code
D. ASCII code
Answer: Option A

68 The decimal number 18 is equal to the binary number ________.


. A. 11110
B. 10001
C. 10010
D. 1111000
Answer: Option C

69 The 2's complement of 11100111 is ________.


. A. 11100110
B. 00011001
C. 00011000
D. 00011010
Answer: Option B

70 Convert the following decimal number to BCD.


. 469
A. 100101101000
B. 010001101001
C. 100001101001
D. 100101100100
Answer: Option B
71 Express the decimal number –37 as an 8-bit number in sign-magnitude.
. A. 10100101
B. 00100101
C. 11011000
D. 11010001
Answer: Option A

72 Convert the following BCD number to decimal.


. 010101101001bcd
A. 539
B. 2551
C. 569
D. 1552
Answer: Option C

73 The binary number 11001110 is equal to the decimal number ________.


. A. 12
B. 206
C. 127
D. 66
Answer: Option B

74 The binary number for F3A16 is ________.


. A. 111100111010
B. 111100111110
C. 000000111010
D. 000011000100
Answer: Option A

75 Convert the following BCD number to decimal.


. 100000000011bcd
A. 8003
B. 803
C. 1003
D. 103
Answer: Option B

76 Convert the following hexadecimal number to binary.


. 14B16
A. 1011010000012
B. 0001010010112
C. 0001010011012
D. 1101010000012
Answer: Option B

77 What is the result when a decimal 5238 is converted to base 16?


. A. 327.375
B. 12.166
C. 1388
D. 1476
Answer: Option D
78 The octal number for binary 1101110101110110 is ________.
. A. 6545218
B. 5565618
C. 1566568
D. 1565668
Answer: Option D

79 Convert the following hexadecimal number to decimal.


. 1CF16
A. 463
B. 4033
C. 479
D. 4049
Answer: Option A

80 Convert the binary number 1011010 to hexadecimal.


. A. 5B
B. 5F
C. 5A
D. 5C
Answer: Option C

81 Convert the following decimal number to hexadecimal.


. 74
A. A416
B. B416
C. 4A16
D. 4B16
Answer: Option C

82 Convert hexadecimal C0B to binary.


. A. 110000001011
B. 110000001001
C. 110000001100
D. 110100001011
Answer: Option A

83 Convert binary 1001 to hexadecimal.


. A. 916
B. 1116
C. 10116
D. 1016
Answer: Option A

84 Convert 73116 to decimal.


. A. 216.4
B. 985
C. 3D9
D. 1841
Answer: Option D
85 What is the decimal value of the hexadecimal number 777?
. A. 191
B. 1911
C. 19
D. 19111
Answer: Option B
86 Convert 110010012 (binary) to decimal.
. A. 201
B. 2001
C. 20
D. 210
Answer: Option A

87 Convert the following decimal number to octal.


. 39
A. 638
B. 368
C. 478
D. 748
Answer: Option C

88 The American Standard Code for Information Interchange (ASCII) uses how many individual pulses for any
. given character?
A. 1
B. 2
C. 7
D. 8
Answer: Option C

89 Convert the following hexadecimal number to decimal.


. B516
A. 212
B. 197
C. 165
D. 181
Answer: Option D

90 The BCD number for decimal 16 is ________.


. A. 00010110
B. 00010000
C. 00010010
D. 11100000
Answer: Option A

91 Alphanumeric codes should include as a minimum:


. A. the capacity to represent the alphabet upper- and lowercase characters and the decimal numbers in a
straight binary format.
B. the capacity to code all possible decimal numbers in a direct octal representation of BCD codes.
C. the alphabet upper- and lowercase letters, the decimal digits, the seven punctuation marks, and other
characters or symbols.
D. the ability to represent decimal numbers greater than 12810 in a straight binary format.
Answer: Option C
92 Convert 52716 to binary.
. A. 343
B. 001101000111
C. 010100100111
D. 011100100101
Answer: Option C

93 Convert 5278 to binary.


. A. 011100111
B. 101010111
C. 343
D. 111010101
Answer: Option B

94 The base of the hexadecimal system is:


. A. eight.
B. sixteen.
C. ten.
D. two.
Answer: Option B

95 Assign the proper even parity bit to the code 1100001.


. A. 11100001
B. 1100001
C. 01100001
D. 01110101
Answer: Option A

96 Select one of the following statements that best describes the parity method of error detection.
. A. Parity checking is best suited for detecting single-bit errors in transmitted codes.
B. Parity checking is not suitable for detecting single-bit errors in transmitted codes.
C. Parity checking is capable of detecting and correcting errors in transmitted codes.
D. Parity checking is best suited for detecting double-bit errors that occur during the transmission of codes
from one location to another.
Answer: Option A

97 Which of the following is the primary advantage of using the BCD code instead of straight binary coding?
. A. Fewer bits are required to represent a decimal number with the BCD code.
B. The relative ease of converting to and from decimal.
C. BCD codes are easily converted to hexadecimal codes.
D. BCD codes are easily converted to straight binary codes.
Answer: Option B

98 How many BCD code bits and how many straight binary bits would be required to represent the decimal
. number 643?
A. 12 BCD, 12 binary
B. 12 BCD, 10 binary
C. 12 BCD, 9 binary
D. 16 BCD, 9 binary
Answer: Option B
When using the repeated division by 2 method of converting from decimal to binary, one must write the first
remainder as the:
A. MSB
B. MSB, provided the following sequence of remainders are written in descending order until the final
remainder is achieved.
C. LSB
D. LSB, provided the final remainder is used to replace the original LSB, which is then moved to the MSB
position.
Answer: Option A

Boolean Algebra and Logic Simplification


1. Convert the following SOP expression to an equivalent POS expression.
A.
B.
C.
D.
Answer: Option B

2. Determine the values of A, B, C, and D that make the sum term equal to zero.
A.A = 1, B = 0, C = 0, D = 0
B. A = 1, B = 0, C = 1, D = 0
C. A = 0, B = 1, C = 0, D = 0
D. A = 1, B = 0, C = 1, D = 1
Answer: Option B

3. Which of the following expressions is in the sum-of-products (SOP) form?


A.(A + B)(C + D)
B. (A)B(CD)
C. AB(CD)
D. AB + CD
Answer: Option D

4. Derive the Boolean expression for the logic circuit shown below:

A.

B.

C.
D.
Answer: Option A

5. From the truth table below, determine the standard SOP expression.
A.
B.
C.
D.
Answer: Option D
6. One of De Morgan's theorems states that . Simply stated, this means that logically there is no
difference between:
A.a NOR and an AND gate with inverted inputs
B. a NAND and an OR gate with inverted inputs
C. an AND and a NOR gate with inverted inputs
D. a NOR and a NAND gate with inverted inputs
Answer: Option A

7. The commutative law of Boolean addition states that A + B = A × B.


A.True
B. False
Answer: Option B

8. Applying DeMorgan's theorem to the expression , we get ________.


A.
B.
C.
D.
Answer: Option A

9. The systematic reduction of logic circuits is accomplished by:


A.using Boolean algebra
B. symbolic reduction
C. TTL logic
D. using a truth table
Answer: Option A

10. Which output expression might indicate a product-of-sums circuit construction?


A.
B.
C.
D.
Answer: Option D
11. An AND gate with schematic "bubbles" on its inputs performs the same function as a(n)________ gate.
A.NOT
B. OR
C. NOR
D. NAND
Answer: Option C

12. For the SOP expression , how many 1s are in the truth table's output column?
A.1
B. 2
C. 3
D. 5
Answer: Option C

13. A truth table for the SOP expression has how many input combinations?
A.1
B. 2
C. 4
D. 8
Answer: Option D

14. How many gates would be required to implement the following Boolean expression before simplification?
XY + X(X + Z) + Y(X + Z)
A.1
B. 2
C. 4
D. 5
Answer: Option D

15. Determine the values of A, B, C, and D that make the product term equal to 1.
A.A = 0, B = 1, C = 0, D = 1
B. A = 0, B = 0, C = 0, D = 1
C. A = 1, B = 1, C = 1, D = 1
D. A = 0, B = 0, C = 1, D = 0
Answer: Option A
16. What is the primary motivation for using Boolean algebra to simplify logic expressions?
A.It may make it easier to understand the overall function of the circuit.
B. It may reduce the number of gates.
C. It may reduce the number of inputs required.
D. all of the above
Answer: Option D

17. How many gates would be required to implement the following Boolean expression after simplification?
XY + X(X + Z) + Y(X + Z)
A.1
B. 2
C. 4
D. 5
Answer: Option B

18. AC + ABC = AC
A.True
B. False
Answer: Option A

19. When are the inputs to a NAND gate, according to De Morgan's theorem, the output expression
could be:
A.X = A + B

B.
C. X = (A)(B)
D.
Answer: Option A

20. Which Boolean algebra property allows us to group operands in an expression in any order without
affecting the results of the operation [for example, A + B= B + A]?
A.associative
B. commutative
C. Boolean
D. distributive
Answer: Option B

21. Applying DeMorgan's theorem to the expression , we get ________


A.
B.
C.
D.
Answer: Option A

22. When grouping cells within a K-map, the cells must be combined in groups of ________.
A.2s
B. 1, 2, 4, 8, etc.
C. 4s
D. 3s
Answer: Option B

23. Use Boolean algebra to find the most simplified SOP expression
for F = ABD + CD + ACD + ABC + ABCD.
A.F = ABD + ABC + CD
B. F = CD + AD
C. F = BC + AB
D. F = AC + AD
Answer: Option A

24. Occasionally, a particular logic expression will be of no consequence in the operation of a circuit, such as a
BCD-to-decimal converter. These result in ________terms in the K-map and can be treated as either ________ or
________, in order to ________ the resulting term.
A.don't care, 1s, 0s, simplify
B. spurious, ANDs, ORs, eliminate
C. duplicate, 1s, 0s, verify
D. spurious, 1s, 0s, simplify
Answer: Option A

25. The NAND or NOR gates are referred to as "universal" gates because either:
A.can be found in almost all digital circuits
B. can be used to build all the other types of gates
C. are used in all countries of the world
D. were the first gates to be integrated
Answer: Option B
26. The truth table for the SOP expression has how many input combinations?
A.1
B. 2
C. 4
D. 8
Answer: Option D

27. Converting the Boolean expression LM + M(NO + PQ) to SOP form, we get ________.
A.LM + MNOPQ
B. L + MNO + MPQ
C. LM + M + NO + MPQ
D. LM + MNO + MPQ
Answer: Option D

28. A Karnaugh map is a systematic way of reducing which type of expression?


A.product-of-sums
B. exclusive NOR
C. sum-of-products
D. those with overbars
Answer: Option C

29. The Boolean expression is logically equivalent to what single gate?


A.NAND
B. NOR
C. AND
D. OR
Answer: Option A

30. Applying the distributive law to the expression , we get ________.

A.
B.
C.
D.
Answer: Option D
31. Mapping the SOP expression , we get ________.

A.(A)
B. (B)
C. (C)
D. (D)
Answer: Option B

32. Derive the Boolean expression for the logic circuit shown below:

A.
B.
C.
D.
Answer: Option C

33. Which is the correct logic function for this PAL diagram?

A.
B.
C.
D.
Answer: Option C

34. For the SOP expression , how many 0s are in the truth table's output column?
A.zero
B. 1
C. 4
D. 5
Answer: Option C

35. Mapping the standard SOP expression , we get


A.(A)
B. (B)
C. (C)
D. (D)
Answer: Option B
36. Which statement below best describes a Karnaugh map?
A.A Karnaugh map can be used to replace Boolean rules.
B. The Karnaugh map eliminates the need for using NAND and NOR gates.
C. Variable complements can be eliminated by using Karnaugh maps.
D. Karnaugh maps provide a cookbook approach to simplifying Boolean expressions.
Answer: Option D

37. Applying DeMorgan's theorem to the expression , we get ________.


A.
B.
C.
D.
Answer: Option D

38. Which of the examples below expresses the distributive law of Boolean algebra?
A.(A + B) + C = A + (B + C)
B. A(B + C) = AB + AC
C. A + (B + C) = AB + AC
D. A(BC) = (AB) + C
Answer: Option B

39. Applying DeMorgan's theorem to the expression , we get ________.


A.
B.
C.
D.
Answer: Option A

40. Which of the following is an important feature of the sum-of-products (SOP) form of expression?
A.All logic circuits are reduced to nothing more than simple AND and OR gates.
B. The delay times are greatly reduced over other forms.
C. No signal must pass through more than two gates, not including inverters.
D. The maximum number of gates that any signal must pass through is reduced by a factor of two.
Answer: Option C
41. An OR gate with schematic "bubbles" on its inputs performs the same functions as a(n)________ gate.
A.NOR
B. OR
C. NOT
D. NAND
Answer: Option D

42. Which of the examples below expresses the commutative law of multiplication?
A.A + B = B + A
B. AB = B + A
C. AB = BA
D. AB = A × B
Answer: Option C

43. Determine the binary values of the variables for which the following standard POS expression is equal to
0.
A.(0 + 1 + 0)(1 + 0 + 1)
B. (1 + 1 + 1)(0 + 0 + 0)
C. (0 + 0 + 0)(1 + 0 + 1)
D. (1 + 1 + 0)(1 + 0 + 0)
Answer: Option A

44. The expression W(X + YZ) can be converted to SOP form by applying which law?
A.associative law
B. commutative law
C. distributive law
D. none of the above
Answer: Option C

45. The commutative law of addition and multiplication indicates that:


A.we can group variables in an AND or in an OR any way we want
B. an expression can be expanded by multiplying term by term just the same as in ordinary algebra
C. the way we OR or AND two variables is unimportant because the result is the same
D. the factoring of Boolean expressions requires the multiplication of product terms that contain like variables
Answer: Option C
46. Which of the following combinations cannot be combined into K-map groups?
A.corners in the same row
B. corners in the same column
C. diagonal
D. overlapping combinations
Answer: Option C
Boolean algebra is also called
A. switching algebra
B. arithmetic algebra
C. linear algebra
D. algebra
To perform product of maxterms Boolean function must be brought into
A. AND terms
B. OR terms
C. NOT terms
D. NAND terms
According to boolean algebra absorption law, which of following is correct?
A. x+xy=x
B. (x+y)=xy
C. xy+y=x
D. x+y=y
A Boolean function may be transformed into
A. logical diagram
B. logical graph
C. map
D. matrix
X*y = y*x is
A. commutative law
B. inverse property
C. associative law
D. identity element
MCQ. Minterms are also called
A. standard sum
B. standard product
C. standard division
D. standard subtraction
MCQ. Maxterms are also called
A. standard sum
B. standard product
C. standard division
D. standard subtraction
MCQ. In Boolean algebra Multiplicative inverse is
A. 0
B. 1
C. 1/a
D. a
MCQ. Boolean algebra is defined as a set of
A. three values
B. two values
C. four values
D. five values
MCQ. First operator precedence for evaluating Boolean expressions is
A. parenthesis
B. AND
C. OR
D. NOT
MCQ. (a+b+c)'=
A. a'b'c'
B. a'+b'+c'
C. abc
D. a+b+c
MCQ. Complement of function (A+B+C)' using theorem and laws is
A. (A')+B+C
B. (A+B)'+C
C. A+B+C
D. A'B'C'
MCQ. A boolean function can be converted from algebraic expressions to a product of maxterms by using
A. graphical representation
B. Truth table
C. Canonical Conversion Method
D. Both b and c
MCQ. A helpful illustration used to visualize relationships among variables of Boolean expression is
A. map
B. logic gates
C. Venn diagram
D. graph
MCQ. A binary variable can take values
A. 0 only
B. 0 and -1
C. 0 and 1
D. 1 and 2
MCQ. According to Boolean algebra theorems x.x is equal to
A. x
B. 1
C. 0
D. x'
MCQ. In Boolean algebra 0 is a
A. commutative property
B. Additive identity
C. associative identity
D. identity element
MCQ. Symbol representing AND operation
A. (+)
B. (.)
C. (-)
D. (/)
MCQ. Boolean algebra is an algebraic structure with two arithmetic operations
A. addition and subtraction
B. subtraction and multiplication
C. addition and multiplication
D. addition and division
MCQ. 2^3 would have
A. three values
B. four values
C. six values
D. eight values
MCQ. Is it possible to find two algebraic expressions that specify same function
A. no
B. yes
C. maybe
D. never
Answer
MCQ. According to boolean algebra, postulate 2 w.r.t addition is
A. x+0=x
B. x+0=1
C. x+0=0
D. x+1=0
MCQ. X+xy=
A. y
B. 1
C. 0
D. x
MCQ. X+0=0+x =x is an example of
A. commutative property
B. inverse property
C. associative property
D. Identity element
MCQ. Boolean algebra is collection of objects having
A. positive properties
B. negative properties
C. common properties
D. different properties
AMCQ. An identity element w.r.t addition
A. x-1
B. x+1
C. x-0
D. x+0
MCQ. If x=0, y=0, z=0, term x'y'z' inminterms have designation of
A. m⊂0
B. m⊂1
C. m⊂2
D. m⊂3
MCQ. Complement of a function expressed as
A. sum of minterms
B. product of minterms
C. sum of maxterms
D. product of maxterms
MCQ. (x*y)*z=x*(y*z) is the
A. commutative property
B. inverse property
C. identity element
D. associative property
MCQ. X+x'=? Is equal to
A. 0
B. 1
C. x
D. x'
Simplification of Boolean Functions
MCQ. Two variables will be represented by
A. eight minterms
B. six minterms
C. five minterms
D. four minterms
MCQ. NAND function is represented by
A. F=x
B. F=(xy)'
C. F=xy
D. F=(x+y)'
MCQ. The output of AND gates in Sum of Product (SOP) is connected to
A. NOT gates
B. OR gates
C. AND gates
D. XOR gates
MCQ. The logical sum of minters associated with boolean function specifies the conditions under which the
function is
A. equals to 1
B. equals to 0
C. none
D. both
MCQ. The minterms in a karnaugh map are marked with a
A. y
B. x
C. 0
D. 1
The starting point of the tabulation method that specify the function is
A. the list of minterms
B. the list of maxterms
C. the list of integers
D. None
MCQ. The wired AND gate is not the
A. useful gate
B. combined gate
C. physical gate
D. logic gate
MCQ. In 2^k, k is any set of
A. prime numbers
B. whole numbers
C. even numbers
D. odd numbers
MCQ. 2^k adjacent squares in an N variable map will have literals having value of
A. k
B. N
C. k-N
D. N-k
MCQ. Adjacent squares represents a
A. circle
B. variable
C. literal
D. minterm
MCQ. X don't care can be included with
A. 1's and 0's
B. 1's only
C. 0's only
D. no above
MCQ. Karnaugh map is made up of
A. circles
B. squares
C. rectangles
D. triangles
MCQ. OR-NAND and NOR-OR performs which function?
A. OR AND invert
B. NOR AND invert
C. OR NAND invert
D. NOR-OR invert
MCQ. A six Variable map needs
A. 32 Squares
B. 40 Squares
C. 50 Squares
D. 64 Squares
MCQ. Larger the combined square smaller the
A. terms
B. literals
C. values
D. points
MCQ. Small circle in a NAND circuit represents
A. input
B. bits
C. output
D. complement
MCQ. Tabulation method is adopted for giving simplified function in
A. subtraction of sum
B. sum of products
C. product of sums
D. subtraction of product
MCQ. Selection of prime implicants are made from
A. even implicant table
B. odd implicant table
C. prime implicant table
D. truth tables
MCQ. Each square in a karnaugh map represents a
A. points
B. values
C. minterm
D. maxterm
MCQ. Sum of products can be done using
A. demorgan's theorem
B. algebraic theorem
C. demorgan's postulate
D. algebraic postulate
MCQ. Complement of F' gives back
A. F'
B. F
C. FF
D. undefined variable
MCQ. Unchecked terms in the table forms are
A. odd implicant
B. Even implicant
C. Prime Implications
D. None
MCQ. If 1's represents minterms then 0's represents
A. maxterms
B. minterms
C. midterms
D. medians
MCQ. Dual complement can be represented as
A. (f ')'
B. (f '')
C. (f )''
D. (f )
MCQ. The gates most found in integrated circuits are
A. NAND, AND
B. NAND, NOR
C. NOR, OR
D. OR,AND
MCQ. The karnaugh map is also known as
A. veitch diagram
B. Venn diagram
C. virtual diagram
D. logic diagram
MCQ. NOR gate is implementation of
A. NOT gates
B. OR gates
C. AND gates
D. XOR gates
MCQ. Eight minterms will be used for
A. three variables
B. four variables
C. five variables
D. six variables
MCQ. Combining the maximum possible no of adjacent squares in a map is called
A. odd implicant
B. even implicant
C. prime implicant
D. integer implicant
MCQ. OR invert is the
A. conventional design
B. unconventional symbol
C. conventional symbol
D. undefined symbol
MCQ. NAND gate is implementation of
A. NOT gates
B. OR gates
C. AND gates
D. XOR gates
MCQ. Don't cares in a map are distinguished from 0's and 1's by
A. Z
B. X
C. Y
D. any variable
MCQ. Minterms are arranged in map in a sequence of
A. binary sequence
B. gray code
C. binary variables
D. BCD code
MCQ. Gates sometimes provide the facility of
A. wired logic
B. algorithms
C. connections
D. switches
MCQ. In the map representation the number of variables cannot be exceeded by
A. 4,5
B. 2,3
C. 5,6
D. 7,8
MCQ. NOR gate requires function to be simplified in
A. sum of product
B. product of sum
C. subtraction of product
D. division of sum
MCQ. One square in a map represents
A. four minterms
B. three minterms
C. two minterms
D. one minterm
MCQ. OR-AND-invert implementation needs
A. subtraction of sum
B. sum of products
C. product of sums
D. subtraction of product
MCQ. In map only one digit changes their value between two adjacent rows or column this may called as
A. reflected code sequence
B. reflected sequence
C. refracted code sequence
D. reflected code density
MCQ. Adjacent squares are squares that are
A. back to each other
B. next each other
C. up to each other
D. down to each other
MCQ. No degenerate forms of logic gates are
A. 2
B. 4
C. 6
D. 8
MCQ. The tabulation form uses
A. Venn diagram
B. matching process cycle
C. demorgan's postulate
D. gates
MCQ. Only value that is mentioned on map is
A. 1's
B. 0's
C. 2's
D. 9's
MCQ. A five variable karnaugh map needs
A. 32 squares
B. 33 squares
C. 34 squares
D. 35 squares
Answer
MCQ. The first tabulation method was
A. MCQuine
B. Cluskey
C. Quine-McCluskey
D. None
Digital Logic Gates
MCQ. Negation can be determined by
A. NOT gate
B. AND gate
C. NOR gate
D. NAND gate
MCQ. NOT gate has
A. one input
B. two inputs
C. three inputs
D. four inputs
MCQ. NOT of AND gate is called
A. NAND gate
B. NOR gate
C. NXOR gate
D. XOR gate
MCQ. We can reproduce all other basic logic gates with the help of
A. NOT gate
B. XNOT gate
C. AND gate
D. NAND gate
MCQ. To reset a state in a circuit we use AND with a mask of
A. 1
B. 0
C. 5V
D. 3.3 V
MCQ. Gate devices function by
A. input signal
B. source signal
C. logical signal
D. output signal
MCQ. We can easily build an AND gate from
A. one NAND gate
B. two NAND gates
C. three NAND gates
D. four NAND gates
MCQ. Table which is a tabulation of all possible inputs and the resulting outputs is referred to as
A. truth logic
B. logic signal
C. truth table
D. multiple table
MCQ. AND gate can be used as
A. electronic switch
B. amplifier
C. summer
D. integrator
MCQ. OR gate can be defined as two sets
A. intersection
B. union
C. addition
D. subtraction
MCQ. The relationship between the input signals and the output signals is often summarized in a
A. truth logic
B. logic signal
C. truth table
D. multiple table
MCQ. A basic OR gate consists of
A. one input
B. two inputs
C. three inputs
D. four inputs
MCQ. We can form the NOT gate by connecting both NAND input terminals to the
A. different input
B. same input
C. different output
D. same output
MCQ. Gates are the fundamental building blocks of
A. analog circuitry
B. digital circuitry
C. DC circuitry
D. AC circuitry
MCQ. Simplest application of basic gates is
A. data inverter
B. data uploader
C. data updater
D. data selecter
MCQ. If the two inputs are A and B, the output often called Q is ON when
A. A=1, B=0
B. A=0, B=0
C. A=1, B=1
D. A=0, B=1
MCQ. XOR output is 1 if the inputs are
A. same
B. different
C. −∞
D. ∞
MCQ. In digital electronics, the on state is often represented by a
A. 1
B. 0
C. 5V
D. 0V
MCQ. A + ? =
A. 0
B. 1
C. −∞
D. ∞
MCQ. NOT of exclusibe OR gate is called
A. NAND gate
B. NOR gate
C. NXOR gate
D. XOR gate
MCQ. We can easily build an OR gate from
A. one NAND gate
B. two NAND gates
C. three NAND gates
D. four NAND gates
MCQ. The OR gate output is 0 only when
A. A=1, B=0
B. both inputs are zero
C. both inputs are 1
D. A=0, B=1
MCQ. NOT of OR gate is called
A. NAND gate
B. NOR gate
C. NXOR gate
D. XOR gate
MCQ. A x ? =
A. 0
B. 1
C. −∞
D. ∞
MCQ. As a simple application of how these basic logic gates can be combined, we consider the concept of
A. masking
B. determinant
C. sequential circuits
D. circuit analyzing
MCQ. To invert a state in a circuit we use XOR with a mask of
A. 1
B. 0
C. 5V
D. 3.3 V
MCQ. In NOT gate, output w.r.t input is always
A. similar
B. opposite
C. −∞
D. ∞
MCQ. NOT gate has only one input and
A. one output
B. two outputs
C. three outputs
D. four outputs
MCQ. For the AND gate, there are possible combinations of input states are
A. 2
B. 4
C. 8
D. 16
MCQ. XOR gate can be constructed from
A. one NAND gate
B. two NAND gates
C. three NAND gates
D. four NAND gates
MCQ. All gates have two or more than two inputs, except
A. NOR gate
B. NOT gate
C. NXOR gate
D. AND gate
MCQ. System in which a single digital input selects one of two digital streams is called
A. data inverter
B. data uploader
C. data updater
D. data selecter
MCQ. A basic AND gate consists of
A. one input
B. two inputs
C. three inputs
D. four inputs
MCQ. To set a state in a circuit we use OR with a mask of
A. 1
B. 0
C. 5V
D. 3.3 V
MCQ. AND can be defined as two sets
A. intersection
B. union
C. addition
D. subtraction
MCQ. From a pair of two-input AND gates, we can easily implements the
A. two input AND gate
B. three input AND gate
C. four input AND gate
D. five input AND gate
MCQ. Multiplication symbol 'x' is representation of
A. AND
B. NAND
C. OR
D. NOT
Combinational logics
MCQ. Code conversion circuits mostly uses
A. AND-OR gates
B. AND gates
C. OR gates
D. XOR gates
MCQ. Full Adder combinational circuits has 3 inputs and
A. 2 outputs
B. 1 output
C. 3 outputs
D. None
MCQ. The NOR function is the dual of
A. AND function
B. OR function
C. XOR function
D. NAND function
MCQ. Designing combinational circuit involves
A. 4 steps
B. 5 steps
C. 6 steps
D. 8 steps
MCQ. Half adder circuits requires two binary
A. Inputs
B. Outputs
C. Digits
D. Both a and b
MCQ. The subtraction of two binary numbers is accomplished by taking complement of Subtrahend and adding
into
A. output
B. subtract or
C. Minuend
D. remainder
MCQ. Circuits that employs memory elements in addition to gates is called
A. combinational circuit
B. sequential circuit
C. combinational sequence
D. series
MCQ. When both inputs are 1, the output of XOR is
A. 1
B. 0
C. x
D. 10
MCQ. The simplified expression of full adder carry is
A. c=xy+xz+yz
B. c=xy+xz
C. c=xy+yz
D. c=x+y+z
MCQ. Practical design procedure have some
A. gates
B. circuits
C. constraints
D. protocols
MCQ. Half subtractor have an output to specify that 1 has been?
A. complemented
B. borrowed
C. carried
D. primed
MCQ. Logic gates takes input signals and generates signals to
A. within gate
B. input
C. output
D. both a and b
MCQ. For code conversion how many bits are required for BCD input and Excess-3 outputs?
A. 3 inputs and 2 outputs
B. 4 inputs and 4 outputs
C. 4 inputs and 3 outputs
D. None
MCQ. Two bit subtraction is done by
A. Demultiplexer
B. Multiplexer
C. full subtract or
D. half subtract or
MCQ. Dual of the NAND function is
A. AND function
B. OR function
C. NOR function
D. NAND function
MCQ. Besides NAND gate universal gate is
A. AND gate
B. OR gate
C. NOR gate
D. XOR gates
MCQ. The most basic arithmetic function is
A. addition
B. subtraction
C. multiplication
D. division
MCQ. Variable in Boolean expressions can be expressed as
A. primed
B. unprimed
C. even
D. both a and b
MCQ. Circuit that is said to be universal gate is
A. AND
B. OR
C. NAND
D. XOR
MCQ. The connection from output to one of input gate is
A. undefined
B. shifted
C. feedback
D. wire
MCQ. In NAND logic analysis procedure application requires repeated application of
A. truth table
B. feedback theorem
C. demorgan's theorem
D. K-map
wer
MCQ. Circuits whose output depends on directly present input is called
A. combinational circuit
B. sequential circuit
C. combinational sequence
D. series
MCQ. Full subtract circuits have
A. 3 inputs and 2 outputs
B. 1 input and 1 output
C. both a and b
D. None
MCQ. In designing a combinational circuits, truth table defines the relationship of
A. logical circuit
B. input
C. output
D. input and output
MCQ. The most significant bit of arithmetic addition is called
A. overflow
B. carry
C. output
D. zero bit
MCQ. Flip flop are constructed using
A. AND gate
B. OR gate
C. NAND gate
D. NOR gate
MCQ. Two bit addition is done by
A. ripple carry adder
B. carry sum adder
C. full adder
D. half adder
MCQ. AND gates are converted to NAND gates using
A. invert OR
B. AND invert
C. NAND invert
D. both a and b
MCQ. In don't cares map input are marked by
A. 0
B. 1
C. star
D. X
MCQ. OR operation is achieved through a NAND gate with Additional
A. AND gates
B. OR gates
C. XOR gates
D. Inverters
MCQ. The simplified expression of half subtractor borrow is
A. B=x+y
B. B=xy
C. B=x'y
D. B=xy'
MCQ. The analysis of combinational circuits is a
A. Direct Process
B. indirect process
C. Reverse Process
D. None
MCQ. The simplified expression of full subtractor borrow is
A. B=xy+xz+yz
B. B=xy'+xz'+yz
C. B=x'y+xy+xz
D. B=x'y+x'z+yz
MCQ. OR gates are converted to NAND gates using
A. invert OR
B. AND invert
C. NAND invert
D. both a and b
MCQ. To implement the Boolean function with NAND gates we convert the function to
A. AND logic
B. OR logic
C. NOR logic
D. NAND logic

MCQ. Designing combinational circuits we consider?


A. maximum no of gates
B. minimum no of gates
C. two gates
D. three gates
MCQ. Full adder performs addition on
A. 2 bits
B. 3 bits
C. 4 bits
D. 5 bits
Answer
MCQ. When both inputs are different the output of XOR is
A. 1
B. 0
C. x
D. 10
MCQ. The convenient way is to convert NAND logic diagram to
A. AND diagram
B. OR diagram
C. AND-OR diagram
D. NOR diagram
MCQ. The result of two bit subtraction is called?
A. difference bit
B. least significant bit
C. most significant bit
D. carry bit
MCQ. For digital circuits logical circuits can be
A. combinational
B. sequential
C. logical
D. both a and b
MCQ. The truth table can directly be obtained from
A. map
B. logic diagram
C. flow chart
D. expression
MCQ. Rather than AND-OR gates combinational circuits are made by
A. NAND-NOR
B. NAND-OR
C. OR only
D. AND only
MCQ. Combinational circuits are described by
A. Boolean functions
B. algebraic functions
C. geometric functions
D. linear equations
MCQ. Sometimes it is necessary to use the output of one system as the
A. input to another
B. carry to another
C. borrow to another
D. None
MCQ. If two systems have different codes then circuit inserted between them is
A. combinational circuit
B. sequential circuit
C. combinational sequence circuit
D. conversion circuit
MCQ. In the design procedure input output values are assigned with
A. numeric values
B. letter symbols
C. 0's
D. 1's
MCQ. In analysis procedure information processing task is correlated with
A. BCD code
B. excess3 code
C. map
D. truth table
MCQ. The NAND logic conversion is facilitated using symbols of
A. invert OR
B. AND invert
C. NAND invert
D. both a and b
MCQ. The multiple variable XOR operation is defined as
A. inverted or function
B. prime function
C. even function
D. odd function
Combinational Logic Circuits

How many 3-line-to-8-line decoders are required for a 1-of-32 decoder?


A.1
B. 2
C. 4
D. 8
Answer: Option C

2. Which of the figures shown below represents the exclusive-NOR gate?

A.a
B. b
C. c
D. d

3. Which of the circuits in figure (a to d) is the sum-of-products implementation of figure (e)?

A.a
B. b
C. c
D. d

4. For the device shown here, let all D inputs be LOW, both S inputs be HIGH, and the input be LOW.
What is the status of the Y output?

A.LOW
B. HIGH
C. Don't Care
D. Cannot be determined
Answer: Option A

5. For the device shown here, let all D inputs be LOW, both S inputs be HIGH, and the input be HIGH.
What is the status of the Y output?

A.LOW
B. HIGH
C. Don't Care
D. Cannot be determined
Answer: Option A
6. Convert BCD 0001 0010 0110 to binary.
A.1111110
B. 1111101
C. 1111000
D. 1111111
Answer: Option A

7. A 74HC147 priority encoder has ten active-LOW inputs and four active-LOW outputs. What would be the
state of the four outputs if inputs 4 and 5 are LOW and all other inputs are HIGH?
A.
B.

C.
D.
Answer: Option A
8. Convert BCD 0001 0111 to binary.
A.10101
B. 10010
C. 10001
D. 11000
Answer: Option C

9. Which of the figures in figure (a to d) is equivalent to figure (e)?

A.a
B. b
C. c
D. d
Answer: Option B

10. How many data select lines are required for selecting eight inputs?
A.1
B. 2
C. 3
D. 4
Answer: Option C
11. The simplest equation which implements the K-map shown below is:

A.
B.
C.
D.
Answer: Option A

12. How many 1-of-16 decoders are required for decoding a 7-bit binary number?
A.5
B. 6
C. 7
D. 8
Answer: Option D

13. Which of the following logic expressions represents the logic diagram shown?

A.
B.
C.
D.
Answer: Option D
14. The implementation of simplified sum-of-products expressions may be easily implemented into actual logic
circuits using all universal ________ gates with little or no increase in circuit complexity. (Select the response for
the blank space that will BEST make the statement true.)
A.AND/OR
B. NAND
C. NOR
D. OR/AND
Answer: Option B

15. Which of the following statements accurately represents the two BEST methods of logic circuit
simplification?
A.Boolean algebra and Karnaugh mapping
B. Karnaugh mapping and circuit waveform analysis
C. Actual circuit trial and error evaluation and waveform analysis
D. Boolean algebra and actual circuit trial and error evaluation
Answer: Option A
16. For the device shown here, assume the D input is LOW, both S inputs are HIGH, and the input is
HIGH. What is the status of the outputs?

A.All are HIGH.


B. All are LOW.
C. All but are LOW.
D. All but are HIGH.
Answer: Option A

17. Which of the following combinations cannot be combined into K-map groups?
A.Corners in the same row
B. Corners in the same column
C. Diagonal corners
D. Overlapping combinations
Answer: Option C

18. As a technician you are confronted with a TTL circuit board containing dozens of IC chips. You have taken
several readings at numerous IC chips, but the readings are inconclusive because of their erratic nature. Of the
possible faults listed, select the one that most probably is causing the problem.
A.A defective IC chip that is drawing excessive current from the power supply
B. A solar bridge between the inputs on the first IC chip on the board
C. An open input on the first IC chip on the board
D. A defective output IC chip that has an internal open to Vcc
Answer: Option C

19. Which gate is best used as a basic comparator?


A.NOR
B. OR
C. Exclusive-OR
D. AND
Answer: Option C

20. The device shown here is most likely a ________.

A.comparator
B. multiplexer
C. demultiplexer
D. parity generator
Answer: Option C
21. In VHDL, macrofunctions is/are:
A.digital circuits.
B. analog circuits.
C. a set of bit vectors.
D. preprogrammed TTL devices.
Answer: Option D

22. Which of the following expressions is in the product-of-sums form?


A.(A + B)(C + D)
B. (AB)(CD)
C. AB(CD)
D. AB + CD
Answer: Option A

23. Which of the following is an important feature of the sum-of-products form of expressions?
A.All logic circuits are reduced to nothing more than simple AND and OR operations.
B. The delay times are greatly reduced over other forms.
C. No signal must pass through more than two gates, not including inverters.
D. The maximum number of gates that any signal must pass through is reduced by a factor of two.
Answer: Option A

24. For the device shown here, assume the D input is LOW, both S inputs are LOW, and the input is LOW.
What is the status of the outputs?

A.All are HIGH.


B. All are LOW.
C. All but are LOW.
D. All but are HIGH.
Answer: Option D

25. An output gate is connected to four input gates; the circuit does not function. Preliminary tests with the
DMM indicate that the power is applied; scope tests show that the primary input gate has a pulsing signal, while the
interconnecting node has no signal. The four load gates are all on different ICs. Which instrument will best help
isolate the problem?
A.Current tracer
B. Logic probe
C. Oscilloscope
D. Logic analyzer
Answer: Option A
26. The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output
levels?
A.A > B = 1, A < B = 0, A < B = 1
B. A > B = 0, A < B = 1, A = B = 0
C. A > B = 1, A < B = 0, A = B = 0
D. A > B = 0, A < B = 1, A = B = 1
Answer: Option C
27. A logic probe is placed on the output of a gate and the display indicator is dim. A pulser is used on each of
the input terminals, but the output indication does not change. What is wrong?
A.The output of the gate appears to be open.
B. The dim indication on the logic probe indicates that the supply voltage is probably low.
C. The dim indication is a result of a bad ground connection on the logic probe.
D. The gate may be a tristate device.
Answer: Option A
28. Two 4-bit binary numbers (1011 and 1111) are applied to a 4-bit parallel adder. The carry input is 1. What
are the values for the sum and carry output?
A. 4 3 2 1 = 0111, Cout = 0
B. 4 3 2 1 = 1111, Cout = 1
C. 4 3 2 1 = 1011, Cout = 1
D. 4 3 2 1 = 1100, Cout = 1
Answer: Option C
29. Each "1" entry in a K-map square represents:
A.a HIGH for each input truth table condition that produces a HIGH output.
B. a HIGH output on the truth table for all LOW input combinations.
C. a LOW output for all possible HIGH input conditions.
D. a DON'T CARE condition for all possible input truth table combinations.
Answer: Option A
30. Looping on a K-map always results in the elimination of:
A.variables within the loop that appear only in their complemented form.
B. variables that remain unchanged within the loop.
C. variables within the loop that appear in both complemented and uncomplemented form.
D. variables within the loop that appear only in their uncomplemented form.
Answer: Option C
31. What will a design engineer do after he/she is satisfied that the design will work?
A.Put it in a flow chart
B. Program a chip and test it
C. Give the design to a technician to verify the design
D. Perform a vector test
Answer: Option B
32. Based on the indications of probe A in the figure given below, what is wrong, if anything, with the circuit?
A.The logic probe is unable to determine the state of the circuit at that point and is blinking to alert the
technician to the problem.
B. The output appears to be shorted to Vcc, but is being pulsed by the pulser.
C. The output appears to be LOW, but is being pulsed by the pulser.
D. Nothing appears to be wrong at that point.
Answer: Option D
33. What is the indication of a short on the input of a load gate?
A.Only the output of the defective gate is affected.
B. There is a signal loss to all gates on the node.
C. The affected node will be stuck in the LOW state.
D. There is a signal loss to all gates on the node, and the affected node will be stuck in the LOW state.
Answer: Option D
34. In HDL, LITERALS is/are:
A.digital systems.
B. scalars.
C. binary coded decimals.
D. a numbering system.
Answer: Option B
35. Which of the following expressions is in the sum-of-products form?
A.(A + B)(C + D)
B. (AB)(CD)
C. AB(CD)
D. AB + CD
Answer: Option D
36. The carry propagation can be expressed as ________.
A.Cp = AB
B. Cp = A + B
C.
D.
Answer: Option B
37. Which of the K-maps given below represents the expression X = AC + BC + B?
A.a
B. b
C. c
D. d
Answer: Option C
38. A decoder can be used as a demultiplexer by ________.
A.tying all enable pins LOW
B. tying all data-select lines LOW
C. tying all data-select lines HIGH
D. using the input lines for data selection and an enable line for data input
Answer: Option D
39. How many 4-bit parallel adders would be required to add two binary numbers each representing decimal
numbers up through 30010?
A.1
B. 2
C. 3
D. 4
Answer: Option C
40. Which statement below best describes a Karnaugh map?
A.A Karnaugh map can be used to replace Boolean rules.
B. The Karnaugh map eliminates the need for using NAND and NOR gates.
C. Variable complements can be eliminated by using Karnaugh maps.
D. Karnaugh maps provide a visual approach to simplifying Boolean expressions.
Answer: Option D
41. For a two-input XNOR gate, with the input waveforms as shown below, which output waveform is correct?

A.a
B. b
C. c
D. d
Answer: Option D
42. A certain BCD-to-decimal decoder has active-HIGH inputs and active-LOW outputs. Which output goes
LOW when the inputs are 1001?
A.0
B. 3
C. 9
D. None. All outputs are HIGH.
Answer: Option C
43. Solve the network in the figure given below for X.

A.A + BC + D
B. ((A + B)C) + D
C. D(A + B + C)
D. (AC + BC)D
Answer: Option B
44. A full-adder has a Cin = 0. What are the sum ( ) and the carry (Cout) when A = 1 and B = 1?
A. = 0, Cout = 0
B. = 0, Cout = 1
C. = 1, Cout = 0
D. = 1, Cout = 1
Answer: Option B
45. What type of logic circuit is represented by the figure shown below?

A.XOR
B. XNOR
C. XAND
D. XNAND
Answer: Option B
46. The device shown here is most likely a ________.

A.comparator
B. multiplexer
C. demultiplexer
D. parity generator
Answer: Option B
47. The design concept of using building blocks of circuits in a PLD program is called a(n):
A.hierarchical design.
B. architectural design.
C. digital design.
D. verilog.
Answer: Option A
48. When adding an even parity bit to the code 110010, the result is ________.
A.1110010
B. 1111001
C. 110010
D. 001101
Answer: Option A
49. Which of the following combinations of logic gates can decode binary 1101?
A.One 4-input AND gate
B. One 4-input AND gate, one OR gate
C. One 4-input NAND gate, one inverter
D. One 4-input AND gate, one inverter
Answer: Option D
50. What is the indication of a short to ground in the output of a driving gate?
A.Only the output of the defective gate is affected.
B. There is a signal loss to all load gates.
C. The node may be stuck in either the HIGH or the LOW state.
D. The affected node will be stuck in the HIGH state.
Answer: Option B
51. How many outputs would two 8-line-to-3-line encoders, expanded to a 16-line-to-4-line encoder, have?
A.3
B. 4
C. 5
D. 6
Answer: Option B
Sequential Logic Circuits - General Questions

1. A ripple counter's speed is limited by the propagation delay of:


A
each flip-flop
.

B
all flip-flops and gates
.

C
the flip-flops only with gates
.

D
only circuit gates
.
Answer: Option A
To operate correctly, starting a ring counter requires:
A
clearing all the flip-flops
.

B
presetting one flip-flop and clearing all the others
.

C
clearing one flip-flop and presetting all the others
.

D
presetting all the flip-flops
.
Answer: Option B
What type of register would shift a complete binary number in one bit at a time and shift all the
stored bits out one bit at a time?
A
PIPO
.

B
SISO
.

C
SIPO
.

D
PISO
.
Answer: Option B
Synchronous counters eliminate the delay problems encountered with asynchronous (ripple)
counters because the:
A
input clock pulses are applied only to the first and last stages
.

B
input clock pulses are applied only to the last stage
.

C
input clock pulses are not used to activate any of the counter stages
.

D
input clock pulses are applied simultaneously to each stage
.
Answer: Option D
One of the major drawbacks to the use of asynchronous counters is that:
A
low-frequency applications are limited because of internal propagation delays
.

B
high-frequency applications are limited because of internal propagation delays
.

C Asynchronous counters do not have major drawbacks and are suitable for use in high-
. and low-frequency counting applications.

D Asynchronous counters do not have propagation delays, which limits their use in high-
. frequency applications.
Answer: Option B
Which type of device may be used to interface a parallel data format with external equipment's
serial format?
A
key matrix
.

B
UART
.

C
memory chip
.

D serial-in, parallel-out
.
Answer: Option B
When the output of a tri-state shift register is disabled, the output level is placed in a:
A
float state
.

B
LOW state
.

C
high impedance state
.

D
float state and a high impedance state
.
Answer: Option D
A comparison between ring and johnson counters indicates that:
A
a ring counter has fewer flip-flops but requires more decoding circuitry
.

B
a ring counter has an inverted feedback path
.

C
a johnson counter has more flip-flops but less decoding circuitry
.

D
a johnson counter has an inverted feedback path
.
Answer: Option D
A sequence of equally spaced timing pulses may be easily generated by which type of counter
circuit?
A
shift register sequencer
.

B
clock
.

C
johnson
.

D
binary
.
Answer: Option A
What is meant by parallel-loading the register?
A
Shifting the data in all flip-flops simultaneously
.

B
Loading data in two of the flip-flops
.

C Loading data in all four flip-flops at the same time


.

D
Momentarily disabling the synchronous SET and RESET inputs
.
Answer: Option C
What is a shift register that will accept a parallel input and can shift data left or right called?
A
tri-state
.

B
end around
.

C
bidirectional universal
.

D
conversion
.
Answer: Option C
What happens to the parallel output word in an asynchronous binary down counter whenever a
clock pulse occurs?
A
The output word decreases by 1.
.

B
The output word decreases by 2.
.

C
The output word increases by 1.
.

D
The output word increases by 2.
.
Answer: Option A
Mod-6 and mod-12 counters are most commonly used in:
A
frequency counters
.

B
multiplexed displays
.

C
digital clocks
.

D
power consumption meters
.
Answer: Option C

MCQ on Synchronous Sequential Logics


MCQ. A master-slave combination can be constructed for any type of flip-flops by adding a clocked
A. RS Flip-flop with an inverted clock for slave
B. T flip-flop with NAND gate for slave
C. Positive trigger for slave
D. None
MCQ. One that is not the type of flip-flop is
A. JK
B. T
C. RS
D. UT
In the excitation table of D flip-flop the next state is equal to
A. present state
B. next state
C. input state
D. D state
MCQ. The reduction of flip-flops in a sequential circuits are referred as
A. reduction
B. state reduction
C. next state
D. both a and b
MCQ. State table can be represented in a
A. state diagram
B. map
C. truth table
D. graph
MCQ. Sequential circuits consists of
A. combinational circuits
B. sequential circuits
C. logic circuits
D. complex circuits

MCQ. The switch which clears the flip-flop to its initial state is called
A. clock
B. invert
C. hold
D. clear
MCQ. The don't care condition in a table is represented by
A. a
B. b
C. c
D. x
MCQ. How many types a sequential circuits have?
A. 2
B. 5
C. 6
D. None
A MCQ. Master-slave flip-flop consists of
A. 2 flip-flops
B. 3 flip-flops
C. 4 flip-flops
D. 5 flip-flops
MCQ. In Moore models, output are the function of only
A. present state
B. input state
C. next state
D. both a and b
MCQ. Memory elements in clocked sequential circuits are called
A. latches
B. flip-flop
C. signals
D. gates
The design procedure of sequential circuit is based on
A. 7steps
B. 8steps
C. 9steps
D. 10steps
ns MCQ. The state of flip-flop can be switched by changing its
A. input signal
B. output signal
C. momentary signals
D. all signals
w MCQ. The major difference between various types of flip-flops are
A. output that they generate
B. input that they posses
C. gates
D. both a and b
MCQ. The flip-flops can be constructed with two
A. NAND gates
B. XOR gates
C. AND gates
D. NOT gates
MCQ. Unused states are treated as Don't cares conditions during the
A. Design of a circuit
B. Execution
C. Pulse trigger
D. None
e MCQ. The momentary change in the state of flip-flop is called
A. feedback path
B. tri state
C. signals
D. trigger
MCQ. The positive transition in flip-flops is referred as
A. clock
B. negative edge
C. positive edge
D. both a and b
MCQ. Feedback among logic gates make asynchronous system
A. stable
B. unstable
C. complex
D. combinational
MCQ. Clocked flip-flops are triggered by
A. feedback path
B. pulses
C. signals
D. clear
MCQ. Direct coupled RS flip-flops are also called
A. RS latch
B. SR latch
C. TS latch
D. ST latch
MCQ. Sequential circuits are
A. Synchronous
B. Asynchronous
C. signals
D. both a and b
MCQ. The behavior of sequential circuits are determined by the state of their
A. clock
B. pulses
C. flip-flops
D. trigger
MCQ. The definite time in a flip-flop is called
A. clear time
B. pulse time
C. hold time
D. reset time
MCQ. JK Master-slave flip-flops are constructed with
A. NAND gates
B. OR gates
C. AND gates
D. NOT gates
MCQ. The operation of basic flip-flop can be changed by providing some additional control
A. Input
B. Output
C. Inverter
D. None
MCQ. M flip-flops produces
A. 2^m-1 states
B. 2-1 states
C. 2^m+1 states
D. 2^m states
MCQ. The state of flip-flops are initialized with
A. reset input
B. master input
C. master reset input
D. both a and b
MCQ. A counter that flows the binary sequence is called
A. ripple counter
B. edge counter
C. binary counter
D. level counter
MCQ. The next state of B(t) will be
A. B(t-1)
B. B(t+1)
C. B(t-2)
D. B(t+2)
MCQ. In Mealy models output are the functions of both
A. present state
B. input state
C. next state
D. both a and b
In T flip-flop when state of the T flip-flop has to be complemented the T must be
A. 0
B. 1
C. t
D. t+1
MCQ. A synchronous sequential circuit is made up of
A. combinational gates
B. flip-flops
C. latches
D. both a and b
MCQ. The next state of the D flip-flop is dependent on
A. state diagram
B. present state
C. input state
D. D state
MCQ. The time sequence for flip-flop can be enumerated by
A. state table
B. map
C. truth table
D. graph
MCQ. Synchronous sequential circuits that uses clock are called
A. clocked sequential circuits
B. sequential circuits
C. logic circuits
D. complex circuits
MCQ. Two states are said to be equal if they have exactly same
A. inputs
B. next state
C. output
D. both a and b
MCQ. The implication table consists of
A. squares
B. triangles
C. cubes
D. circles
MCQ. Table that lists the inputs for required change of states is called
A. truth table
B. excitation table
C. state table
D. clock table
MCQ. A circuit that goes through prescribed sequence of state is called
A. flip-flops
B. truth tables
C. latches
D. counters
MCQ. Classification of sequential circuits depends upon their timing of
A. feedback path
B. gates
C. signals
D. complex circuits
MCQ. Which state a flip-flop circuits can maintain as long as a power is delivered to the circuit?
A. n states
B. tri state
C. binary state
D. octa state
MCQ. The negative transition in flip-flops are referred as
A. clock
B. negative edge
C. positive edge
D. both a and b
MCQ. Clock generator, generates periodic train of
A. feedback path
B. gates
C. clock pulses
D. both a and b
MCQ. Flip-flops are sensitive to
A. feedback path
B. pulses
C. signals
D. pulse transition
MCQ. A flip-flop circuit can be constructed by two NAND gates or
A. with Two AND gates
B. with Two OR Gates
C. with Two NOR gates
D. None
MCQ. One that is not stated in a state table is
A. present state
B. next state
C. input state
D. clock state
MCQ. In the last step of design procedure we
A. draw map
B. draw circuit
C. draw table
D. draw a logic diagra
MCQ. The state diagram provides the same information as the
A. flip-flops provides
B. State table provides
C. truth table provides
D. both a and b

Digital Circuits Questions and Answers – Introduction of


Memory Devices – 1
This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Introduction of
Memory Devices – 1”.

1. Memory is a/an
a) Device to collect data from other computer
b) Block of data to keep data separately
c) Indispensable part of computer
d) Device to connect through all over the world
View Answer
Answer: c
Explanation: Memory is an indispensable unit of a computer and microprocessor based systems.
2. The instruction used in a program for executing them, is stored in the
a) CPU
b) Control Unit
c) Memory
d) Microprocessor
View Answer
Answer: c
Explanation: All of the program and the instructions are stored in the memory.
3. A flip flop stores
a) 10 bit of information
b) 1 bit of information
c) 2 bit of information
d) None of the Mentioned
View Answer
Answer: b
Explanation: A flip-flop has capability to store 1 bit of information. It can be used further after erasing previous
information.
4. A register is able to hold
a) Data
b) Word
c) Nibble
d) Both data and word
View Answer
Answer: b
Explanation: Register is also a part of memory inside a computer. It stands there to hold a word.
5. A register file holds
a) A large number of word of information
b) A small number of word of information
c) A large number of programs
d) A modest number of words of information
View Answer
Answer: d
Explanation: A register file is different from a simple register because of capability to hold a modest number of
words of information.
6. The very first computer memory consisted of
a) A small display
b) A large memory storage equipment
c) An automatic keyboard input
d) None of the Mentioned
View Answer
Answer: b
Explanation: The very first computer memory consisted of a minute magnetic toroid, which required large, bulky
circuit boards stored in large cabinates.
7. A minute magnetic toroid is also called as
a) Large memory
b) Small memory
c) Core memory
d) Both small and large memory
View Answer
Answer: c
Explanation: A minute magnetic toroid is also called as core memory which is made up of a semiconductor.
8. Which one of the following has capability to store data in extremely high densities?
a) Register
b) Capacitor
c) Semiconductor
d) None of the Mentioned
View Answer
Answer: c
Explanation: Semiconductor has capability to store data in extremely high densities.
9. A large memory is compressed into a small one by using
a) LSI semiconductor
b) VLSI semiconductor
c) CDR semiconductor
d) None of the Mentioned
View Answer
Answer: b
Explanation: VLSI (Very Large Scale Integration) semiconductor is used in modern computers to short the size of
memory.
10. VLSI chip utilizes
a) NMOS
b) CMOS
c) BJT
d) All of the Mentioned
View Answer
Answer: d
Explanation: VLSI is a memory chip which is made up of NMOS, CMOS, BJT, and BiCMOS.
11. CD-ROM refers to
a) Floppy disk
b) Compact Disk-Read Only Memory
c) Compressed Disk-Read Only Memory
d) None of the Mentioned
View Answer
Answer: b
Explanation: CD-ROM refers to Compact Disk-Read Only Memory.
12. Data stored in an electronic memory cell can be accessed at random and on demand using
a) Memory addressing
b) Direct addressing
c) Indirect addressing
d) Control Unit
View Answer
Answer: b
Explanation: Direct addressing eliminates the need to process a large stream of irrelevant data in order to the desired
data word.
13. The full form of PLD is
a) Programmable Large Device
b) Programmable Long Device
c) Programmable Logic Device
d) None of the Mentioned
View Answer
Answer: c
Explanation: The full form of PLD is Programmable Logic Device.
14. The evolution of PLD began with
a) EROM
b) RAM
c) PROM
d) EEPROM
View Answer
Answer: a
Explanation: The evolution of PLD began with Programmable Read Only Memory (i.e. PROM).
15. A ROM is defined as
a) Read Out Memory
b) Read Once Memory
c) Read Only Memory
d) None of the Mentioned
View Answer
Answer: c
Explanation: A ROM is defined as Read Only Memory which can read the instruction stored in a computer.

Discrete Mathematics Questions and Answers – Cardinality of Sets

This set of Discrete Mathematics Questions and Answers for Aptitude test focuses on “Cardinality of Sets”.

1. The cardianlity of the set A = {1, 2, 3, 4, 6} is:


a) 5
b) 6
c) Integer
d) None of the mentioned
View Answer
Answer: a
Explanation: 5, it is number of elements in the sets.
2. For two equal sets there:
a) Cardinality is same
b) Cardinality is different
c) May be same or different
d) None of the mentioned
View Answer
Answer: a
Explanation: Two equal sets should have same number of elements.
3. If A is a subset of B:
a) Cardinality of A is greater than B
b) Cardinality of B is greater than A
c) Can’t say
d) None of the mentioned
View Answer
Answer: b
Explanation: B contains all the elements of A, as well as other elements.
4. If there is bijection between two sets A and B then :
a) Cardinality of A is greater than B
b) Cardinality of B is greater than A
c) Cardinality of B is equal to A
d) None of the mentioned
View Answer
Answer: c
Explanation: If there is bijection then two sets A and B will be equinumerous and thus will have same cardinality.
5. Let a set E ={0,2,4,6,8….} of non-negative even numbers and O = {1, 3, 5, 7, 9,…..} of non-negative odd
numbers then :
a) Cardinality of set E is greater thanthat of O
b) Cardinality of set O is greater than that of E
c) Cardinality of set E is equal to that of O
d) None of the mentioned
View Answer
Answer: c
Explanation: There is bijection then two sets E and O and they will be equinumerous and thus will have same
cardinality.
6. State whether the given statement is true or false
Cardinality of the set of lower letter english alphabets is 26.
a) True
b) False
View Answer
Answer: a
Explanation: From a, b, c…z there will be 26 elements.
7. Cardinality of the set of even prime number under 10 is 4.
a) True
b) False
View Answer
Answer: b
Explanation: Since 2 is only even prime thus cardinality should be 1.
8. If for sets A and B there exists a injective function but not bijective function from A to B then:
a) Cardinality of A is stricly greater than B
b) Cardinality of B is strictly greater than A
c) Cardinality of B is equal to A
d) None of the mentioned
View Answer
Answer: b
Explanation: If there doesnot exist a bijective function from A to B that means there are some elements in B whose
preimage is not in A, thus cardinality of B is strictly greater than A.
9. If cardinality of (A U B) = cardinality of A+ cardinality of B. This means:
a) A is a subset of B
b) B is a subset of A
c) A and B are disjoint
d) None of the mentioned
View Answer
Answer: c
Explanation: Thus if cardinality of (A U B) = cardinality of A+ cardinality of B ,it means they don’t have any
element in common, n(A∩B) = 0.
10. If A is a subset of B and B is a subset of C,then cardinaity of A U B U C is equal to :
a) Cardinality of C
b) Cardinality of B
c) Cardinality of A
d) None of the mentioned
View Answer
Answer: a
Explanation: A U B U C = C, since a, b are subsets to C.

Discrete Mathematics Questions and Answers – Types of Set

This set of Discrete Mathematics Multiple Choice Questions & Answers (MCQs) focuses on “Types of Set”.

1. {x: x is an integer neither positive nor negative} is


a) Empty set
b) Non- empty set
c) Finite set
d) Both b and c
View Answer
Answer: d
Explanation: Set = {0} non-empty and finite set.
2. {x: x is a real number between 1 and 2} is an
a) Infinite set
b) Finite set
c) Empty set
d) None of the mentioned
View Answer
Answer: a
Explanation: It is an infinite set as there are infinitely many real number between any two different real numbers.
3. Write set {1, 5, 15, 25,…} in set-builder form :
a) {x: either x=1 or x=5n, where n is a real number}
b) {x: either x=1 or x=5n, where n is a integer}
c) {x: either x=1 or x=5n, where n is an odd natural number}
d) {x: x=5n, where n is a natural number}
View Answer
Answer: c
Explanation: Set should include 1 or an odd multiple of 5.
4. Express {x: x= n/ (n+1), n is a natural number less than 7} in roster form:
a) {1⁄2, 2⁄3, 4⁄5, 6⁄7}
b) {1⁄2, 2⁄3, 3⁄4, 4⁄5, 5⁄6, 6⁄7, 7⁄8}
c) {1⁄2, 2⁄3, 3⁄4, 4⁄5, 5⁄6, 6⁄7}
d) Infinite set
View Answer
Answer: c
Explanation: n/(n+1) = 1/(1+1) = 1⁄2 and n>7.
5. Number of power set of {a, b}, where a and b are distinct elements.
a) 3
b) 4
c) 2
d) 5
View Answer
Answer: b
Explanation: Power set of {a, b} = {∅, {a, b}, {a}, {b}}.
6. Which of the following is subset of set {1, 2, 3, 4}.
a) {1, 2}
b) {1, 2, 3}
c) {1}
d) All of the mentioned
View Answer
Answer: d
Explanation: There are total 16 subsets.
7. A = {∅,{∅},2,{2,∅},3} ,which of the following is true.
a) {{∅,{∅}} ∈ A
b) {2} ∈ A
c) ∅ ⊂ A
d) 3 ⊂ A
View Answer
Answer: c
Explanation: Empty set is a subset of every set.
8. Subset of the set A= { } is:
a) A
b) {}
c) ∅
d) All of the mentioned
View Answer
Answer: d
Explanation: Every set is subset of itself and Empty set is subset of each set.
9. {x: x ∈ N and x is prime} then it is:
a) Infinite set
b) Finite set
c) Empty set
d) Not a set
View Answer
Answer: a
Explanation: There is no extreme prime, number of primes is infinite.
10. Convert set {x: x is a positive prime number which divides 72} in roster form:
a) {2, 3, 5}
b) {2, 3, 6}
c) {2, 3}
d) {∅}
View Answer
Answer: c
Explanation: 2 and 3 are the divisors of 72 which are prime.

iscrete Mathematics Questions and Answers – Sets

This set of Discrete Mathematics Multiple Choice Questions & Answers (MCQs) focuses on “Sets”.

1. A __________ is an ordered collection of objects.


a) Relation
b) Function
c) Set
d) Proposition
View Answer
Answer: c
Explanation: By the definition of set.
2. The set O of odd positive integers less than 10 can be expressed by _____________
a) {1, 2, 3}
b) {1, 3, 5, 7, 9}
c) {1, 2, 5, 9}
d) {1, 5, 7, 9, 11}
View Answer
Answer: b
Explanation: Odd numbers less than 10 is {1, 3, 5, 7, 9}.
3. Power set of empty set has exactly _________ subset.
a) One
b) Two
c) Zero
d) Three
View Answer
Answer: a
Explanation: Power set of null set has exactly one subset which is empty set.
4. What is the Cartesian product of A = {1, 2} and B = {a, b}?
a) {(1, a), (1, b), (2, a), (b, b)}
b) {(1, 1), (2, 2), (a, a), (b, b)}
c) {(1, a), (2, a), (1, b), (2, b)}
d) {(1, 1), (a, a), (2, a), (1, b)}
View Answer
Answer: c
Explanation: A subset R of the Cartesian product A x B is a relation from the set A to the set B.
5. The Cartesian Product B x A is equal to the Cartesian product A x B. Is it True or False?
a) True
b) False
View Answer
Answer: b
Explanation: Let A = {1, 2} and B = {a, b}. The Cartesian product A x B = {(1, a), (1, b), (2, a), (2, b)} and the
Cartesian product B x A = {(a, 1), (a, 2), (b, 1), (b, 2)}. This is not equal to A x B.
6. What is the cardinality of the set of odd positive integers less than 10?
a) 10
b) 5
c) 3
d) 20
View Answer
Answer: b
Explanation: Set S of odd positive an odd integer less than 10 is {1, 3, 5, 7, 9}. Then, Cardinality of set S = |S| which
is 5.
7. Which of the following two sets are equal?
a) A = {1, 2} and B = {1}
b) A = {1, 2} and B = {1, 2, 3}
c) A = {1, 2, 3} and B = {2, 1, 3}
d) A = {1, 2, 4} and B = {1, 2, 3}
View Answer
Answer: c
Explanation: Two set are equal if and only if they have the same elements.
8. The set of positive integers is _____________
a) Infinite
b) Finite
c) Subset
d) Empty
View Answer
Answer: a
Explanation: The set of positive integers is not finite.
9. What is the Cardinality of the Power set of the set {0, 1, 2}.
a) 8
b) 6
c) 7
d) 9
View Answer
Answer: a
Explanation: Power set P ({0, 1, 2}) is the set of all subsets of {0, 1, 2}. Hence,P({0, 1, 2}) = {null , {0}, {1}, {2},
{0, 1}, {0,2}, {1, 2}, {0, 1, 2}}.
10. The members of the set S = {x | x is the square of an integer and x < 100} is ________________
a) {0, 2, 4, 5, 9, 58, 49, 56, 99, 12}
b) {0, 1, 4, 9, 16, 25, 36, 49, 64, 81}
c) {1, 4, 9, 16, 25, 36, 64, 81, 85, 99}
d) {0, 1, 4, 9, 16, 25, 36, 49, 64, 121}
View Answer
Answer: b
Explanation: The set S consists of the square of an integer less than 10.

Discrete Mathematics Questions and Answers – Set Operations


This set of Discrete Mathematics Multiple Choice Questions & Answers (MCQs) focuses on “Set Operations”.

1. The union of the sets {1, 2, 5} and {1, 2, 6} is the set _______________
a) {1, 2, 6, 1}
b) {1, 2, 5, 6}
c) {1, 2, 1, 2}
d) {1, 5, 6, 3}
View Answer
Answer: b
Explanation: The union of the sets A and B, is the set that contains those elements that are either in A or in B.
2. The intersection of the sets {1, 2, 5} and {1, 2, 6} is the set _____________
a) {1, 2}
b) {5, 6}
c) {2, 5}
d) {1, 6}
View Answer
Answer: a
Explanation: The intersection of the sets A and B, is the set containing those elements that are in both A and B.
3. Two sets are called disjoint if there _____________ is the empty set.
a) Union
b) Difference
c) Intersection
d) Complement
View Answer
Answer: c
Explanation: By the definition of the disjoint set.
4. Which of the following two sets are disjoint?
a) {1, 3, 5} and {1, 3, 6}
b) {1, 2, 3} and {1, 2, 3}
c) {1, 3, 5} and {2, 3, 4}
d) {1, 3, 5} and {2, 4, 6}
View Answer
Answer: d
Explanation: Two sets are disjoint if the intersection of two sets is the empty set.
5. The difference of {1, 2, 3} and {1, 2, 5} is the set ____________
a) {1}
b) {5}
c) {3}
d) {2}
View Answer
Answer: c
Explanation: The difference of the sets A and B denoted by A-B, is the set containing those elements that are in A
not in B.
6. The complement of the set A is _____________
a) A – B
b) U – A
c) A – U
d) B – A
View Answer
Answer: b
Explanation: The complement of the set A is the complement of A with respect to U.
7. The bit string for the set {2, 4, 6, 8, 10} (with universal set of natural numbers less than or equal to 10) is
____________________
a) 0101010101
b) 1010101010
c) 1010010101
d) 0010010101
View Answer
Answer: a
Explanation: The bit string for the set has a one bit in second, fourth, sixth, eighth, tenth positions, and a zero
elsewhere.
8. Let Ai = {i, i+1, i+2, …..}. Then set {n, n+1, n+2, n+3, …..} is the _________ of the set Ai.
a) Union
b) Intersection
c) Set Difference
d) Disjoint
View Answer
Answer: b
Explanation: By the definition of the generalized intersection of the set.
9. The bit strings for the sets are 1111100000 and 1010101010. The union of these sets is ___________
a) 1010100000
b) 1010101101
c) 1111111100
d) 1111101010
View Answer
Answer: d
Explanation: The bit string for the union is the bitwise OR of the bit strings.
10. The set difference of the set A with null set is __________
a) A
b) null
c) U
d) B
View Answer
Answer: a
Explanation: The set difference of the set A by null set denoted by A – {null} is A.

iscrete Mathematics Questions and Answers – Set Operations – 2

This set of Discrete Mathematics Interview Questions and Answers focuses on “Set Operations – 2”.

1. Let the set A is {1, 2, 3} and B is {2, 3, 4}. Then number of elements in A U B is
a) 4
b) 5
c) 6
d) 7
View Answer
Answer: a
Explanation: AUB is {1, 2, 3, 4}.
2. Let the set A is {1, 2, 3} and B is { 2, 3, 4}. Then number of elements in A ∩ B is
a) 1
b) 2
c) 3
d) 4
View Answer
Answer: b
Explanation: A ∩ B is {2, 3}.
3. Let the set A is {1, 2, 3} and B is {2, 3, 4}. Then the set A – B is
a) {1, -4}
b) {1, 2, 3}
c) {1}
d) {2, 3}
View Answer
Answer: c
Explanation: In A – B the common elements get cancelled.
4. In which of the following sets A- B is equal to B – A
a) A= {1, 2, 3}, B ={2, 3, 4}
b) A= {1, 2, 3}, B ={1, 2, 3, 4}
c) A={1, 2, 3}, B ={2, 3, 1}
d) A={1, 2, 3, 4, 5, 6}, B ={2, 3, 4, 5, 1}
View Answer
Answer: c
Explanation: A- B= B-A = Empty set.
5. Let A be set of all prime numbers, B be the set of all even prime numbers, C be the set of all odd prime numbers,
then which of the following is true?
a) A ≡ B U C
b) B is a singleton set.
c) A ≡ C U {2}
d) All of the mentioned
View Answer
Answer: d
Explanation: 2 is the only even prime number.
6. If A has 4 elements B has 8 elements then the minimum and maximum number of elements in A U B are
respectively
a) 4, 8
b) 8, 12
c) 4, 12
d) None of the mentioned
View Answer
Answer: b
Explanation: Minimum would be when 4 elements are same as in 8, maximum would be when all are distinct.
7. If A is {{Φ}, {Φ, {Φ}}, then the power set of A has how many element?
a) 2
b) 4
c) 6
d) 8
View Answer
Answer: b
Explanation: The set A has got 2 elements so n(P(A))=4.
8. Two sets A and B contains a and b elements respectively .If power set of A contains 16 more elements than that of
B, value of ‘b’ and ‘a’ are respectively
a) 4, 5
b) 6, 7
c) 2, 3
d) None of the mentioned
View Answer
Answer: a
Explanation: 32-16=16, hence a=5, b=4.
9. Let A be {1, 2, 3, 4}, U be set of all natural numbers, then U-A’(complement of A) is given by set.
a) {1, 2, 3, 4, 5, 6, ….}
b) {5, 6, 7, 8, 9, ……}
c) {1, 2, 3, 4}
d) All of the mentioned
View Answer
Answer: c
Explanation: U – A’ ≡ A.
10. Which sets are not empty?
a) {x: x is a even prime greater than 3}
b) {x : x is a multiple of 2 and is odd}
c) {x: x is an even number and x+3 is even}
d) { x: x is a prime number less than 5 and is odd}
View Answer
Answer: d
Explanation: Because the set is {3}.