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ALU:

module alu(a,b,s,y);
input[3:0]a;
input[3:0]b;
input[2:0]s;
output[7:0]y;
reg[7:0]y;
always@(a,b,s)
begin
case(s)
3'b000:y=a+b;
3'b001:y=a-b;
3'b010:y=a&b;
3'b011:y=a|b;
3'b100:y=4'b1111^a;
3'b101:y=(4'b1111^a)+1'b1;
3'b110:y=a*b;
3'b111:begin y=a;
y=y>>1'b1;
end
endcase
end
endmodule

TESTBENCH:
initial begin
a=4'b1101; b=4'b1001;
s=3'b000;
#100 s=3'b001;
#100 s=3'b010;
#100 s=3'b011;
#100 s=3'b100;
#100 s=3'b101;
#100 s=3'b110;
#100 s=3'b111;
end
initial
#1000 $stop;
Endmodule
SISO:
module siso(clk,rst,a,q);
input a;
input clk,rst;
output q;
reg q;
always@(posedge clk,posedge rst)
begin
if(rst==1'b1)
q<=1'b0;
else
q<=a;
end
endmodule
TESTBENCH:
initial
clk=1'b1;
always #10 clk=~clk;
initial begin
a=1'b0;rst=1'b1;
#100 rst=1'b0;
#100 a=1'b1;
#100 rst=1'b1;
#100 rst=1'b0;
end
initial
#1000 $stop;
Endmodule
PIPO:
module pipo(clk,rst,a,q);
input clk,rst;
input[3:0]a;
output[3:0]q;
reg[3:0]q;
always@(posedge clk,posedge rst)
begin
if (rst==1'b1)
q<=4'b0000;
else
q<=a;
end
endmodule
TESTBENCH:
initial
clk='b1;
always #10 clk=~clk;
initial begin
a=4'b1101;rst=1'b1;
#100 rst=1'b0;
#100 a=4'b1000;
#100 rst=1'b1;
#100 rst=1'b0;
end
initial
#600 $stop;

Endmodule

SIPO:
module sipo(a,clk,rst,q);
input clk,rst;
input a;
output [3:0]q;
wire [3:0]q;
reg [3:0]temp;
always@(posedge clk,posedge rst)
begin
if(rst==1'b1)
temp<=4'b0000;
else
begin
temp<=temp<<1'b1;
temp[0]<=a;
end
end
assign q=temp;
endmodule
TESTBENCH:
initial
clk=1'b0;
always #10 clk=~clk;
initial begin
rst=1'b1; a=1'b1;
#500 rst=1'b0;
#100 a=1'b0;
#100 a=1'b1;
#100 a=1'b0;
#100 a=1'b0;
#100 a=1'b1;
#100 a=1'b0;
end
initial
#1300 $stop;
endmodule
PISO:
module piso(clk,rst,a,q);
input clk,rst;
input [3:0]a;
output q;
reg q;
reg [3:0]temp;
always@(posedge clk,posedge rst)
begin
if(rst==1'b1)
begin
q<=1'b0;
temp<=a;
end
else
begin
q<=temp[0];
temp <= temp>>1'b1;
end
end
endmodule
TESTBENCH:
initial
clk=1'b1;
always #10 clk=~clk;
initial begin
rst=1'b1; a=4'b1101;
#300 rst=1'b0;
#200 rst=1'b1;
#200 rst=1'b0;
end
initial
#1000 $stop;

endmodule
// File : Serial IN Parallel OUT Shift Register using Behavior Modeling
Style.v

module SIPO ( din ,clk ,reset ,dout );

output [3:0] dout ;


wire [3:0] dout ;

input din ;
wire din ;
input clk ;
wire clk ;
input reset ;
wire reset ;

reg [3:0]s;

always @ (posedge (clk)) begin


if (reset)
s <= 0;
else begin
s[3] <= din;
s[2] <= s[3];
s[1] <= s[2];
s[0] <= s[1];
end
end

assign dout = s;

endmodule
-----------------------------------------------------------------------------
answer
--------------------------------------------------------------------------------
`timescale 1ns / 1ps
module uni_shift_4b(op,clk,rst_a, load,sh_ro_lt_rt,ip);
output reg [3:0] op;
input load;
input [1:0] sh_ro_lt_rt;
input [3:0] ip;
input clk, rst_a;

reg [3:0]temp;

always @(posedge clk or posedge rst_a)


begin
if (rst_a)

op = 0;

else
case(load)
1'b1:
begin //Load Input
temp = ip;
// op = temp;
end
1'b0: //Operation
case (sh_ro_lt_rt)
2'b00: op = temp<<1; //Left Shift
2'b01: op = temp>>1; //Right Shift
2'b10: op = {temp[2:0],temp[3]}; //Rotate Left
2'b11: op = {temp[0], temp[3:1]}; //Rotate Right

default: $display("Invalid Shift Control Input");


endcase

default: $display("Invalid Load Control Input");


endcase

end

endmodule

----------------------------------
tb------------
------------------------------------
`timescale 1ns/1ps

module uni_shift_8b_tst;
reg [3:0] ip;
reg [1:0] sh_ro_lt_rt;
reg load,rst_a,clk;
wire [3:0] op;

uni_shift_4b u1 (.op(op), .ip(ip), .sh_ro_lt_rt(sh_ro_lt_rt), .load(load) ,


.rst_a(rst_a) , .clk(clk));

initial
begin
clk=1'b1;
forever #50 clk=~clk;
end

initial
begin
ip = 4'b1011;
rst_a = 1'b0;
load = 1'b0;
sh_ro_lt_rt = 2'b11;
#100;

ip =4'b1011;
rst_a = 1'b0;
load = 1'b1;
sh_ro_lt_rt = 2'b00 || 2'b01 ||2'b10 ||2'b11 ;
#100;

ip =4'b1011;
load = 1'b1;
sh_ro_lt_rt = 2'b00 || 2'b01 ||2'b10 ||2'b11 ;
#100;

ip = 4'b1011;
load = 1'b0;
sh_ro_lt_rt = 2'b10;
#100;
ip = 4'b1011;
load = 1'b0;
sh_ro_lt_rt = 2'b00;
#100;

ip = 4'b1011;
load = 1'b0;
sh_ro_lt_rt = 2'b01;
#100;

ip = 4'b1011;
load = 1'b0;
sh_ro_lt_rt = 2'b10;
#100;

ip = 4'b1011;
load = 1'b0;
sh_ro_lt_rt = 2'b11;
#100;

ip = 4'b1011;
load = 1'b0;
sh_ro_lt_rt = 2'b00;
#100;

ip = 4'b1001;
load = 1'b0;
sh_ro_lt_rt = 2'b00;
#100;

ip = 4'b1001;
load = 1'b1;
sh_ro_lt_rt = 2'b00;
#100;

ip = 4'b1001;
load = 1'b0;
sh_ro_lt_rt = 2'b00;
#100;

ip = 4'b1001;
load = 1'b0;
sh_ro_lt_rt = 2'b01;
#100;

ip = 4'b1001;
load = 1'b0;
sh_ro_lt_rt = 2'b10;
#100;

ip = 4'b1001;
load = 1'b0;
sh_ro_lt_rt = 2'b11;
#100;

end // initial begin


endmodule