DESIGN OF A NOVEL REGULATED CASCODE

CURRENT MIRROR
A
Dissertation
Submitted in partial fulfillment of the requirements
For the award ofdegree

Of
Master of Technology
In

Embedded System Design

Submitted by
DEVENDRA JAKHAR
Roll No-3136522
Under the Guidance of
Mr.GAURAVSAINI
(Assistant Professor, Department of ECE)

SCHOOL OF VLSI DESIGN AND EMBEDDED SYSTEMS

NATIONAL INSTITUTE OF TECHNOLOGY
KURUKSHETRA-I36119
SESSION 2014-2015
 </0
'jqv\ 'I
Si- vy/^
 SCHOOL OF VLSI DESIGN AND EMBEDDED SYSTEMS
NATIONAL INSTITUTE OF TECHNOLOGY
KURUKSHETRA -136119

CANDIDATE'S DECLARATION
I hereby certify that the work which is being presented in the thesis, entitled "Design
of a novel regulated cascode current mirror" is submitted to School of VLSI Design
and Embedded Systems at National Institute of Technology, Kurukshetra in the partial
fulJBUment of the requirements for the award of the degree of Master of Technology in
Embedded System Design. This dissertation is an authentic record of my own work carried
out during July 2014 to June 2015 under the guidance of Mr. Gaurav Saini, Assistant
Professor, Department of Electronics and Communication Engineering, National Institute
of Technology, Kurukshetra.
The matter embodied in this dissertation has not been submitted by me to any
other University/Institute for the award of any Degree or Diploma.

DEVENDRA JAKH AR
This is to certify that the above statehient made by the candidate is correct to the best of
my knowledge.

Supervisor
Mr. Gaurav Saini
Assistant Professor
Department of ECE
NIT Kurukshetra

Date: External Examiner

 ACKNOWLEDGEMENT

I would like to express my deep gratitude and appreciation to all the people who have
helped and supported me in the process of this dissertation.

First of all, I would like to express my deep and sincerest gratitude to my supervisor, Mr.
Gaurav Saini, Asst. Professor, Department of Electronics and Communication Engineering,
NIT Kurukshetra for giving me the opportunity to do my master's dissertation on this
important and interesting topic under his guidance. I am very thankful for his support,
motivation, patience, and guidance during the study. His professional knowledge and faith
in me were very important and gave me the strength to conclude this work.

I would like to thank Dr. A.K. Gupta, Professor, Department of Electronics and
Communication Engineering and Coordinator of School of VLSI Design and Embedded
System, NIT Kurukshetra for giving his valuable suggestions during mid semester
evaluation of the dissertation work.

I would also like to thank Dr. R. K. Sharma, Professor, Department of Electronics and
Communication Engineering, NIT Kurukshetra. I am highly obliged to him for allowing us
to use 24 hours lab facility which helped me a lot in completing my dissertation work in
time.

Finally, I dedicate this dissertation to my parents for their understanding, patience and
encouragement through all these years. This work would have not been possible without
their support.

.rUsiA ,JeL^^
DEVENDRA JAKHAR
School of VLSI Design and Embedded Systems

National Institute of Technology

Kurukshetra
 ABSTRACT
The main objective of this dissertation is to provide high output impedance current mirror
circuit. In this dissertation, we propose two techniques named "A novel regulated cascode
current mirror" and "High output impedance regulated cascode current mirror". These two
techniques will provide high output impedance than previously reported current mirror
circuits. "A novel regulated cascode current mirror" technique will improve output
unpedance approximately three times and power dissipation is same as existing regulated
cascode current mirror at the cost of high systematic gain error. The output current is
mirrored with a transfer error less than 1 % when the input current is increased from 0 to
20p,A. "High output impedance regulated cascode current mirror" technique will improve
output impedance approximately two times higher and power dissipation is same as the
existing regulated cascode current mirror at the cost of increase in the systematic gain error.
The output current is mirrored with a transfer error less than 1% when the input current is
increased from 0 to 20 |iA. To improve the output impedance more effectively, we use
cascode stage in proposed techniques but it increases systematic gain error simultaneously.
The proposed techniques can be used for low power applications such as portable device,
sensors and Bio-medical instruments etc.
 TABLE OF CONTENTS
Page No

CERTIFICATE i

ACKNOWLEDGEMENT ii

ABSTRACT iii

TABLE OF CONTENTS iv

LIST OF FIGURES vi

LIST OF TABLES ix

LIST OF SYMBOLS ix

LIST OF ABBREVIATIONS x

CHAPTER-!: INTRODUCTION

1.1 Motivation 1

1.2 Research objective 1

1.3 Thesis organization 2

CHAPTER-2: LITERATURE REVIEW

2.1 Current mirror characteristics 4

2.1.1 Input-Output resistance 4

2.1.2 Input linear range 4

2.1.3 Compliance voltage 4

2.1.4 DC balance 4

2.1.5 Finite Bandwidth 5

2.1.6 Device matching 5

2.2 Different types of current mirror 5

2.2.1 Simple current mirror 5

2.2.1.1 Output impedance analysis 7

 2.2.2 Cascode current mirror 9

2.2.2.1 Output impedance analysis 9

2.2.3 Wilson current mirror 11

2.2.3.1 Output impedance analysis 12

2.2.4 Improved Wilson current mirror 14

2.2.4.1 Output impedance analysis 15

2.2.5 Regulated cascode current mirror 17

2.2.5.1 Output impedance analysis 18

CHAPTER-3: DESIGN AND ANALYSIS OF PROPOSED CURRENT MIRROR

STRUCTURE

3.1 A novel regulated cascode current mirror 20

3.1.1 Output impedance analysis 21

3.2 High output impedance regulated cascode current mirror 25

3.2.1 Output impedance analysis 26

CHAPTER-4: SIMULATION RESULTS

4.1 Simple current mirror 30

4.2 Cascode current mirror 33

4.3 Wilson current mirror 36

4.4 Improved Wilson current mirror 39

4.5 Regulated cascode current mirror 42

4.6 A novel regulated cascode current mirror 45

4.7 High output impedance regulated cascode current mirror 48

CHAPTER-5: CONCLUSION

5.1 Conclusion 52

5.2 Future scope 52

REFERENCES 53

PUBLICATIONS 55
 LIST OF FIGURES
Figure Name Page No.

Fig. 2.1 Simple current mirror circuit diagram

Fig. 2.2 Small signal model of simple current mirror 8

Fig. 2.3 Cascode current mirror circuit diagram 9

Fig. 2.4 Small signal model of cascode current mirror 10

Fig. 2.5 Wilson current mirror circuit diagram 12

Fig. 2.6 Small signal model of wilson current mirror 13

Fig. 2.7 Improved Wilson current mirror circuit diagram. 14

Fig. 2.8 Small signal model of improved wilson current mirror 15

Fig. 2.9 Regulated cascode current mirror circuit diagram 18

Fig. 2.10 Small signal model of regulated cascode current mirror 19

Fig. 3.1 Novel Regulated Cascode Current Mirror Circuit 22

Fig. 3.2 Small Signal Model of Novel Regulated Cascode Current 23

Mirror

Fig. 3.3 High Output Impedance Regulated Cascode Current Mirror 26

Circuit

Fig. 3.4 Small Signal Model of High Output Impedance Regulated 27

Cascode Current Mirror

Fig. 4.1 lout with respect to lin of simple current mirror 31

Fig. 4.2 Idc with respect to Vdc of simple current mirror 32

Fig. 4.3 Output impedance with respect to Vdc of simple current 32

mirror

Fig. 4.4 Systematic gain error graph of simple current mirror 33

Fig. 4.5 Power dissipation with respect to Vdc of simple current

mirror 33

Fig. 4.6 lout with respect to lin of cascode current mirror 34

Fig. 4.7 Idc with respect to Vdc of cascode current mirror 34

Fig. 4.8 Output impedance with respect to Vdc of cascode current 35

mirror

Fig. 4.9 Systematic gain error graph of cascode current mirror 35

Fig. 4.10 Power dissipation with respect to Vdc of cascode current

mirror 36

Fig. 4.11 lout with respect to lin of Wilson current mirror 36

Fig. 4.12 Idc with respect to Vdc of Wilson current mirror 37

Fig. 4.13 Output impedance with respect to Vdc of Wilson current

mirror 37

Fig. 4.14 Systematic gain error graph of Wilson current mirror 38

Fig. 4.15 Power dissipation with respect to Vdc of Wilson current

mirror 38

Fig. 4.16 lout with respect to lin of improved Wilson current mirror 39

Fig. 4.17 Idc with respect to Vdc of improved Wilson current mirror 39

Fig. 4.18 Output impedance with respect to Vdc of improved Wilson

current mirror 40
Fig. 4.19 Systematic gain error graph of improved Wilson current
mirror 40

Fig. 4.20 Power dissipation with respect to Vdc of improved Wilson 41

current mirror

Fig. 4.21 lout with respect to lin of regulated cascode current mirror 41
Fig. 4.22 Idc with respect to Vdc of regulated cascode current mirror 42

Fig. 4.23 Output impedance with respect to Vdc of regulated cascode

current mirror 42

Fig. 4.24 Systematic gain error graph of regulated cascode current

mirror 43

Fig. 4.25 Powa- dissipation with respect to Vdc of regulated cascode

current mirror 43

Fig. 4.26 lout with respect to lin of novel regulated cascode current
mirror 44

Fig. 4.27 Idc with respect to Vdc of novel regulated cascode current
mirror 44

Fig. 4.28 Output impedance with respect to Vdc of novel regulated

cascode current mirror 45

Fig. 4.29 Systematic gain error graph of novel regulated cascode

current mirror 45

Fig. 4.30 Power dissipation with respect to Vdc of novel regulated

cascode current mirror 46

Fig. 4.31 lout with respect to lin of high output impedance regulated
cascode current mirror 46

Fig. 4.32 Idc with respect to Vdc of high output impedance regulated 47
cascode current mirror

Fig. 4.33 Output impedance with respect to Vdc of high output 47

impedance regulated cascode current mirror

Fig. 4.34 Systematic gain error graph of high output impedance 48

regulated cascode current mirror
 Fig. 4.35 Power dissipation with respect to Vde of high output
impedance regulated cascode current mirror 48

LIST OF TABLES

Table No Table Name Page No

Table 4.1 Performance parameter of current mirrors 49

LIST OF SYMBOLS

Symbol Significance
lin Reference current

lout Output current

Mobility of Electrons

Gate oxide capacitance

L Channel length of MOSFET

w Channel width of MOSFET

\ Channel length modulation factor

Gate to source voltage of MOSFET

Vds Drain to source voltage of MOSFET

Vth Threshold voltage of a MOSFET

it Output current of CM

Vt Output voltage of a CM

gm Transconductance of a MOSFET

Output resistance of MOSFET

Rout Output resistance of CM

Vmin Input compliance voltage

Vout Output compliance voltage

Vg Gate voltage of a MOSFET

Source voltage of a MOSFET

LIST OF ABBREVIATIONS

Abbreviation Meaning

CMOS Complementary Metal Oxide Semiconductor

CM Current Mirror

NMOS Negative Charmel Metal Oxide Semiconductor

UMC United Microelectronics Corporation

VLSI Very Large Scale Integration

 CHAPTER 1
INTRODUCTION

1.1 Motivation
Current mirrors are core structure of almost all the analog and mixed signal circuit design.
The circuit implemented using current mirror occupies less area, consume less power
dissipation, and achieve high operational speed. The work of current mirror is to copy the
reference current to the output terminal. According to requirement, it is also possible to
amplify or attenuate the reference current. Therefore, current mirror can also be defined
as current controlled current source. Ideally, the output current of current mirror circuit
does not depend on output voltage but only depend on input current. Ideally, the input
impedance of current mirror should be zero therefore input current vary with input
voltage and the output impedance should be infinite therefore output current is
independent of output voltage.

Current mirrors are used for biasing, active load and current amplification etc.
High output impedance current mirror can be used as an active load which provide a
better insensitivity to the variation in power supply and temperature [1]. Current mirrors
are used in many applications such as operational ampUfier, analog to digital converter
and digital to analog convertor etc. Therefore, efficient design of current mirror can
improve the overall performance of the system. The most essential parameters of current
mirror are accuracy, input and output compliances voltage, input and output impedance,
bandwidth, linearity, noise and sensitivity to change in load impedance [2].

1.2 Research Objective

The objective of this dissertation is to design and study the existing current mirror circuits
and thereby, propose the new current mirror circuits that provides high output impedance
and low power dissipation. The high output impedance current min'or circuit is
independent of the variation in power supply and temperature therefore can be efficiently
used as an active load. The proposed circuits can be used for low power application such
as portable device, Bio-medical instruments and sensors etc.
ii«jB9t3i>WtMMW«BcgaK>iai»««Bg^;;a^Stfa.'.tJB»;i'^ -'v. apgT:..^ y , ^ - t f ^ T - - - * ^ T - , ^7^f.^^*^*'''fe^BW***f.^^^^y^J^&JaaiJL^

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 1

1.3 Thesis organization

The thesis is organized into five chapters

CHAPTER 1: This chapter introduces the need of current mirror circuit and summarizes
the organization of this thesis.

CHAPTER 2: This chapter explains the Uterature survey of different type of current
mirrors and their characteristics.

CHAPTER 3: This chapter explains the proposed circuit v^dth their small signal analysis.

CHAPTER 4: This chapter discusses comparative study of proposed circuit and existing
current mirror circuit in terms of total power dissipation, output impedance, systematic
gain error and area with their simulation results.

CHAPTER 5: This chapter summarizes major accomplishments and future scope of this
dissertation.

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 2

 CHAPTER 2
LITERATURE REVIEW

This chapter contains the background information needed to provide a framework for the
results presented in this thesis. The current mirror characteristics are presented first. A
summary of previously reported Simple, Cascode, Wilson, Improved Wilson and
Regulated cascode current mirror circuits are presented.

Several current mirror circuit reported in literature. Dadoria et al. [3] reviewed the
basic current mirror to explore the effect of device dimensions on the ratio of lour and Im
for better accuracy. The limitations of basic current mirrors are lower output impedance,
higher systematic gain error and higher power consumption [4]. Martin et al. [5] reviewed
the Cascode current mirror to improve the output impedance using cascode stage at the cost
of reduction in voltage swing at the output. Cascoding enhances the gain without affecting
the stability of the circuit [6]. However, Cascode current mirror is not suitable at low supply
voltage [7].

Wang [8] reviewed the Wilson current mirror to improve the output impedance
using negative current feedback. Due to negative feedback used in Wilson current mirror,
its output current is stabilized. The drawback of Wilson current mirror is that it is not
suitable at low supply voltage and it shows a peak in it's bode plot which leads to an
imdesirably great overshoot in time domain [9]. Ronald G. Spencer [10] reviewed the
improved Wilson current mirrors to find the closed loop gain with multiple feedback loop
and output impedance. The advantage of improved Wilson current mirror is lowest
systematic gain error, however, it shows low output impedance in comparison to cascode
current mirror [11].

Vajpayee et al. [12] reviewed Regulated cascode current mirror which have highest
output impedance and d.c. gain. In Regulated cascode current mirror, negative feedback is
used to enhance the output impedance. Here, the meaning of regulation is to maintain a
stable output current with respect to variation of output voltage with the help of feedback
loop [13]. The advantages of regulated cascode current mirror are high output impedance,
stabilized output current and Vomin is least as compared to other current mirrors [14].

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 3

 The high output impedance of current mirror helps to keep the output current
constant. So that the high output impedance current mirror circuits are used as an active
load in analog circuits to provide insensitivity to the circuit with respect to power supply
and temperature. Therefore, it is of interest to improve the output impedance existing
regulated cascode current mirror. The proposed structures are used to improve the output
impedance of existing regulated cascode current mirror. The proposed circuit can be used
for low power applications such as portable device, sensors and Bio-medical instruments
etc.

2.1 Characteristics of current mirror

In this section, performance parameter of current mirror circuit are discussed [21].

2.1.1 Input - Output resistance

Ideally, the input resistance of current mirror should be zero means input current is not
vary with input voltage and output resistance should be infinite means output current is
not vary with output voltage. In practical circuit this is not possible that's why input
resistance should be very low and output resistance should be very high.

2.1.2 Input linear range

For exact replica of current at output, the reference current must be in range where both
the transistors Ml and M2 (e.g. simple current mirror) operate in saturation.

2.1.3 Compliance voltage

In ideal current mirror, the output current is independent with respect to output voltage
variation. Practically, current mirror requires a minimum voltage at output to ensure that
the circuit operate in saturation region. This minimum voltage is known as output
compliance voltage.

2.1.4 DC balance

The drain to source voltage of the mirror transistors influence the accuracy of the output
current. The error due to mismatch in Vgs is equal to the channel length modulation effect

g»a«Nati'5wgMa)MBig»wt:^gg«,j'«»saFWfl»^

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 4

(X,). This indicate that if Vgs voltage of mirroring transistors are not similar then there will
be an offset current.

2.1.5 Finite bandwidth

The current amplification in current mirror circuit is typically less than a factor of 100 and
due to constant gain bandwidth product, high fi-equency operation of the circuit is
possible. Current mirror circuits provide wide bandwidth operation at low gains.
However, the voltage mode circuits with similar closed loop gains produce comparable
bandwidtL

2.1.6 Device matching

In current mirror circuit, for similar input and output current the mirroring current should
be matched. The matching parameters are W/L ratio, trans-conductance and threshold
voltage etc. Due to mismatching in device parameters there will be two type of errors,
random error and systematic gain error.

2.2 Different Types of Current Mirror

In this section previously reported current mirror circuits are presented. Their AC analysis
is performed to calculate the output impedance. Finally their advantages and drawbacks
are discussed.

2.2.1) Simple current mirror

2.2.2) Cascode current mirror
2.2.3) Wilson current mirror
2.2.4) Improved wilson current mirror
2.2.5) Regulated cascode current mirror

2.2.1 Simple current mirror

Fig. 2.1 shows the simple current mirror circuit with three n-type MOS transistors.
Transistors MO and Ml are diode connected. Diode connected transistor always remain in
saturation region which is one of the important condition of any current mirror [15]. Input
current of circuit is lin and output current is lout then
pwiwi.&:--^afc^^i^tafi^ieg&aEg'a

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 5

 M^^
lin = [In Cox ( 7 ^ ) (Vgsl - Vthl)2 ( 1 + A Vdsl) (2.1)

lout = Hn Cox ( 7 ^ ) (Vgs2 - Vth2)2 ( 1 + A Vds2) (2.2)

L2

levQ 18VQ
3-
MO

a Ml M2i

Fig. 2.1 Simple current mirror circuit diagram

From equation (2.1) and (2.2) -

,(,ut tin Cox (,w-,

^ ) (Vgs2 - Vth2)2 (1 + A Vds2)
(2.3)
lin nn Cox (,w^ ) (Vgsl - Vthl)2 (1 + A. Vdsl)
''I

Where,
[in = mobility of electrons
>^ox~ gate capacitance
W & L = gate width and length
A = channel length modulation factor

If drain to source voltage of transistors Ml and M2 are equal then channel length
modulation will be zero. Now equation (2.3) can be written as

[out _ nnCox(^)(Vgs2-Vth2)2
(2.4)
lin tin Cox ( ^ ) (Vgsl - Vthl)2
'-1

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Pages

In the Fig. 2.1, we can see that gate to source voltage of transistors Ml and M2 are equal
so equation (2.4) can be written as
Wn
lout nn Cox (y^)
(2.5)
lin nnCox(^)

,w. ratio of transistors Ml and M2 are equal then lout will be equal to lin-
If (—)

lout = lin (2.6)

For simple current mirror minimum input compliance voltage is

2/,:
= Vth + (2.7)
Bi

Output compliance voltage is -

(2.8)

2.2.1.1 Output Impedance Analysis

The small signal equivalent circuit used to calculate the output impedance of simple
current mirror is shown in Fig. 2.2. In the following analysis, gm is trans-conductance, ro
is output resistance of transistor, Vt is output voltage, it is output current, Vgs is gate to
source voltage of transistor and Rom is overall output impedance. The transistors numbers
are demonstrated as subscripts of these parameters. The mathematical calculation is given
as follows:

1/gml gm2. v«^0

Fig. 2.2 Small signal model of simple current mirror

lKSi!*^K«-"S« ' ^ S ^ ' '^t i f f ^ S a y ^ i ^ ^ - J ^

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page?

From Fig. 2.2, the current at output node is given in equation (2.9)

h— 9m2-^gs2 + ~~ (2.9)
'02

Where,

it = output current

Vt = output voltage

gm2 = transconductance of transistor M2

Vgs2 = gate to source voUage of transistor M2

To2 = output resistance of transistor M2

We know that

Vgs2 = Vg2 - Vs2

Vgs2 = 0-0

Vgs2 = 0 (2.10)

From equation (2.9) and (2.10)

Vt
h=

— = ro2

Rout — ro2 (2.11)

Therefore, Eq. (2.11) shows the output impedance of simple current mirror circuit.

Advantage
a) Only for general purpose application.

Drawbacks
a) Low output impedance.
b) High systematic gain error.
c) High power dissipation.

•jf>^:;?msLM^,sji&^'£. .jT^TCgg

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Pages

2.2.2 Cascode current mirror

Fig. 2.3 shows the cascode current mirror circuit with five n-type MOS transistors.
Transistors MO, Ml and M3 are diode connected transistors which always remain in
saturation. In the saturation region output current of transistor is independent of output
voltage. In Simple current mirror one cascode stage is added that's why this circuit is
known as cascode current mirror [16]. Cascode means one transistor on the top of another
where a common emitter transistor drives a common base transistor. The effect of
cascode stage is enhance the output impedance by the factor gm ro and enhances the gain
without affecting the stability of the circuit.

3- MO i.evQ
'O
M4

3- M3
-E

M2

3 M
Ml

Fig. 2.3 Cascode current mirror circuit diagram

For Cascode current mirror minimum input compliance voltage is

Vmin = 2Vth + 2 J - ^ (2.12)

Output compliance voltage is

Vout = Vth + 2 1 ^ (2.13)

2.2.2.1 Output Impedance Analysis

The small signal equivalent circuit used to calculate the output impedance of cascode
current mirror is shown in Fig. 2.4. In the following analysis, gm is trans-conductance, ro
is output resistance of transistor, Vt is output voltage, it is output current, Vgs is gate to

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Pages

source voltage of transistor and Rout is overall output impedance. The transistors numbers
are demonstrated as subscripts of these parameters. The mathematical calculation is given
as follows:

From Fig. 2.4, gate to source voltage of transistors M2 is calculated as

Vgs2 = Vg2 - Vs2

Vgs2 = 0-0

Vgs2 = 0 (2.14)

l/gm3
gm4.VB»4<^

1/gml
gm2.Vcs2<0>

Fig. 2.4 Small signal model of cascode current mirror

Current at the output node of circuit is calculated as

(2; 15)
'04

Gate to source voltage of transistor M4 is

Vgs4 = - it ro2 (2.16)

From equation (2.15) and (2.16)

^t-ikraz)
it — gm4.(-it ro2) +

rnxme^^^^"^^- >-^i--4s.:t^%^i^TS^\,

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 10

 it [1 + gm4.ro2 + 7^] = I ^
'04 '^04

Rout = ro4 [1 + gm4.ro2 + — ]

^"04

Rout = ro4 + gm4.ro2.ro4 + ro2

If To = ro2 = ro4

Rout = gm4ro2 (2.17)

Therefore, Eq. (2.17) shows the output impedance of cascode current mirror circuit.

Advantage
a) High output impedance compared to Simple, Wilson and improved
Wilson current mirror.
b) Power dissipation is less compared to Simple current mirror.
Drawbacks
a) It is not suitable at low supply voltage.
b) High input and output compliance voltage.

2.2.3 Wilson current mirror

Fig. 2.5 shows the Wilson current mirror circuit with four n-type MOS transistors.
Transistors Ml and M3 are diode connected transistors. Diode connected transistors
always remain in saturation region which is one of the important condition of current
mirror because in saturation region it work as a constant current source. In saturation
region output current is independent of output voltage because of its high output
impedance. In Wilson current mirror negative feedback is used to stabilize the output
current with respect to variation of output voltage [17]. The concept of negative feedback
can be understand as, if load is change in the circuit then output current will increase and
due to increase in output current drain to source voltage of transistor M3 increase due to
which gate to source voltage of transistor M2 increase as a result drain current should
increase but reference current is constant that's why it can't change and drain to source
voltage of transistor M2 decrease due to this gate voltage of transistor M4 decreases and
output current decreases. So any variation in output current is stabilize by negative
feedback.

,:^-;8S^Bafcaey3?,^WWTO^^m^J•.^>^iJ'•,;at::^^

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 11

 svQ 18V(
Ml
M4
Er

M2 M3
B

Fig. 2.5 Wilson current mirror circuit diagram

For Wilson current mirror minimum input compliance voltage is

Vmin = 2Vth + 2 J ^ (2.18)

Output compliance voltage is

Vout = Vth + 2 (2.19)

Bi

2.23.1 Output Impedance Analysis

The small signal equivalent circuit used to calculate the output impedance of Wilson
current mirror is shown in Fig. 2.6. In the following analysis, gm is trans-conductance, ro
is output resistance of transistor, Vt is output voltage, it is output current, Vgs is gate to
source voltage of transistor and Rout is overall output impedance. The transistors numbers
are demonstrated as subscripts of these parameters. The mathematical calculation is given
as follows:

From Fig. 2.6, gate to source voltage of transistor M2 can be calculated as

^qs2— k-Z (2.20)

9m3

) + VgsZ = 0

(2.21)

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 12

 g m 4 Vc*4
-fc> rc>4

vt©
f o i ' I ro2 m2. Vcs2 a/gm3

Fig. 2.6 Small signal model of wilson current mirror

Substitute the value of Vgs2 from equation (2.20) into (2.21)

Vgs4 = - T ^ [ l + 9m2 (^01 II ro2 ) ] (2.22)

9m3

Vt-v
gs2
9m4 ^s4+ (2.23)

Substitute the value of ^^^4 from equation (2.22) into (2.23)

k= • 5 m 4 f ^ [ l + 9m2 (roi II ro2 )] + T-+ 7 - 7 -

9m3 '04 '04 8m3

r= ^t[l + T V + ? ^ [ l + 3m2 (roi II ro2)] (2.24)

'04 5m3'04 tfms

If gm3 = gm4 & To = Fol = ro2 = ro4

Put these value in equation (2.24)

Rout = ro H 1- Fo [ 1 + g m 2 - f ]
3m3 2

Rout = gm2 -J- (2.25)

Therefore, Eq. (2.25) shows the output impedance of wilson current mirror circuit.

Advantage
a) High output impedance compared to Simple current mirror.
b) Better high frequency behavior compared to Cascode current mirror.
c) Power dissipation less compared to Simple current mirror.

mrrtntt mtiaum^rm^^mm mmsam^i,sfm^im^'S^^' Vf'^i3ssfiXfsrs&^:^?;^'Simsirr-'m-~-'.r!rr'Js:j^?:^sisz

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 13

Drawback
a) Asymmetrical biasing due to which large DC matching error.
b) Its bode plot has peak which leads to a large undesirable overshoot in
the time domain.
c) High input and output compliance voltage.

2.2.4 Improved Wilson current mirror

Fig. 2.7 shows the improved wilson current mirror circuit with five n-type MOS
transistors. Transistors MO, Ml and M3 are diode connected transistors which always
remain in saturation region because drain to gate voltage is zero and Yds > Vgs - Vt.

evQ a MO
l.&V

a Ml M4

a. IVI2

M3
^

Fig. 2.7: Improved Wilson current mirror circuit diagram.

The drawback of Wilson current mirror, asymmetrical biasing due to which large DC
matching error is removed by adding one more transistor M2 in series with transistor M3
so there is lower systematic gain error. It is known as improved Wilson current mirror
because it improves the systematic gain error as compared to Wilson current mirror.
For Improved Wilson current mirror minimum input compliance voltage is

Vmin = 2Vth + 2 (2.26)

Output compliance voltage is

2Iin
Vout = Vth + 2 (2.27)

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 14

2.2.4.1 Output Impedance Analysis

The small signal equivalent circuit used to calculate the output impedance of Improved
Wilson current mirror is shown in Fig. 2.8. In the following analysis, gm is trans-
conductance, To is output resistance of transistor, Vtis output voltage, it is output current,
Vgs is gate to source voltage of transistor and Rout is overall output impedance. The
transistors numbers are demonstrated as subscripts of these parameters. The mathematical
calculation is given as follows:

gmtVfs*
4> ro4
lit

Vt@

ro2 l/gmJ

tl 12

Fig. 2.8 Small signal model of improved wilson current mirror

From Fig. 2.8, the current at output node is calculated as

it = gm4 Vgs4 + (2.28)

il = gm2Vgs2( , ""^ , ) (2.29)

^nn+ fn7'^ '
Bml

i2 = g m 2 V g s 2 ( - — - ^ f V ) (2.30)
flmi

Vg4 = -ii. roo (2.31)

Vgs2 = Vs4 = it. (2.32)

5m3

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 15

From equation (2.29), (2.31) and (2.32)

Vg4 = - i t ^ ( '-^^-r-) (2.33)

3m3 roo+ro2+^—

From equation (2.32) and (2.33)

Vas4 = it — ( ^^'^-T-) - it —
* 3m3 Voo+roz+TT- ^"13
Sml
1
it.-
It = - It gm4 — - ( ; —r-) - It. — - + — 9m.2
dm3 foo"^'''02+Z 3m3 ^04 ^04
5ml

- = ro4 [1 + ——— +-— +gm2— (.—r~-^\

k ~04.9m3 9m3 9m3 ^00+^02 + -
5ml

Rout = ro4 + — + ro4 ^2^ + ro4 Qmi ^ ^ ( ^^^^-r-) (2-34)

9m3 9m3 9m3 T'oo+'''o2 + -
5ml

If ro = ro4 = roo = Voi, gm = gmi = gm2= gm3 = gm4 and neglecting the lower terms then
from equation (2.34)

Rout=gm^ (2.35)

Therefore, Eq. (2.35) shows the output impedance of improved Wilson current mirror
circuit.

Advantage
a) Lower systematic gain error.
b) High output impedance compared to Simple current mirror.
c) Betto- high frequency behavior compared to Cascode current mirror.
d) Power dissipation less compared to Simple current mirror.

Drawback
a) Its bode plot has peak which leads to a large undesirable overshoot in the
time domain.
b) High input and output compliance voltage.

NATIONAL INSTrafTE OF TECHNOLOGY KURUKSHETRA Page 16

2.2.5 Regulated cascode current mirror

Fig. 2.9 shows the regulated cascode current mirror circuit with four n-type MOS
transistors. Transistor Ml is diode connected transistor which always remain in saturation
region because drain to gate voltage is zero and Vds > Vgs - Vt. In regulated cascode
current mirror negative feedback is used to enhance the output impedance and two bias
voltage 1.8 V and 0.7 V are used in such a way that constant current flow to stabilize the
output current [18].In regulated cascode current mirror, regulated means, the output
current is controlled by the gate voltage of transistor M3 as well as the drain to source
voltage of transistor M3. The drain to source voltage of transistor M3 is regulated by the
transistors pair M2 and M4. The feedback is provides to keep the drain to source voltage
of transistor M3 constant, which minimize the charmel-length modulation effect [19]. The
feedback loop works as follows:
From the given Fig. 2.9, we can calculate

Vds3 = Vgs2 (2.36)

Vds2 = Vgs4 + Vds3 (2.37)

When Vds3 decreases then from equation (2.36) Vgs2 has to decreases.
Because input current is constant

I = tin Cox ( T ^ ) (Vgs2 - Vth2)2 ( 1 + A Vds2) (2.38)

and Vgs2 is decreasing then Vds2 should be increased,

since
Vds2 - V^4 + Vds3
because Vds2 increasing that's why Vgs4has to increase and output current should increase
but it can't change so

I = ^n Cox ( ^ ) (Vgs3 - Vth3)2 (1 + X Vds3) (2.39)

Vgs3 is constant that's why Vds3 will increase. Finally we can say that Vds3 is stabilize.

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 17

 8VQ a. I.BV0

Ml
M4
Br

• ^

M2
JM3
H-
O.TvA

Fig. 2.9 Regulated cascode current mirror circuit diagram

2.2.5.1 Output Impedance Analysis

The small signal equivalent circuit used to calculate the output impedance of regulated
cascode current mirror is shown in Fig. 2.10. In the following analysis, gm is trans-
conductance, ro is output resistance of transistor, Vtis output voltage, it is output current,
Vgs is gate to source voltage of transistor and Rout is overall output impedance. The
transistors numbers are demonstrated as subscripts of these parameters. The mathematical
calculation is given as follows:
From Fig. 2.10, the current at output node is calculated as

it= gm4Vgs4 + (2.40)

^04

Applying the KVL in the small signal model

Vgs4 + gm2 ( F O I II ro2) Vgs2 + It ro3 = 0 (2.41)

Gate to source voltage of transistor M3 is
Vgs3 = it ro3 (2.42)

From equation (2.41) and (2.42)

Vgs4 + gm2 ( r o l li ro2) ToS It + it ro3 = 0 (2.43)

maummajsm
NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 18
 g;r»*4 V e * ' *
'. Ttr*
I it
v t ^

t o t ' • ro2 Imi. Vcs2

r<c^

Fig. 2.10 Small signal model of regulated cascode current mirror

From equation (2.40) and (2.43)

Vt- hToz
it = [-gm2 (roi II ro2) ro3 it - it ros] gm4 +

— = it [ 1 + (gm2 ( f o l II ro2) ro3 + r o s ) gm4 + — ]

04 To 4

Rout = ro4 + gm2. gm4 ( f o l II ro2) ro3. ro4 + gm4 FoS ro4 + ro3

R o u t = gin2. gm4 ( f o l II ro2) ro3. ro4 (2.44)

If gm = gm2 = gm4 a n d To = Tol = r o 2 = ro3 = ro4

Put these value in equation (2.44)

I^out - gm ~ (2.45)

Therefore, Eq. (2.45) shows the output impedance of regulated cascode current mirror
circuit.

Advantage
a) Highest output impedance.
b) Lower input and output compliance voltage.
c) Low power dissipation.
Drawback
a) High systematic gain error.

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 19

 CHAPTER 3

DESIGN AND ANALYSIS OF PROPOSED CURRENT

MIRROR STRUCTURES

In this section, we have discussed two novel current mirror structures named as "a novel
regulated cascode current mirror" and "high output impedance current mirror" provides
new solutions to in:q)rove the output impedance. AC analysis have been presented to
demonstrate the feasibility of the proposed circuits. Unfortunately, a novel regulated
cascode current mirror and high output impedance current mirror technique come with
systematic gain error overheads so it provides new insights to designers who require
higher output impedance and are wilUng to pay some cost in terms of systematic gain
error.

3.1 A Novel Regulated Cascode Current Mirror

The schematic of the NMOS type of proposed current mirror is shown in Fig. 3.1. The
idea behind the proposed circuit is to combine the two current mirror and improve the
output impedance. In proposed circuit, cascode and regulated cascode current mirror are
combined. Here, the double cascode stage is used to enhance the output impedance and
feedback loop is used to stabilize the output current with respect to variation in output
voltage [20]. Circuit consisting of MO, Ml, M2 and Ml 1 at output side and M4, M5, M6
and Ml2 at input side of current mirror. In Fig. 3.1, transistors M2 and Mil are
connected in cascode form which increase output impedance and transistors M4 and MO
are connected in such a way so that they can compensate any deviation in output current.
In proposed structure, two diode connected transistors M5 and M6 are used to keep the
transistors in saturation region because in saturation region output current is independent
of output voltage. Here, transistor M4 work as an amplifier and the working of an
amplifier is to sense and compensate the deviation in drain to source voltage and maintain
a constant gate voltage at the gate of output transistor.

!>c^«i-.'?^jv:?-^'^.-ij.A- ?y7..J!-.igj|L-jsgg?'-!Kgger;

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 2 0

 i.svA
V d c •= 2 . S V
i -•-I T12

H
T6 Til l--<-
H

T5 T2
h-*-

TO

T4
-*~\

Tl

V d c l = 0.7V cT
I
Fig. 3.1 Novel Regulated Cascode Current Mirror Circuit

3.1.1 Output Impedance Analysis

The small signal equivalent circuit used to calculate the output impedance of cascode
current mirror is shown in Fig. 3.2. In the following analysis, gm is trans-conductance, ro
is output resistance of transistor, Vt is output voltage, it is output current, Vgs is gate to
source voltage of transistor and Rom is overall output impedance. The transistors numbers
are demonstrated as subscripts of these parameters. The mathematical calculation is given
as follows:

il = gm4 Vgs4 ( - ) (3.1)

'•''*"*"'•''"•'^;;;;"^5m6

''012+—+ —
12 - gm4 Vgs4 (, j — ; —) (3.2)
''04+ ^ 0 1 2 '
5ms 5m6

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 21

 vt®
g m l l . VgslK roll

g m 2 . Vgs2( ro2

X
gmO. VgsOCb* ^ roO

VgsO

rol2

ro4 Brn4. V e s 4 ^ r o l II 1 / g m l
l/gmS

l/gm6

Fig. 3.2 Small Signal Model of Novel Regulated Cascode Current Mirror

Gate to source voltage of transistor MO can be calculated as

VgsO = -{(TOXZ + 7 - + T—) II ^04} &"4 Vgs4 - Vgs4

5m5 8m6

VgsO = - Vgs4 [{(roi2 + :r~ + r ~ ) " ^04} gm4 + 1 ] (3.3)

From Fig. 3.2, current at output node is

i t = gmll Vgsll + (3.4)

Gate to source voltage of transistor Ml 1 is

Vgsll = Vgu - Vsii and (3.5)

Vgii = - ii roi2 (3.6)

NATIONAL INSTTTUTE OF TECHNOLOGY KURUKSHETRA Page 22

From equation (3.1) and (3.6)

Vgll = - rol2 gm4 Vgs4 ( 7 °*i i ) (3.7)

°* °^^ 9ms 9m6

Gate to source voltage of transistor M4 is

Vgs4 = itroi (3.8)

From equation (3.7) and (3.8)

Vgll = - it roi roi2 gm4 ( ^ —) (3-9)

Sms 9m6

From equation (3.4)

it = g m l l Vgll - g m l l V s l l -
^011

it = g m l l Vgll - g m l l V s l l -
^011 ^011

Vr 1
it = g m l l Vgll + Vsll(gmllH ) (3.10)
'"oil ^011

Source voltage of transistor Ml 1 is

1
V s l l = ro2 it - gm2 ro2 Vg2 + Vs2 ro2 (gm2 -\ ) (3.11)

Output current is

It = gmO VgsO H
''oo

roo it = roo gmo Vgso + Vs2 - it foi

Vs2 = it (foo + roi) - roo gmoVgso (3.12)

From equation (11) and (12)

Vsll = ro2 it + it fol ro2 gm2 gm4 ( °-\ J—) (l"ol2 "I ) + (it (roO + r o i ) - roO
'•o4+'"oi2 + 7r~r+ 7— 9m(,

amS amo

gmO Vgso) ro2 (gm2 H ) (3.13)

witm^fmKim^ ii|liiiiini*»imia^ajWMW ipiM^^JwjhaiMBEsa&^<~-^^^^aiifX^'altg-3K^<.^!<;sgfcg-.-.gg-^

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 23

From equation (3.3) and (3.13)

r 1
Vsu = ro2 it + it Foi ro2 gm2 gm4 ( ^ j—) (jou H ) + (it (roo + roi) + it roi

ro2 gmO { 1 + { ( r o i 2 + - ^ + 7 - ) II ^04} gm4}) ro2 (gm2 + ^) (3.14)

«ms yme '02

From equation (3.9), (3.10) and (3.14)

it = - it Tol Ton gmll gm4 ( ^^i T") + ~ ^ " it(gmllH )[ro2 + Tol ro2 gm2 gm4

C ,, ? ' i , —) (roi2 + - ^ ) ] + [(roo + roi) + roo roi gmo{1 + {(ra^2 + T " + T " )
SmS Sm6

II ''04} gni4}] ro2 (gm2 + -^)

— = roll [ 1 + roi rol2 gmll gm4 ( ^^1 —) + ( g m l l H ) [ ro2 + Tol ro2 gm2

&"4(— 7V-—1-) (roi2 + - ^ )] + [(roo + roi) + roo roi gmo (1 + {(r^iz + - ^ +

^04+'''012'^ •" - — yme SmS
3ms Bme

•7-) II ^04} gm4}] ro2 (gm2 + r " ) ]

9 7716 '02

T 1
Rout = roll [ 1 + roi rol2 gmll gm4 ( ^ T")] + ( g m l l H ) [ro2 + Tol ro2 gm2
^"04+ ^012+ -—+ ;;— ^011

gm4 (roi2 + — ) ( ^^ i-)] + [(roo + roi) + roo roi gmo (1 + {(TOU + — +

9m6 ''04+ '"012+":;—•• ":;— dms
9m5 3mf>

-T-) II TOA] gm4}] ro2 (gm2 + ^ ) (3.15)

tlmb 'o2

Therefore, Eq. (3.15) shows the overall output impedance of novel regulated cascode
current mirror circuit.

Advantage
a) High output impedance compared to other current mirror.
b) Power dissipation is lower.

Drawbacks
a) High systematic gain error.

BgBgaMgt^cgagaiaiJisaK^asgg

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 24

3.2 High Output Impedance Regulated Cascode Current Mirror

The schematic of the NMOS type of proposed current mirror is shown in Fig. 3.3. The
idea behind the proposed circuit is to combine the two current mirror and improve the
output impedance. In proposed circuit, simple and regulated cascode current mirror are
combined.

2V
i ai MO
2V0

t>4S
9- JVll
^

N14
e
a ISiCt

1S43

OTVCP

Fig. 3.3 High Output Impedance Regulated Cascode Current Mirror Circuit

Here, the single cascode stage is used to enhance the output impedance and feedback loop
is used to stabilize the output current with respect to variation in output voltage [20]. In
Fig. 3.3, transistor M5 is connected in cascode with existing regulated cascode current
mirror to increase output impedance and transistors M2 and M4 are connected in such a
way so that they can compensate any deviation in output current. In proposed structure,
one diode connected transistor Ml used to keep the transistor in saturation region because
in saturation region output current is independent of output voltage. In proposed circuit,
transistor M2 is work as an amplifier and the working of amplifier is to sense and

s^&*g^ga»jig{8KaiaE«.aabfej&A:jt«3L^'-':" i-'j^jata

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 25

compensate the deviation in drain to source voltage and maintain a constant gate voltage
at the gate of output transistor.

3.2.1 Output Impedance Analysis

The small signal equivalent circuit used to calculate the output impedance of cascode
current mirror is shown in Fig. 3.4. In the following analysis, gm is trans-conductance, ro
is output resistance of transistor, Vt is output voltage, it is output current, Vgs is gate to
source voltage of transistor and Rout is overall output impedance. The transistors numbers
are demonstrated as subscripts of these parameters. The mathematical calculation is given
as follows:

Vt
^

gmS. Vgs5 @ foS

ro4

Too

l/gml

Fig. 3.4: Small Signal Model of High Output Impedance Regulated Cascode Current
Mirror

»;)awgaa-TS^ag^a»g'55i!;^S9at-'i;a*^JBJi

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 26

From Fig. 2, current at output node is

it=gm5Vgs5 + ^^^^^ (3.16)

ro2
ii = gm2ro3it( —i-) (3.17)
^00+'"02+"
9mi

12 = gm2 ro3 it ( ^^^V-) (3.18)

Gate to source voltage of transistor M2 is

Vgs2 = ro3it and (3.19)

Gate to source voltage of transistor M5 is

Vgs5 = Vg5-Vs5 (3.20)

Gate voltage of transistor M5 is

Vg5 = -iiroo (3.21)

From equation (3.17) and (3.20)

'02
VgS = - gm2 ro3 it ( —) Too (3.22)
roo+roz+-
57711

Gate to source voltage of transistor M4 is

Vgs4 = Vg4 - Vs4

Vgs4 = - ro2 i2 - FOB it (3.23)

From equation (3.18) and (3.23)

'"00+—
Vgs4 = - gmz ro2 ro3 it ( 1 ) - ro3 it
^00+ ^02+ •
57711

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 27

 ''00+- ^
Vgs4 = - it [gm2 ro2 ro3 ( ^2ii_,) + ro3] (3.24)
roo+ro2 + g^^

Source voltage of transistor M5 is

Vs5 = it [ro3 + ro4 + gm2 gm4 ro2 foS ro4 ( ^ ^ V " ) + ToS ro4 gm4] (3.25)
'OO'T'OZ'' „

From equation (3.16)

it = gmS Vgs5 +
ros

it = gmS (VgS - Vss) +

ros

it = gmS VgS - Vs5(gm5 + — ) + — (3.26)

From equations (3.22), (3.25) and (3.26)

it = - gm2 gmS roO ToS it ( 1") " it [ro3 + ro4 + gm2 gm4 ro2 foS ro4 ( ^^^) +

ro3 ro4 gm4] H

roo+-^—
- ^ = it [ 1 + gm2 gmS roO To3 ( ^ T") + ro3 + ro4 + gm2 gm4 ro2 ro3 ro4 ( ^^^^)

+ ro3 ro4 gm4]

- r = [ro5 + (ro3 + ro4) roS + gm4 ro3 ro4 roS + gm2 gmS roO ro3 roS ( j—) + gm2 gm4
It Tnn+ f„7+ flml

^00+-—
ro2 ro3 ro4 roS ( ^^^V")]
''O0+''o2+'l
•9ml

^02 „ „
Rout = [ ( 1 + ro3 + ro4) ro5 + gm4 ro3 ro4 ro5 + gm2 gmS roO ro3 ro5 ( i—) + gm2 gim4
^00+ ^02+7;
5ml
1
^00+-
ro2 ro3 ro4 ro5 ( ^2ii_)] (3.27)
^00+^02 +
5mi

gaR3asg;sg-^^'.»wa»g^iai^irfgij«a...^-j;wwjM-t^-j„«»^[M.jLi^-^>jULijLLMj:m^iij^im^

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 28

Therefore, Eq. (3.27) shows the overall output impedance of high output impedance
regulated cascode current mirror circuit.

Advantage
a) High output impedance compared to other current mirrors except novel
regulated cascode current mirror.
b) Power dissipation is lower.
Drawbacks
a) High systematic gain error.

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 29

 CHAPTER 4
SIMULATION RESULTS

In this section, we will discuss simulation results of previously reported current mirror
circuits and proposed current mirror circuits. All the simulations are performed using
Cadence virtuoso at 180nm technology [20]. The measurement results include following
parameters such as output impedance, power dissipation and systematic gain error.

4.1 Simple Current Mirror

In simple current mirror circuit, we have calculated all the results at Vdc= 1.8 V. Fig. 4.1
shows the graph between input current and output current. In this circuit output current
follow input current for very small range. Fig. 4.2 shows the graph between output
current and output voltage. Output current is not constant in the saturation region i.e. not
flat curve because this circuit has very low output impedance. So high output impedance
is required condition for good performance current mirror.

400.0p -

300.0|J

O 200.0M

lOO.Op -

800.01J

Fig. 4.1 lout with respect to lin of simple current mirror

NATIONAL INSTrrUTE OF TECHNOLOGY KURUKSHETRA Page 30

 J 1 I 1 I . l__i I I I I I 1 I I I 1 L

50.0|J -

-1 1 > 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1-
-0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

Vdc(V)
Fig. 4.2 Idc with respect to Vdc of simple current mirror

• 1 • 1 • [ • 1 I 1 • 1 • 1 • 1 • 1 • 1 1
160.0k -

140.0k -

120.0k -

100.0k-

EIP 80.0k - /

60.0k -
N

40.0k -

20.0k -

0.0-
• I • • • 1 1 1 • 1 • 1 • 1 1 1 1 I 1 1 1

-0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

VDC(V)

Fig. 4.3 Output impedance with respect to Vdc of simple current mirror

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 31

 8.0M

6.0JJ-

^ 4.0M
<

• 2.0M -
<
3
O 0.0-

-2.0M -

-4.0M- 1 1 1 1 1 1 1
O.O 50.0M 100.0M 150.0M 200.0M

lin(A)

Fig. 4.4 Systematic gain error graph of simple current mirror

J I I I I J I I L -i 1 1_ J I I • l_

180.0M

160.0M -

140.0M -

120.0M -

^ 100.0M

5 80.0M -

a.
60.0M-

40.0M -

20.0M -
o.o - 1 — I — I — I — I — I — • — r - — • — I — I — I — 1 — I — • — I — 1 — I — I -

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VDC(V)

Fig. 4.5 Power dissipation with respect to Vdc of simple current mirror

^•Wg^^'*,gr^m-..•JEa!5JKgSJ..-tiBgaiKK U:.JiaSiiJf»!i-' 1>M*M<.<L< <umi.['KllAfM 1.1

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 32

Fig. 4.3 shows the graph between output impedance and Vdc. The output impedance of
this circuit is 142 KQ. at biasing voltage Vdc = 1.8 V. Fig. 4.4 shows the graph of
systematic gain error for this current mirror circuit. The graph indicates highest
systematic gain error. Fig. 4.5 shows the graph between power dissipation and Vdc. The
power dissipation of this circuit is 168 |iW at biasing voltage Vdc = 1.8 V.

4.2 Cascode Current Mirror

In cascode current mirror circuit, we have calculated all the results at Vdc = 1.8 V. Fig. 4.6
shows the graph between input current and output current. In this circuit output current
follow input current upto 150 |JA. Fig. 4.7 shows the graph between output current and
output voltage. Output current is approximately constant in the saturation region i.e. flat
curve because this circuit has high output impedance. So high output impedance is
required condition for good performance current mirror. Fig. 4.8 shows the graph
between output impedance and Vdc. The output impedance of this circuit is 4.89 MQ. at
biasing voltage Vdc = 1-8 V. Fig. 4.9 shows the graph of systematic gain error for this
current mirror circuit. Fig. 4.10 shows the graph between power dissipation and Vdc. The
power dissipation of this circuit is 34.36 ^W at biasing voltage Vdc = 1.8 V.

300.0M - 1 . 1 . 1 . 1 . 1 . 1

250.0M -

200.0M -

< 150.0M -

J 100.0M -
/

50.0M -

0.0-

1 -•— 1 ' 1 ' 1 ' 1 ' 1

0.0 200.0M 400.0M 600.0M 800.0M 10m

"in(A)
Fig. 4.6 lout with respect to lin of cascode current mirror

BKais«i»tfafc^ft^JCK!fK-iai>a!!^

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 33

 -j I I L. -I I I ' J . I i__l 1 I 1 I > L

10.0M -

8.0M-

6.0M-

u
-? 4.0M H

2.0M-

0.0-

-1 1 1 1 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 r
-0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

Vdc(V)
Fig. 4.7 Idc with respect to Vdc of cascode current mirror

T—'—I—I—I—"—I—'—I—'—I—'—I—•—I—'—1—•—r
-0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

VDC(V)

Fig. 4.8 Output impedance with respect to Vdc of cascode current mirror

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 34

 1 • 1 • 1 • 1 • - 1 1

0.0-

-2.0|J - ^ ^ x

-4.0|J-
<
-6.OIJ- \
1

-8.0M-

-10.0M -
O
-12.0M -

-14.0M -

-16.0M -
'••- 7 ' 1 • - 1 ' 1 ' 1

0.0 50.0M 100.0M 150.0M 200.0M

«in(A)

Fig. 4.9 Systematic gain error graph of cascode current mirror

. 1 . 1 . 1 . 1 . 1 . 1 . 1 . 1 . 1 . 1 .

35.0M -

30.0M -

25.0M -

1
20.0M -

J
15.0M -
OL
10.0M-

5.0M-

O.O-

-5.0M - • 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 •

-0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

VDC(V)

Fig. 4.10 Power dissipation with respect to Vdc of cascode current mirror

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 35

4.3 Wilson Current Mirror
In Wilson current mirror circuit, we have calculated all the results at Vdc = 1.8 V. Fig.
4.11 shows the graph between input current and output current. In this circuit output
current follow input current upto 50 ^A. Fig. 4.12 shows the graph between output
current and output voltage. Output current is not constant in the saturation region i.e. not
flat curve because this circuit has low output impedance. So high output impedance is
required condition for good performance current mirror. Fig. 4.13 shows the graph
between output impedance and Vdc. The output impedance of this circuit is 860.53 KQ at
biasing voltage Vdc == 1.8 V. Fig. 4.14 shows the graph of systematic gain error for this
current mirror circuit. Fig. 4.15 shows the graph between power dissipation and Vdc. The
power dissipation of this circuit is 38.89 |iW at biasing voltage Vdc = 1.8 V.

0.0 200.0p m.O\i 600.0M 800.0|J

lin(A)
Fig. 4.11 lout with respect to lin of Wilson current mirror

tamsitr%iBm<iiiSE^xm3rs^ies^>e&rsms

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 36

 -1—I—1—I—I—I—I—I—1—I—1—I—1—I—I—I—I—I—1—p
-0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

Vdc(V)
Fig. 4.12 Idc with respect to Vdc of Wilson current mirror

800M J I J 1 L

700M-

600M-

500M-

E 400M

300M-
N
200M-

100M

0-

-100M - 1 — I — I — I — • — I — I — I — I — I — , — ^ — 1 — I — , — I — > -

0.0 0.2 0.4 0.6 0.8 1,0 1.2 1.4 1,6 1

VDC(V)
Fig. 4.13 Output impedance with respect to Vdc of Wilson current mirror

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 37

 1 , 1 , 1 . 1 . 1
10.0M -

0.0-

-lO.OiJ -

-20.0H -
g ^ ^ ^
^ -30.0M -

1
-40.0JJ -

3 -50.0M -
O
-60.0M -

-70.0M -

-80.0M -
t ' I ' 1 ' 1 • 1
O.O 50.0M 100.0M 150.0M 200.0M

lin(A)
Fig. 4.14 Systematic gain error graph of Wilson current mirror

J I I 1 I I L ' ' • J I I • I I L -1 1 t.

40.0|j-

30.0M-

f- 20.0M-j

Q.

10.0M

0.0-

-I 1 1 1 1 1 . 1 1 1 1 1 1 1 1 1 . 1 1 1 r
-0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

VDC(V)
Fig. 4.15 Power dissipation with respect to Vdc of Wilson current mirror

N A T I O N A L INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 3 8

4.4 Improved Wilson Current Mirror

In improved Wilson current mirror circuit, we have calculated all the results at Vdc= 1.8
V. Fig. 4.16 shows the graph between input current and output current. In this circuit
output current follow input current upto 60 |iA. Fig. 4.17 shows the graph between output
current and output voltage. Output current is not constant in the saturation region i.e. not
flat curve because this circuit has low output impedance. So high output impedance is
required condition for good performance current mirror. Fig. 4.18 shows the graph
between output impedance and Vdc. The output impedance of this circuit is 718.44 KO at
biasing voltage Vdc = 1.8 V. Fig. 4.19 shows the graph of systematic gain error for this
current mirror circuit. The graph indicate that below 60 ^A the systematic gain error is
approximately 1%. Fig. 4.20 shows the graph between power dissipation and Vdc. The
power dissipation of this circuit is 37 nW at biasing voltage Vdc = 1.8 V.

-1 1 1 1 1 1 r 1 1 1 , 1 1 1 r-

0.0 50,0[j lOO.Op 150.01J 200.0p 250.0^ 300.0p 350.0M 400.0^

Fig. 4.16 lout with respect to lin of improved Wilson current mirror

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 39

 < 6.0p -
U
•o

1 — • — 1 — • — I — ' — I — ' — I — • — 1 — ' — I — • — I — ' — I — ' — r

-0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

VdclV)
Fig. 4.17 Idc with respect to Vdc of improved Wilson current mirror

800M- • 1 . 1 . r . t . 1 . 1 . 1 . 1 . 1 . 1 .

700M-

600M-

500M-
^^
E 400M-

o 300M-
N
200M-

100M-

0-

-100M - 1 1 1 1 1 1 1 , 1 1 1 J 1 1 . , . , . , .

-0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

VDC(V)
Fig. 4.18 Output impedance with respect to Vdc of improved Wilson current mirror

amm^.^mmiie»m-ii3s^st>mimss'its'jsmi^:^ws
NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 40
 1 -l 1 1-
0.0 50.0M IOO.OM 150.01J 200.0|J

>in(A)

Fig. 4.19 Systematic gain error graph of improved Wilson current mirror

. 1 . 1 . 1 . 1 . 1 . 1 . 1 . 1 . 1 . 1 .

40.0|J -

35.0|J -

30.0|J -

25.01J -

1 20.0M -

Q. 15.0M -

10.0M -
^ /
5.0M-

0.0-

-5.0M - I 1 • 1 1 1 . 1 • 1 1 1 . 1 > I 1 1 1 1 1

-0,2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

VDC(V)

Fig. 4.20 Power dissipation with respect to Vdc of improved Wilson current mirror

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 41

4.5 Regulated Cascode Current Mirror

In this current mirror, Vdc is 1.8 V and Vdci is 0.5 V. We have calculated all the results at
Vdci = 0.5 V. Fig. 4.21 shows the graph between input current and output current. In this
current mirror output current does not follow input current. Fig. 4.22 shows the graph
between output current and output voltage. Output current is approximately constant in
the saturation region i.e. flat curve because this circuit has high output impedance. So
high output impedance is required condition for good performance current mirror. Fig.
4.23 shows the graph between output impedance and Vdc. The output impedance of this
circuit is 21 MQ at biasing voltage Vdci = 0.5 V and Vdc = 1.8 V. Fig. 4.24 shows the
graph of systematic gain error for the proposed current mirrors. The graph indicate that
below 20 ^A the systematic gain error is approximately 1% but after 20 ^.A the
systematic gain error is very high. Fig. 4.35 shows the graph between power dissipation
and Vdc. The power dissipation of this circuit is 35.71 ^W at biasing voltage Vdci = 0.5 V.

T • 1 ' 1 • 1 ' r
-100.0IJ 0.0 100.0|J 200.0|J 300.0H 400.0[J 500.0|J

iin(A)

Fig. 4.21 lout with respect to Jin of regulated cascode current min'or

ff-jtaiua'ia»]:aa^'ip*i»aaiw

NATIONAL INSTTTUTE OF TECHNOLOGY KURUKSHETRA Page 42

 . 1 , 1 . 1 . 1 . 1 . 1 . 1 . 1 . 1 . 1 .

3.5|J-

3.0|J-
X^"""
2.5M- /

2.0M-
<

1.5M-

1.0M-

500.0n -

0.0- j , , . 1 I 1 1 1 1 1 1 , , , . 1 1 1 1

-0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

Vdc(V)
Fig. 4.22 Idc with respect to Vdc of improved Wilson current mirror

. 1 . 1 . 1 . 1 . 1 . 1 . 1 . 1 . 1 . r .

20.0M -

15.0M -

? /

_y
10.0M -
o
N
5.0M-

0.0-

, . , . , , , , , , , 1 1 1 1 1 , , , ,

-0.2 0.0 0.2 0.4 0,6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

VDC(V)

Fig. 4.23 Output impedance with respect to Vdc of improved Wilson current mirror

NATIONAL INSTITUTE OF TEOiNOLOGY KURUKSHETRA Page 43

 0.0 50.0tJ 100.0M 150.0M 200.0p

'in(A)
Fig. 4.24 Systematic gain error graph of improved Wilson current mirror

-i—I—,—,—I—I—I—1—I—1—I—.—I—1—1—.—I—1—r
-0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

VDC(V)

Fig. 4.25 Power dissipation with respect to Vdc of improved Wilson current mirror

Uiju ..^va^ag^a^?j^rijagi-^a^.j.->^.t^^tB?g;»^

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 44

4.6 A Novel Regulated Cascode Current Mirror

In proposed circuit 1, Vjc is 2.5 V and Vdc2 is 1.5 V. We have calculated all the results at
Vdci = 0.7 V. Fig. 4.26 shows the graph between input current and output current. In the
proposed circuit output current follow input current upto 20 ^A. Fig. 4.27 shows the
graph between output current and output voltage. Output current is approximately
constant i.e. flat curve which is required condition of current mirror circuit. Fig. 4.28
shows the graph between output impedance and Vdc of proposed circuit. The output
impedance of proposed circuit is 70 MQ at biasing voltage Vdci = 0.7 V and Vdc' = 1.5 V.
Fig. 4.29 shows the graph of systematic gain error for the proposed current mirrors. The
graph indicate that below 20 ^A the systematic gain error is approximately 1 % but after
20 [lA the systematic gain error is very high. Fig. 4.35 shows the graph between power
dissipation and Vdc. The power dissipation of proposed circuit is 29 )iW at biasing voltage
Vdci = 0.7 V which is lower than regulated cascode current mirror.

iOCp 60.Sp SO Op

IjnfA)
Fig. 4.26 lout with respect to lin of novel regulated cascode current mirror

f^-smis^f !»• ^sagCT^MBweafttfaweiiigP a?ft'.Ml,jeaMLg5lgrgTOg!

N A T I O N A L INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 4 5

 a L—a ' • I ' I • ' ' ' • L J L
ISOt -

16,Op

UXJp-

12jQp-

-P
6itp •

4iJp-

2J0p-

0.0
-2^p _,—, , , , , , , , ,—, , , , ,—J , j -
-02 0-0 02 0^ Ofi 0.8 IJO 12 1.4 1.6

VDCM
Fig. 4.27 Idc with respect to Vdc of novel regulated cascode current mirror

80W-I 1 1 1 1 1 1 1 1 L I i I I I t I

TOM

50l«-

J.
o
20t«

101^-

0-

-13V — I — • — I — . — I — I — I — . — { — • — I — . — I — . — 1 — I — r
0 0 02 01 06 08 1.0 1.2 1i 1.6

VDCW
Fig. 4.28 Output impedance with respect to Vdc of novel regulated cascode current mirror

»aBa«agiia>B«)iaaaa««gguaBRi4CBij..ti.ufmB^

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 46

 10.0M - J 1 I 1 L J I I . I 1 I I I 1 1—I—L

5.0M-

0.0-
-5.0M -

-10.0M -

^ -15.0M-

^ -20.0M -

~ -25.0M -

<^ -30.0M -

g -35.0M ^

"" -40.0M -

-45.0M -

-50.0M -

-55.0M -

-60.0M-- " — I — • — I — • — I — " — I ' — I — ' — I — • — I — ' — I — ' 1 — ' 1 — • — I — ' •

-10.0M-5.0M 0.0 5.0M 10.0M 15.0M20.0M25.0M30.0M35.0M40.0M45.0M50.0M

"in(A)

Fig. 4.29 Systematic gain error graph of novel regulated cascode current mirror

J I I I I I I 1 L I I U

SO.Op -

25.0M -

20.0M -

f- 15.0M H
Q.
10.0M

5.0M-

O.O-

-1 ^ r 1 . 1 1 1 1 1 1 1 1 1 1 , 1 p-
-0.2 O.O 0.2 0,4 0.6 0.8 1.0 1.2 1.4 1.6

VDC(V)

Fig. 4.30 Power dissipation with respect to Vdc of novel regulated cascode current mirror

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 47

4.7 High Output Impedance Regulated Cascode Current Mirror

In proposed circuit 2, Vdc is 2 V and Vdd is 0.7 V. We have calculated all the results at
Vdci = 0.7 V. Fig. 4.31 shows the graph between input current and output current. In the
proposed circuit output current follow input current upto 20 ^lA that means it can be used
for low power application upto 20 jxA. Fig. 4.32 shows the graph between output current
and output voltage. Output current is approximately constant in the saturation region i.e.
flat curve because the proposed circuit has high output impedance. So high output
impedance is required condition for good performance current mirror. Fig. 4.33 shows the
graph between output impedance and Vdc of proposed circuit. The output impedance of
proposed circuit is 51 MQ at biasing voltage Vdci = 0.7 V and Vdc =2 V. Fig. 4.34 shows
the graph of systematic gain error for the proposed current mirrors. The graph indicate
that below 20 \iA the systematic gain error is approximately 1% but after 20 \iA the
systematic gain error is very high. Fig. 4.35 shows the graph between power dissipation
and Vdc. The power dissipation of proposed circuit is 35.56 |xW at biasing voltage Vdci =
0.7 V which is approximately same as regulated cascode current mirror.

1 . 1 . 1 . 1 . 1 . 1 . 1 .
30.0M -

25.0M -

20.0M -

<" 15.0M -
3
O
10.0M -

5.0M-

0.0-
, . , . , . 1 • I • 1 1 I 1

0.0 5.0M 10.0M 15.0M 20.0M 25.0M 30.0M 35.0M 40.0M

'in(A)

Fig. 4.31 lout with respect to Ijn of high output impedance regulated cascode current mirror

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 48

 0.0 0.5 1.0 1.5 2.0

VDC(V)
Fig. 4.32 Idc with respect to Vdc of high output impedance regulated cascode current mirror

-1—I—I—I—1—I—I—I—1—I—,—I—I—I—I—I—1—I-
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

VDC(V)
Fig. 4.33 Output impedance with respect to Vdc of high output impedance regulated
cascode current mirror

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 49

 10.0M • J 1 U I • I . I . I _l I L

S.Op-

0.0-

-5.0M •

-10.0M •

-15.0M •
<,
^ -20.0M •

-25.0M •

< -30.0M •
3 -35.0M •
O
-40.0M

^5.0M •
-50.0M •

-55.0M

-60.0M • 1—'—T—'—r -1 1 1 1 r-
T—'—r
-1 0.0M -5.0M 0.0 5.0M 1 0.0M 1 5.0M 2 0 . 0 M 2 5 . 0 M 3 0 . 0 M 3 5 . 0 M 4 0 . 0 M 4 5 . 0 M 5 0 . 0 M

'ln(A)
Fig. 4.34 Systematic gain error graph of high output impedance regulated cascode current
mirror

40.01J

QL

0.0 0.5 1.0 1.5 2.0

VDC(V)
Fig. 4.35 Power dissipation with respect to Vdc of high output impedance regulated
cascode current mirror
m>'»ifl»SSS3^-i/»l»7<''*':^^"Z!!S:S:!SSSTJS^£StS

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 50

 CHAPTER 5
CONCLUSION

5.1 Conclusion
In this dissertation, we propose two current mirror structures "a novel regulated cascode
current mirror (Proposed Circuit-1)" and "high output impedance current mirror
(Proposed Circuit-2)" to improve the output impedance. The Proposed Circuit-1 provides
approximately 3 times higher output impedance (i.e. 70 MQ) than existing regulated
cascode current mirror at the biasing voltage of 0.7 V. The Proposed Circuit-2 provide
approximately 2 times higher output impedance (i.e. 51 MQ) than existing regulated
cascode current mirror at the biasing voltage of 0.7 V. The power dissipation of proposed
circuit-1 is 29 [iW and proposed circuit-2 is 35.56 ^W. The systematic gain error of
proposed circuits are approximately 1 % below 20 jiA input current and after 20 |aA input
current the systematic gain error is very high. Therefore, proposed circuits can be used for
low power application such as sensor, Bio-medical instruments and portable device etc.
The small signal analysis is used to calculate output impedance of current mirror. The
simulation results have been presented to demonstrate the feasibility of the proposed
current mirror circuits.

5.2 Future Scope

In our proposed structure, the output impedance is improved with reduction in power
dissipation but systematic gain error is increased. Infiiture,using cascode and improved
Wilson current mirror, systematic error can be reduced with high output impedance. We
have done analysis on 180 nm technology on circuit level. Further analysis can be done at
lower technology node.

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 52

 REFERENCES

[I] B. Razavi, "Design of Analog CMOS Integrated Circuit", New York: Tata McGraw
Hill 2002.
[2] Naresh Lakkamraju and Ashis Kumar Mai, "A Low Voltage High Output Impedance
Bulk Driven Regulated Cascode Current Mirror" lEEEISCAS, vol. 3, pp. 1-4,2011.
[3] Ajay Kumar Dadoria, Arjun Singh Yadav, and C M Roy, "A New CMOS Voltage
Divider Based Current Mirror Compared with the Basic and Cascode Current
Mirrors," International Journal of Advanced Research in Computer Science and
Software Engineering, vol.3, pp. 1-6, 2013.
[4] Vivek Pant and Shweta Khurana, "Optimal High Performance Self Cascode CMOS
Current Mirror", GlobalJournal of Computer Science and Technology, vol. 11, pp.
60-64,2011.
[5] Tony Chan Carusone, David A. Johns and Kenneth W. Martin, "Analog Integrated
Circuit Design", John Wiley and Sons,Inc,New york 1997.

[6] Klaas Bult, Govert J.G.M. Geelen, "A fast-settling CMOS Op amp for SC circuits
with 90-dB DC gain", lEEEJ. Solid-State Circuits, vol. 25, pp. 1379-1384,1990.
[7] Howard C. Yang, and David J. AUstot, "An Active - Feedback Cascode Current
Source," IEEE Transactions on Circuits and Systems, vol. 37, pp. 644-646, 1990.
[8] Z. Wang, "Analytical Determination of Output Resistance and DC Matching Error in
MOS Current Mirror", lEE Proceedings, vol. 137, pp. 394-404, 1990.
[9] G. Palumbo, "Optimised Design of Wilson and Improved Wilson CMOS Current
Mirrors", Electronics Letters, vol. 29, pp. 818-819, 1993.
[10] Ronald G. Spencer, "Analysis of the Modified MOS Wilson Current Mirror: A
Pedagogical Exercise in Signal Flow Graphs, Mason's Gain Rule, and Driving-Point
Impedance Technique", IEEE Transaction On Education, vol. 44, pp. 322-328,
2001.
[II] Zhao Baishu, Mao Chuanwu, Li Lingwei and Yu Liuyu, "High-Precision Voltage
Controlled Current Source Based on Wilson Current Mirrors", The Tenth
International Conference on Electronic Measurement & Instruments, vol. 1, pp. 166-
169,2011.

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 53

[12] Prateek Vajpayee, A. Srivastava, S.S. Rajput and G.K. Sharma, "Low Voltage
Regulated Cascode Current Mirrors suitable for Sub-lV Operation", IEEE
Transaction, vol. 1, pp. 584-587, 2010.
[13] J. Sarao, Z.J. Wang, Y.L. Wu, and H.L. Kwok, "An improved regulated cascode
current mirror", Elsevier Science Ltd, Solid-State Electronics, vol. 46, pp. 307-312,
2002.
[14] Teresa Serrano and BemaM Linares-Barranco, "The Active-Input Regulated-
Cascode Current Mirror", IEEE Transactions on Circuits and Systems, vol. 41, pp.
464-467,1994.
[15] Bajrang Bansal, Prabhat Ranjan, and Himanshu Kaushik, "Current Mirror Circuits with
Improved Performance," International Journal of Electrical and Electronics
Engineering (IJEEE), vol. 1, pp. 1-6, 2011.
[16] M.T. Belaroussi, D. Benamrouche, and Y. Harabi, "Evaluation and comparison of
BiCMOS and MOS current mirrors," Microelectronics Journal, vol. 29, pp. 895-900,
1998.
[17] Sven Lutkemeier and Ulrich Ruckert, "A Subthreshold to Above - Threshold Level
Shifter Comprising a Wilson Current Mirror," IEEE Transaction on Circuit and
Systems, vol. 57, pp. 721-724,2010.
[18] Eduard sackinger, Walter guggenbuhl, "A High-Swing, High-Impedance MOS
Cascode Circmf\ IEEE Journal of Solid-State Circuits, vol. 25, pp.289-298,1990.
[19] Jaydeep Chikanil, Parag Chaudhari, and Vijay Savani, "Analysis and
Characterization of Various Current Mirror Topologies in 90 nm Technology",
International Journal of Emerging Technology and Advanced Engineering, vol. 2, pp.
151-156,2012.
[20] Cadence Design System, Affirma^'^ Analog Circuit Design Environment User Guide,
2001.
[21] Bajrang Bansal, Prabhat Ranjan and Himanshu Kaushik, "Current Mirror Circuits
with Improved Performance", International Journal of Electrical and Electronics
Engineering (IJEEE), vol. 1, pp. 1-6, 2011.

NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA Page 54

 PUBLICATIONS

[1] Devendra Jakhar and Gaurav Saini, "Design of a novel regulated cascode current
mirror," IEEE International Conference on Computer Communication and Control
(IC4-20I5), Medi-Caps Group of Institutions, Indore, M.P. INDIA, September 2015.
(Accepted)
[2] Devendra Jakhar and Gaurav Saini, "A high output impedance regulated cascode
ciirrent mirror," i'"'' National Conference on Nanoscience and Instrumentation
Technology (NCNIT-2015), NIT Kurukshetra, Haryana ,India, June 2015.

NATIONAL I N S H T U T E OF TECHNOLOGY KURUKSHETRA Page 55