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Chapter 3

Programmable Interface Devices

• We discussed interfacing simple I/O devices such as switches and LEDs. It was assumed that the I/O devices were always
ready for data transfer.
• This assumption is not always valid as the speed of the CPU is much higher than that of the I/O devices such as printer.
• CPU needs to check whether the peripheral is ready for data transfer before it reads from or write to it. Also it needs to
know if the peripheral received the data or not.
• Handshake signals are used to make an agreement between the CPU and the peripherals.
• However implementing such signals needs extra hardware circuit.
• Solution: use Programmable Peripheral Interface (PPI) devices.

3.1 Zilog Parallel Input Output (PIO)

PIO is a programmable I/O interfacing device, specially designed for the Z80. It has two 8-bit I/O ports A and B.

1. Data Bus: D7 − D0
2. I/O lines: A7 − A0 : bidirectional tri-state I/O lines of Port A, used to transfer data between the PIO and a peripheral.
B7 − B0 : Port B I/O lines similar to those of Port A.
3. Handshake signals: four handshake signals, two for each port. However, all of them are used for Port A when in mode 2.
- ASTB - Active low Port A input signal from a peripheral to the PIO. When Port A is configured as an output port, this
signal indicates the acknowledgement of the byte received by the peripheral. When Port A is configured as an input port,
this signal indicates that a byte has been placed in Port A by a peripheral.
10
Chapter 3 Programmable Interface Devices 11
- ARDY Active high Port A output signal from the PIO to a peripheral. In the output mode, the signal indicates that a
byte has been placed in the Port A register and is ready for data transfer. In the input mode, it indicates that the Port
A register is empty and ready to accept the next byte from the peripheral.
- BSTB and BRDY Handshake signals for Port B similar to those of Port A.
4. Power and clock:
5. Interrupt control logic:
- INT Interrupt: an active low output signal from the PIO used to interrupt the Z80.
- IEI Interrupt Enable In: an active high input signal used to form a priority interrupt daisy chain when multiple periph-
erals are connected in the interrupt I/O. The high on this pin indicates that no other peripherals with higher priority are
being serviced.
- IEO Interrupt Enable Out: an active high output signal used in daisy chain priority interrupts. This signal goes high
when IEI is high and the Z80 is not servicing an interrupt from this PIO. This signal blocks lower priority devices from
interrupting when a higher priority device is being serviced.
6. Control signals: - CE Chip Enable: an active low signal and is connected to a decoded address bus.
- B/A Port B or A Select: When this signal is high, Port B is selected, and when it is low, Port A is selected. This signal
is generally connected to address line A0 .
- C/D Control or Data Select. When this signal is high, the control register is selected to write a command, and when it is
low, the I/O (Port A or Port B) register is selected to transfer data between the Z80 and the PIO. This signal is generally
connected to address line A1 .
- M1 , RD , and IORQ All these signals are connected to the corresponding control signals of the Z80.
- Read: When the RD and IORQ signals are active low, the Z80 reads from the selected register.
- Write: When the IORQ is active, but the RD is inactive, the Z80 writes into the selected register.
- Interrupt Acknowledge: When M1 and IORQ are active, the Z80 acknowledges the interrupt from the PIO.
- Reset: When M1 is active and both RD and IORQ are inactive, the PIO is reset.

3.1.1 PIO Modes

• Modes 0 and 1: Mode 0 is for output and Mode 1 is for input. Ports A and B can be used in two ways: simple I/O with-
out handshake signals or interrupt I/O with handshake signals. Each port has two handshake signals: Strobe and Ready.

• Mode 2: specifies the bidirectional data flow using Port A only; and it uses all four handshake signals.

• Mode 3: each bit of Port A and Port B can be configured as input or output. The handshake signals cannot be used in
this mode.

- Control Word: PIO can operate in four different modes. To set up an operating mode, the appropriate control word
must be written in the control register of the port being used as shown in the figure bellow.
12 Chapter 3 Programmable Interface Devices

Example: Figure shows a circuit interfacing the PIO with the Z80. Eight DIP switches are connected to Port A and
eight LEDs are connected to Port B (the buffer is necessary to supply sufficient current to the LEDs).
- Identify the port addresses of Port A and B and control registers.
- Write instructions to initialize Port A as an input port and Port B as an output port. Read Port A, turn on corresponding
LEDs at Port B. The program should continue to monitor the switches.

Solution: To initialize Port A as an input Port A as an input port, D7 = 0 and D6 = 1, and to initialize Port B as an
output port, D7 and D6 should be both 0.

Port A as Input Port : 0 1 0 0 1 1 1 1 = 4FH Mode 1


Port B as Output Port: 0 0 0 0 1 1 1 1 = 0FH Mode 0
PORTA . EQU 80 H ; Port A address
PORTB . EQU 81 H ; Port B address
CNTRLA . EQU 82 H ; Control Register A
CNTRLB . EQU 83 H ; Control Register B

LD A , 01001111 B ; Control word 4 FH for Port A


OUT ( CNTRLA ) , A ; Write in control register A
LD A , 00001111 B ; Control word 0 FH for Port B
OUT ( CNTRLB ) , A ; Write in control register B
READ IN A , ( PORTA ) ; Read DIP switches
OUT ( PORTB ) , A ; Turn on LEDs
JP READ ; Continue to check DIP switches
Chapter 3 Programmable Interface Devices 13
3.2 Intel 8255A Programmable Peripheral Interface

The 8255A has 24 I/O pins, grouped into three 8-bit ports: A, B, and C. Port C bits can be used as individual bits or
grouped into two 4-bit ports: CU and CL .

To communicate with peripherals through 8255A, we need:

1. Determine the addresses of ports A, B, and C and the control register according to the Chip Select (CS) logic and A0 and A1 :

2. Write control word in the control register:

3. Write I/O instruction to communicate with peripherals through ports A, B, and C.

3.2.1 8255A Operating Modes

Mode 0: Simple I/O any of A, B, CU and CL can be programmed as input or output


Mode 1: I/O with Handshake A and B can be used for I/O. Port C provides the handshake signals. Two types of data
transfer can be implemented: status check under software control (Polling) or Interrupt.
Mode 2: Bi-directional with handshake A is bi-directional with C providing handshake signals. B is simple I/O (mode-
0) or handshake I/O (mode-1)
BSR (Bit Set Reset) Mode Only C is available for bit mode access. Allows single bit manipulation for control applications.
14 Chapter 3 Programmable Interface Devices
3.2.2 Control word

3.2.3 Mode 0: Simple Input/Output

- Provides simple input and output operations for each of the three ports.
- No ’handshaking’ is required, data is simply written to or read from a specified port.
- Two 8-bit ports and two 4-bit ports.
- Any port can be input or output.
- Outputs are latched. Inputs are not latched

3.2.4 BSR Mode

- The BSR mode is concerned only with 8 bits port C


- Bits can be set/reset by writing appropriate control words in the control register.
- For a BSR control word D7 = 0,
- It does not change the previous I/O operations configuration of ports A and B
Chapter 3 Programmable Interface Devices 15
Example: Interfacing ADC0801 using the 8255A in Mode 0 and BSR Mode:

- Set up port A to read data from the ADC.


- Set up two handshaking signals: PC0 : to provide a start pulse to begin conversion and PC7 to check the ready status of
the converter.
- The port addresses of the 8255A are: Port A: 20H, Port B:21H, Port C: 22H, Control Register: 23H

Mode 0 control word to specify Port A as input, CL as output (PC0 ), CU as input (PC7 ), Port B is not used.

BSR control word to reset then set PC0 to send a start pulse to the ADC

The following program shows the subroutine AtoD to make one conversion. This code uses the polling technique in which
the CPU is busy waiting for the ADC until the end of conversion.
PORTA EQU 20 H ; Port A address
PORTC EQU 22 H ; Port C address
CNTRL EQU 23 H ; Control register address

AtoD LD A , 10011000 B ; Load mode 0 control word 98 H


OUT ( CNTRL ) , A ; Write the control word
LD A , 00 H ; Load BSR control word to reset PC0
OUT ( CNTRL ) , A ; Write the BSR control word
CALL DELAY ; Wait for sufficient pulse width
LD A , 01 H ; Load BSR control word to set PC0
OUT ( CNTRL ) , A ; Start conversion
READ IN A , ( PORTC ) ; Read bit PC7
RLA ; Place bit PC7 in the carry
JP C , READ ; Wait in the loop until the end of conversion where PC7 is low
IN A , ( PORTA ) ; Read ADC data value
RET
16 Chapter 3 Programmable Interface Devices
3.2.5 Mode 1: Input/Output with Handshake

- Two Groups (Group A and Group B). Each group has one 8-bit data port and one 4-bit control/data port.
- The 8-bit data port can be either input or output. Both inputs and outputs are latched.
- The 4-bit port is used for control and status of the 8-bit data port.
- Interrupt logic is supported

3.2.5.1 Mode 1 Input Control Signals

Port A and B are configured as inputs. Port A uses upper three signals PC3 , PC4 , and PC5 . Port B uses lower three signals
PC2 , PC1 , and PC0 . The function of these signals are:

• STB (Strobe Input). (PC4 for A, PC2 for B): A ’low’ on this input loads data into the input latch. It is Generated by a
peripheral to indicate that it has transmitted a data byte.
• IBF (Input Buffer Full). (PC5 for A, PC1 for B): A ’high’ on this output indicates that the data has been loaded into
the input latch; in essence, an acknowledgement by the 8255A to the device. IBF is set by STB being low and reset by the
rising edge of the RD input
• INTR (Interrupt Request) (PC3 for A, PC0 for B): A ’high’ on this output can be used to interrupt the CPU when an
input device is requesting service. This signal is generated if STB, IBF, and INTE are all at logic 1, and is reset by the
falling edge of the RD signal.
• INTE (Interrupt Enable Flip-Flop): An internal flip-flop used to enable/disable the generation of the INTR signal. The
two flip-flops INTEA and INTEB are controlled by bits PC4 and PC2 respectively, through the BSR mode.
• PC6 and PC7 can be set up as either input or output.

3.2.5.2 Mode 1 Control and Status Word

When the 8255A is in Modes 1 or 2, Port C generates or accepts handshaking signals with the peripheral. Reading Port C
allows the programmer to test or verify the ’status’ of each peripheral and change the program flow accordingly.

The following figure shows:


(a) the associated control signals used for handshaking,
(b) the control word used to setup port A and B in Mode 1 input,
(c) status word which is placed into the accumulator if port C is read.
Chapter 3 Programmable Interface Devices 17
3.2.5.3 Mode 1 Output Control Signals

Port A and B are configured as output ports and controlled using the following signals:

• OBF (Output Buffer Full) (PC7 for A, PC1 for B): This output goes ’low’ to indicate that the CPU has written data
out to the specified port. A signal to the device that there is data to be read. It goes ’high’ again after the 8255A receives
an ACK (Acknowledge) from the peripheral.
• ACK (Acknowledge) (PC6 for A, PC2 for B): A ’low’ on this input informs the 8255A that the data from Port A or Port
B has been accepted, which is a response from the peripheral device indicating that it has read the data.
• INTR (Interrupt Request) (PC3 for A, PC0 for B): A ’high’ on this output can be used to interrupt the CPU when an
output device has accepted the data. It can also be used to request the next data byte for output. INTR is set when OBF,
ACK, and INTE are all one and reset by the falling edge of the WR.
• INTE (Interrupt Enable Flip-Flop): An internal flip-flop used to enable/disable the generation of the INTR signal. The
two flip-flops INTEA and INTEB are controlled by bits PC6 and PC2 respectively, through the BSR mode.
• PC4 and PC5 can be set up as either input or output.

3.2.5.4 Mode 1 Control and Status Word

3.2.5.5 Programming 8255A in Mode 1

The 8255A can be programmed to function using either Status Check I/O (Polling) or Interrupt I/O as shown in figure bellow:
18 Chapter 3 Programmable Interface Devices
(a) The CPU continues to check data status through the IBF line until it goes high. The disadvantage of this technique is
that the CPU is tied up (busy) in the loop.
(b) The INTR line is used to interrupt the CPU assuming that vectored interrupts are available. It may be necessary to read
the status word to identify the port requesting the service.

3.2.6 Mode 2: Bidirectional Data Transfer

- Used in Group A only. One 8-bit, bidirectional port (Port A) and a 5-bit control port (Port C).
- Port B in either Mode-0 or Mode-1.
- Both inputs and outputs are latched.
- The following figure shows two configurations of Mode 2:

82C55A

INPUT CONFIGURATION
D7 D6 D5 D4 D3 D2 D1 D0
pe-
I#O I#O IBFA INTEA INTRA INTEB IBFB INTRB
ed to
ac-
GROUP A GROUP B
l de-
pro- OUTPUT CONFIGURATIONS
pe- D7 D6 D5 D4 D3 D2 D1 D0
ac- OBFA INTEA I#O I#O INTRA INTEB OBFB INTRB

GROUP A GROUP B
s in-
n of - The following
Figure figure
17a! MODE showsWord
1 Status Mode 2 Status Word Format (for Group A only):
Format

D7 D6 D5 D4 D3 D2 D1 D0
OBFA INTE1 IBFA INTE2 INTRA

82C55A GROUP A GROUP B


(Defined By Mode 0 or Mode 1 Selection)

Mode Definition
Figure 17b!Summary
MODE 2 Status Word Format
MODE 0 MODE 1 MODE 2
AlternateINPortOUT
C Pin SignalIN(Mode)
OUT GROUP A ONLY
ACKB (Output
PA0 ModeOUT
IN 1) or STBB (Input
IN Mode
OUT 1) !
PA1 Mode
STBA (Input IN 1OUT
or Mode 2) IN OUT !
PA2
ACKA (Output
IN
Mode
OUT
1 or Mode 2
IN OUT !
PA IN OUT
3 IN OUT !
t Enable Flags in Modes
PA4 IN1 and
OUT2 IN OUT !
PA5 IN OUT IN OUT !
PA6 IN OUT IN OUT !
PA7 IN OUT IN OUT !
PB0 IN OUT IN OUT !
PB1 IN OUT IN OUT !
PB2 IN OUT IN OUT !
MODE 0
PB3 IN OUT IN OUT !
PB4 IN OUT IN OUT ! OR MODE 1
PB5 IN OUT IN OUT ! ONLY
PB6 IN OUT IN OUT !
PB7 IN OUT IN OUT !
PC0 IN OUT INTRB INTRB I"O
PC1 IN OUT IBFB OBFB I"O
PC2 IN OUT STBB ACKB I"O
PC3 IN OUT INTRA INTRA INTRA
PC4 IN OUT STBA I"O STBA
PC5 IN OUT IBFA I"O IBFA
PC6 IN OUT I"O ACKA ACKA
PC7 IN OUT I"O OBFA OBFA

Special Mode Combination Considerations change an interrupt enable flag$ the ‘‘Set"Reset Port
C Bit’’ command must be used#
There are several combinations of modes possible#
Chapter 3 Programmable Interface Devices 19
3.3 8255A Interfacing Applications

3.3.1 LEDs and switches

The 74LS244 tri-state buffer is used to supply or sink current to the LEDs. The Switches are connected with a pull-up
resistor (to VCC).

Switch bouncing
3.3.2 Push Buttons A common problem in mechanical switches
When a switch is asserted, we expect a signal like this:

When the button is pressed, the port bit becomes 0 and when the buttonPressed
is released, itRelease
becomes 1.
Ideal switch
Switch Debounce: A common problem in mechanical switches is when a switch is asserted, a idead signal is expected.
tch bouncing
However,
mmon problem the actual
in mechanical signal
switches shows bounce on touch and release.
However, the actual signal is:
a switch is asserted, we expect a signal like this:

Pressed Release
Real switch
Ideal switch
5 to 20 ms 5 to 20 ms

- For a short period of time, the switch signal is bouncing, because switch contacts do not come to rest immediately
H/W solutions
ver, the actual signal is:
- Problem: Although it is one press, the processor mayFor
consider each low
a short period voltage
of time, as onesignal
the switch press. Humans cannot 3press
is bouncing. - 37 a
eral methods.
switch several time in 20 ms, but because the processor is so fast, it can read several low voltages in 20 ms.
mple solution: using
- Solution: a capacitor
De-bouncing using: Real switch

(a) HW solutions:5 toA20 ms


5 to 20 ms simple solution using a capacitor, when the switch is closed, Vout = 0. Because of bouncing, the
When the switch charges
capacitor is closed,
for V
aout =0 time making a small voltage on the capacitor. This small voltage will be interrupted as logic 0.
short
2- Software solutions
aecause (b)
of Software
short period solutions:
of time, the
bouncing switch
the using
signal
capacitor a delay tofor
is bouncing.
charges skip the
3 - 37 bouncing
a short time signal
making a small voltage on the capacitor.
his small voltage will be interrupted as logic 0
5 to 20 ms 5 to 20 ms

When the port pin is When the port pin is


0, wait for around 1, wait for around
Wait until the switch
20ms to bypass the 20ms to bypass the
is released. bouncing.
bouncing.

ldy #20 HH: ldy #20


brclr PTH,#%00000001,HH jsr Delay_yms
3 - jsr
39 Delay_yms
20 Chapter 3 Programmable Interface Devices
3.3.3 Stepper Motor

Stepper motors have input pins that allow current from a supply source into the motor coil windings. Pulsed waveforms in
the correct pattern is used to create the electromagnetic fields to drive the motor. The µP controls the stepper motor by
sending pulsed waveforms to its inputs. µP cannot provide enough current for the motor to move, it needs a driver such as
ULN2003 or ULN2803 IC. The control bits from the processor are connected to the motor through the driver IC.

Wave drive: one coil is energise, Full Step drive: two coils are energise at the same time, Half Step drive: the stepper
motor moves half step at a time.

Half Step drive: A B C D


1 1 0 0 0
Wave drive: A B C D Full Step drive: A B C D 2 1 1 0 0
1 1 0 0 0 1 1 1 0 0 3 0 1 0 0
2 0 1 0 0 2 0 1 1 0 4 0 1 1 0
3 0 0 1 0 3 0 0 1 1 5 0 0 1 0
4 0 0 0 1 4 1 0 0 1 6 0 0 1 1
7 0 0 0 1
8 1 0 0 1

Write a program to make one 7-segment display count from 0 to 9 and


3.3.4 7-Segment
repeats. Displays
The display should change every one second.

The circuit of the


EE 308 dragon board Spring 2010

Making a pattern on a seven-segment LED

• Want to generate a particular pattern on a seven-segment LED:

f b
Display #3
g is
enabled if PP3 is 0
e c
d
• Determine a number (hex or binary) which will generate each element of the pattern

Steps:- – For example, to display a 0, turn on segments a, b, c, d, e and f, or bits 0,

The microprocessor must send an appropriate value to Port B in order to display a certain value following these steps:-
1, 2, 3, 4 and 5 of PTB. The binary pattern is 00111111, or $3f.

1- Make a table having a to g segments’ values for the digits 0, 1, 2, ..9


– To display 0 2 4 6 8, the hex numbers are $3f, $5b, $66, $7d, $7f.
• Put the numbers in a table
1- Make a table having a to g segments’ values for the digits 0, 1, 2, ..9
• Go through the table one by one to display the pattern

2- Enable only one display.


2- Enable only one display.
• When you get to the last element, repeat the loop

3- X points
3- X points at the
at the beginning
beginning of the table
of the table
4- Output
4- Output thethe
valuevalue pointed
pointed by XB to port B
by X to port
5- Wait few milliseconds
5- Wait one second 3 - 22
6- If X points to the last element, go to 3 else go to
6- If X points to the last element, go to 3 else go to 4 4 28

- A time-multiplexing technique is used to display multiple digits simultaneously.


- Repeatedly, enable one display for a short period of time and then disable this display and enable the next one. Due to
the persistence of vision, all digits appear to be lighted at the same time.
- For Port P, to enable one display at a time, only one bit should be 0 and the others should be 1.
Chapter 3 Programmable Interface Devices 21
3.3.5 Keypad

CS12 to a Keypad

essed, it connects two


nd one column

PA3
PA2
PA1
PA0

PA4

PA5

PA6
* 0 #

PA7
3 - 44
- A keypad is an array of switches that can be connected to the 8255A. Four output signals for the row lines and four input
signals for the column lines.
- When a switch is pressed, it connects two conductors one row and one column
- First, all columns are set low (0000), then read the rows. If the rows are all high (1111), this means no key is pressed. If
one of the row signals is low, a key is pressed. - To detect which key is pressed, we reset each column input signal to 0 and
set the others to 1, and read the rows
- If the rows are still high (1111), then we move to the next column and repeat the same process
- If one of the rows is low, then the key is found (row, column)

3.3.6 Buzzer

The sound transducer (buzzer or speaker) can be connected to Z80 via 8255A as shown in the figure in section 3.3.1. A
sound can be generated by creating a digital waveform in the audible range and using it to drive the buzzer. By alternating
the frequency of the generated waveform between two different values, a two tone siren can be generated

3.3.7 LCD