module counter(clk,up,down,reset,outc,err);

input clk,up,down,reset;
output reg err;
output reg [3:0]outc;

always @(negedge clk) begin

//reset
if(reset==0) begin
outc=0;
err=0;
end
else
if (up==1) begin //numaratoare crescatoare
outc=outc+1;
if(outc==15)
err=1;
else
err=0;
end
if(down==0) begin//numaratoare descrescatoare
outc=outc-1;
if(outc==0)
err=1;
else
err=0;
end
if(up==1 && down==0)
err=1;
end
endmodule

module test_counter;
reg clk,up,down,reset;
wire err;
wire [3:0]outc;
counter DUT(clk,up,down,reset,outc,err);
initial begin
reset=0;
#10 reset=1;
up=1;
#200 up=0;down=0;
end
//semnal de ceas
initial begin
clk=0;
forever #5 clk=~clk;
end
endmodule