You are on page 1of 1

08.

402 DIGITAL ELECTRONICS AND LOGIC DESIGN (E)

MODULE-II

PART A

1. Distinguish between decoder and demultiplexer. Implement f =∑(1,3,5,6 ,8,12,15) using


single 4:1Mux.
2. Realize a full adder using half adders.
3. Draw the internal circuit details of a TTL NAND gate.
4. Implement a 4 bit parallel adder using 74LS83 to perform both addition and subtraction.
Explain the logic behind the implementation with example.
5. Design an active high enable, active low output 2 to 4 line decoder using gates.
6. Give the truth table and circuit of a half subtractor.
7. What do you mean by FANIN and FANOUT?
8. What are the advantages and disadvantages of CMOS and ECL families?
9. What you mean noise margin?
10. Draw the logic diagram of BCD adder.

PART B

1. Explain in detail, with circuit, the working of NOT, NAND and OR gates of CMOS.
2. a) Draw the logic diagram of a full subtractor using the NAND gates.
b) Explain the working of a look ahead carry adder.
3. Design and explain BCD to 7 segment decoder.
4. What you mean by current sinking and current sourcing operations of an IC?
5. a) Design and explain 4-bit magnitude comparator.
b) Implement a full subtractor with 1:8 demultiplexer.