Using FPGAs for Software-Defined Radio Systems: a PHY layer
for an 802.15.4 transceiver.
Eloi Ramon
Dept. d’Enginyeria Electrònica
Universitat Autònoma de Barcelona
ETS d’Enginyeria
08193 Bellaterra
Eloi.Ramon@uab.es
Abstract
During the last decade, designers have used
ASICs and DSPs to handle nearly all of the signal-
processing functions associated with radio
communications. Latest generation of FPGAs are
so powerful that they're now displacing both
ASICs and DSPs in software-radio applications.
Software radio is an emerging technology,
aimed to build flexible radio systems, which are
multiple-service, multi-standard, multi-band,
reconfigurable and re-programmable, by software.
In this paper we present the state-of-the-art in
Software-Defined Radio Systems and a PHY layer
for an 802.15.4 transceiver.
1. Introduction
1.1. Software-Defined Radio Systems (SDR)
Software Radio can be described as radio
functionalities defined by software [1]. Currently
the radio interface in wireless systems is usually
implemented by dedicated hardware. The
presence of software defining the radio interface
implies the use of DSPs replacing dedicated
hardware to execute, in real time, the radio
functionalities by software [2].
The most common definitions of SDR systems
are [3]:
• Flexible transceiver architecture, controlled
and programmable by software
• Signal processing able to replace, as much as
possible, radio functionalities
Jordi Carrabina
Dept. de Microelectrònica i Sistemes
Electrònics
Universitat Autònoma de Barcelona
ETS d’Enginyeria
08193 Bellaterra
Jordi.Carrabina@uab.es
• air-interface-download ability: dynamically
re-configurable radio equipment by
downloadable software, at every level of the
protocol stack
• Software realization of terminals multi-mode/
multi-standard
• Transceiver where frequency band & radio
channel bandwidth, modulation & coding
scheme and radio resource and mobility
management protocols can be defined by
software.
• System where parameters can be adapted and
changed by network operator, service
provider or final user.
A wireless receiver developed as a software-
defined radio system consists of just a few
components: an analog RF front-end, an analog-
to-digital converter (ADC) and a demodulator +
decoder.
The RF front-end is easy to use from a wide
number of companies providing analog integrated
down-converters in some of the most used ranges
of frequencies (from ISM to DVB terrestrial or
satellite). Due to high frequencies used in most of
the commonly used frequency ranges, RF front-
end can’t be digital. A lot of experiences have
been reported in lower frequencies (commercial
AM and FM, et cetera) due that these frequencies
are still in the working range of commercial
analog-to-digital converters (ADC). In the cases
of higher frequencies, an analog down-converter
is required to translate frequencies (hundreds of
MHz to some GHz) to an intermediate frequency
(IF) or baseband (BB). At lower frequencies the
used bandwidth of channel can be processed in a
standard ADC.
 Next task is IF processing, consisting The main objectives of an LR-WPAN are ease
normally of filtering and down-sampling at the of installation, reliable data transfer, short-range
high speed generated for the ADC (14 bits at 30 to operation, extremely low cost, and a reasonable
80 MHz typically). IF processing is a suitable battery life, while maintaining a simple and
application for FPGA since its computational flexible protocol.
requirements are relatively simple and its speed Some of the characteristics of an LR-WPAN
requirement is high [4]. are:
• Over-the-air data rates of 250 kb/s, 40 kb/s,
Front End and 20 kb/s using a Direct Sequence Spread
Antenna Digital Local
Oscillator Spectrum (DSSS) modulation
• Star or peer-to-peer operation
• Allocated 16 bit short or 64 bit extended
RF down- A/D Digital addresses
converter converter Mixer • Carrier sense multiple access with collision
avoidance (CSMA-CA) channel access
• Allocation of guaranteed time slots (GTSs)
Digital Low Pass
Filter
• Energy detection (ED)
down-
converter
• Link quality indication (LQI)
• 16 channels in the 2450 MHz band, 10
channels in the 915 MHz band, and 1 channel
in the 868 MHz band
Analysis &
control Decode Demod
In the IEEE 802.15.4 Standard, two different
device types can participate in an LR-WPAN
DSP required features
network; a full-function device (FFD) and a
Figure 1. Standard functions for Software Radio reduced-function device (RFD). The FFD can
Devices operate in three modes serving as a personal area
network (PAN) coordinator, a coordinator, or a
device. An FFD can talk to RFDs or other FFDs,
At the end, baseband demodulation and while an RFD can talk only to an FFD. An RFD is
decoding need a computation-intensive algorithm intended for applications that are extremely
often implemented in a DSP. Actually, new simple, such as a light switch or a passive infrared
generations of FPGAs with DSP blocks, as the sensor; they do not have the need to send large
Altera Stratix devices included in our amounts of data and may only associate with a
development board, allow implementing these single FFD at a time. Consequently, the RFD can
tasks and to join all digital processing is a single be implemented using minimal resources and
chip. memory capacity.

1.2. IEEE 802.15.4 Standard

Wireless personal area networks (WPANs) are

used to transmit information over relatively short
distances. 802.15.4 defines a standard for an ultra-
low complexity, ultra-low cost, ultra-low power
consumption, and low data rate (LR-WPAN)
wireless connectivity among inexpensive devices.
The raw data rate is high enough (maximum of
250 kb/s) to satisfy a set of simple needs but
scalable down to the needs of sensor and
automation needs (20 kb/s or below) for wireless Figure 2. Star and peer-to-peer topology examples
(Source: IEEE 802.15.4 Specifications)
communications.
 An LR-WPAN device comprises a PHY,
which contains the radio frequency (RF)
transceiver along with its low-level control
mechanism, and a MAC sublayer that provides
access to the physical channel for all types of
transfer.
The PHY is responsible for the following
tasks [5]:
• Activation and deactivation of the radio
transceiver
• Energy Detection within the current channel
• Link Quality Indication for received packets
• Clear Channel Assessment for CSMA-CA
• Channel frequency selection
• Data transmission and reception
Figure 3. LR-WPAN device architecture (Source:
IEEE 802.15.4 Specifications)
The MAC sublayer handles all access to the
physical radio channel and is responsible for the
following tasks [5]:
• Generating network beacons if the device is a
coordinator
• Synchronizing to the beacons
• Supporting PAN association and
disassociation
• Supporting device security
• Employing the CSMA-CA mechanism for
channel access
• Handling and maintaining the Guaranteed
Time Slot (GTS) mechanism
• Providing a reliable link between two peer
MAC entities
The upper layers, shown in figure3 in a
graphical representation, consist of a network
layer, which provides network configuration,
manipulation, and message routing, and an
application layer, which provides the intended
function of the device.
In this paper we will introduce the PHY layer
for the 2.4 GHz ISM band.
The paper is structured as follows. Next
section describes the architecture of the
transceiver. The implementation issues are
presented afterwards. In the concluding section we
outline the main features of the designed system
and discuss on their application scope and future
work.
2. Architecture of transceiver
2.1. RF Front-end
Currently transmitters and receivers are based on
the traditional super heterodyne scheme (Figure
4). The RF and IF stages are completely analog.
Figure 4. Traditional heterodyne receiver
Only the BB stage is digital, usually built in
dedicated hardware. In Figure 4 the signal is
picked up by the antenna. The next step is to filter
the signal with a band-pass filter (BPF) and to
amplify it with a low-noise amplifier (LNA). The
resulting system band is converted to a lower
frequency band by multiplying it with a local
oscillator (LO). A low-pass filter (LPF) isolates
the down-converted system band. Then the analog
gain control (AGC) block tries to normalize the
signal power for an optimal use of the analog
digital converter (ADC). The next step is to isolate
one channel from the system band. First the signal
is multiplied with a voltage-controlled oscillator
(VCO). The Digital-Base-Band block controls this
VCO. A digital analog converter (DAC) is used to
convert the digital control signal of the Digital-
Base-Band block to an analog signal.
This analog signal controls the VCO. After the
signal is multiplied with the VCO, the signal is
filtered with a LPF and finally sampled (ADC).
Because some mobile system standards use
quadrature modulation techniques, both the in-
phase (I) and quadrature-phase (Q) component are
extracted and sampled. These two bit streams are
sent to the digital base band processing.
The ideal software-radio receiver is shown in
Figure 5. The analog stage is as small as possible.
Figure 5. The ideal software-radio receiver
The analog stage consists only of the antenna,
the BPF and the LNA. The A/D conversion
(ADC) is done immediately after the LNA, in
order maximize the re-programmability of the
system.
At this moment, the ideal software radio is not
realizable. There are several matters, which cause
this [6]. For example it is impossible to build
antennas and LNAs on a working bandwidth
ranging from hundreds MHz to units or tens of
GHz. The only way to guarantee the multi-band
feature is to have more RF stages. Also, jitter
effects limit the possibility of A/D conversion
directly at the RF band. The most promising
solution for the moment is known as Digital Radio
receiver, shown in Figure 6.
In this solution, the RF stage is still
completely analog, but the A/D converter samples
the spectrum allocated at IF immediately after the
RF stage.
MAXIM Semiconductor disposes of a wide
variety of Low Noise Amplifiers (LNAs), Power
Amplifiers (PAs), down-converters and up-
converters in the range of 2,4 GHz ISM band,
with a very small footprints and low cost.
Figure 6. Digital software-defined radio receiver
2.2. IF Stage
The IF stage of the Digital Radio transceiver
consists of the programmable down-converter
(PDC) which provides the following operations
[2]:
• down conversion: digital conversion from IF
to BB, by using a look-up table containing
the samples of a sinusoidal carrier. The look-
up table replaces the local oscillator used in
the analog down converter.
• channelization: selection of the carrier and
channel which is performed by digital
filtering. In analog receivers, analog filters
with very stringent requirements are used.
• sample-rate adaptation: under-sampling of the
channelization-filter-signal output, to match
the sample rate to the selected channel
bandwidth. The bandwidth of a channel is
compared to the spectrum of the A/D input
signal a narrow-band signal. Therefore the
sample rate can be much lower to accomplish
the required processing power.
The local oscillator or NCO consists of a
phase accumulator, which is just a register, and an
adder, both available as standard library blocks for
virtually all FPGAs. The phase value in the
accumulator drives a sine/cosine lookup table,
which you can implement in a simple ROM. The
mixer is nothing more than a pair of digital
multipliers, now available as dedicated hardware
resources in the latest generation FPGAs.
2.3. Demodulation and decoding
The 2450 MHz PHY employs a 16-ary quasi-
orthogonal modulation technique. During each
data symbol period, four information bits are used
to select one of 16 nearly orthogonal pseudo-
random noise (PN) sequences to be transmitted.
The PN sequences for successive data symbols are
concatenated, and the aggregate chip sequence is
modulated onto the carrier using offset quadrature
phase-shift keying (O-QPSK).
Software radio technology requires the use of
transmitter and receiver pulse-shaping filters to
compensate for the non-ideal frequency response
of wireless channels. Pulses transmitted through a
channel are usually smeared, and these smeared
pulses can cause intersymbol interference (ISI).
ISI occurs when neighboring symbols interfere
with the detection of each desired symbol.
Transmitter and receiver pulse-shaping filters are
used to mitigate intersymbol interference by
limiting the bandwidth of the transmitted signal.
The raised-cosine filter is a commonly used
pulse-shaping filter. By controlling the filter’s
roll-off factor β, the design can be optimized for
less excess bandwidth (β closer to 0) or for less
ISI (β closer to 1). The modulation scheme for
each wireless standard requires a different roll-off
factor.
In a multi-standard software radio, the pulse-
shaping filter structure remains constant while the
coefficients and the roll-off factor must be field-
programmable. Similarly, the key parameters of
other components need to be re-programmed to
meet the specifications of each supported standard
and to handle variations in operating conditions.
Altera, and tested the model in normal mode,
which resulted in hybrid models and simulations
that were easier to debug.
As a final step, we targeted the whole process
to hardware to verify that hardware computation
was as expected.
To develop the system a DSP development
board Stratix professional edition has been used
with the following features:
• Stratix EP1S80B956 device
• Two-channel, 12-bit, 125 million samples per
second (MSPS) analog-to-digital (A/D)
• Two-channel, 14-bit, 165 MSPS digital-to-
analog (D/A)
• Two Mbytes of 7.5-ns synchronous SRAM
The system developed is a 40MHz-IF
DSSS/QPSK transceiver. In the transmitter side
both signals in-phase and in-quadrature are
converted using the onboard D/A converters to IF
signals connected again to onboard A/D
converters to be demodulated and decoded.
4. Results
Simulations made in MATLAB/Simulink
environment obtained a BER < 10-5 for Eb/No
between 4 and 20 dB through an AWGN channel.
The obtained results accomplish the requirements
of the IEEE 802.15.4 Standard.
Spectrum of the transmitted channel at IF in
40 MHz is showed in figure 7 and is closer to
expected one.

3. Implementation issues

A hierarchical system-level design approach to

design, simulation, and rapid prototyping have
been used as method of handling this type of
design complexity. Using block-diagram system
simulation software helps rapidly evaluate design
strategies and prototype real-time implementation
alternatives in software radio designs.
We designed the first version using only
standard communication and DSP blocksets from
Simulink, running in double precision from start
to end. As a second step, we gradually replaced
Simulink blocks with MegaCores IP blocks from Figure 7. Spectrum of transmitted signal
 Figure 8. Simulink model for PHY layer of 802.15.4 standard
The received constellation for the O-QPSK
modulation after the AWGN channel is presented
in figure 9.
Figure 9. Received constellation after AWGN channel
5. Conclusions and future work
A PHY layer of a compliant IEEE 802.15.4
Standard has been presented. The simulation
result has been positive and demonstrates the
robustness of DSSS-QPSK modulation chosen for
the specified standard.
The future intention is to implement some
aspects of MAC layer and to add the analog RF
stages to convert 2,4 GHz to IF signals and test
the system in a true 802.15.4 environment.
References
[1] Herbrig, H., Lundheim, L., Rossing, N. K.,
“SORT SW-Radio - From Concept Towards
Demonstration”, Proceedings of the ACTS
Mobile Communications Summit 1999.
[2] Cummings, M. and Haruyama, S., “FPGA in
the Software Radio,” IEEE Communications
Magazine, pp. 108 – 112, February 1999.
[3] Buracchini, E., “SORT & SWRADIO
concept”, Proceedings of the ACTS Mobile
Communications Summit 1999.
[4] Mitola III, J., “The Software Radio
Architecture,” IEEE Communications
Magazine, pp. 26 – 38, May 1995.
[5] IEEE, IEEE Standard 802.15.4™-2003, Part
15.4: Wireless Medium Access Control (MAC) and
Physical Layer (PHY) Specifications for Low-Rate
Wireless Personal Area Networks (LR-WPANs)
[6] Kraemer, B., Chen, P., Damerow, D.,
Bacrania, K., “Advances in Semiconductor
Technology - Enabling Software Radio”,
Software Radio Workshop, Brussels,
Belgium, 1997.