State university of New York at New Paltz Electrical and Computer Engineering Department

Introduction to VHDL
By Dr. Yaser Khalifa
Electrical and Computer Engineering Department State University of New York at New Paltz

What is VHDL?
• VHDL stands for VHSIC Hardware Description Language. • VHSIC is an abbreviation for Very High Speed Integrated Circuit, a project sponsered by the US Government and Air Force begun in 1980 to advance techniques for designing VLSI silicon chips. VHDL is an IEEE standard.

Using VHDL for design synthesis
The design process is a 6 step cycle: • • • • • • Define the design requirement Describe the design in VHDL code Simulate the source code Synthesize, optimize, and fit the design Simulate the design Implement the design

. critical paths. clock requirements. maximum operating frequency.Design requirements Required setup.

The most common of these are: • Top-down : In top-down.Describe the design in VHDL code Prior to this a design methodology should be used to describe the system. Then a description of lower levels follows. . where each block has its defined inputs and outputs and is performing a specific function. the main functional blocks are first defined.

•Bottom-up : In this case first the individual blocks are defined and designed and then they are brought together to form the overall design. . •Flat : In this case the design is normally simple and does not need a hierarchical approach.

.Simulate the source code • This is an important feature of Hardware Description Languages as the simulation is done before the synthesis and design stage.

optimized functions. allow designers to design logic circuits by creating design descriptions without necessarily having to perform Boolean algebra or create technology-specific. .Synthesize. optimize and fit the design • Synthesis tools in VHDL.

.Optimization process. is the process of minimizing the circuitry by means of reducing the sum of product terms. the process is multi-objective and dependent on the expression being realized and the device used in implementation. However.

. is the process of taking the logic produced by the synthesis and optimization processes and placing it into a logic device.Fitting. Place and route. is fitting the logic into the logic device and placing the logic elements in optimal locations and routing the signals from one unit to another in an optimal way.

.Design Entity A design entity is design element in VHDL and consists of: • an entity declaration and • an architecture body.

A B F C D .

B . end AOI .Entity An entity body describes the input and output pins (ports) of the design entity. . entity AOI is port ( A . C . F : out STD_LOGIC ) . D : in STD_LOGIC .

.architecture V1 of AOI is begin F <= not ( ( A and B ) or ( c and D ) ) . end V1 .

Entity Declaration Each port in an entity should include : • name of the signal (identifier) • direction (mode) • data type .

but the source of the buffered signal is always determined by the driving value of the port. .Modes : There are four default modes in VHDL in : input into the entity ( unidirectional) out : output from the entity( unidirectional) inout : input and output to and from the entity ( bidirectional signals ) buffer : behaves in a similar way as inout.

array types string bit_vector std_logic_vector example “abc” “1001” “101Z” .Data Types There are scalar and array data types in VHDL.

sec.35 -1. ps. us.Scalar type character bit std_logic example ‘a’ ‘1’ ‘0’ ‘0’ forcing 0 ‘1’ forcing 1 ‘x’ forcing unknown ‘z’ high impedance ‘-‘ don’t care ‘L’ weak 0 ‘H’ weak 1 ‘U’ uninitialized true false 2. ns. hr boolean real integer time .0E+38 832 -1 fs. ms. min.

Signals An internal connection is described in VHDL as a signal defined inside the architecture. .

A B AB O F C D CD architecture V2 of AOI is signals AB. O : STD_LOGIC . CD <= C and D after 2 NS. end V2 . . begin AB <= A and B after 2 NS. F <= not O after 1 NS. O <= AB or CD after 2 NS. CD.

Concurrent statements are used in data flow and structural descriptions.Concurrent Statements • VHDL statements are grouped into sequential and concurrent statements. Sequential statements are used in bahavioral descriptions Concurrent statements are mainly: Concurrent signal assignment statements with BOOLEAN equations • Selective signal-assignment (with-select-when) Conditional statements (if-then-else) .

C. An event is a change in value. B. . AB <= A and B after 2 NS. D: in STD_LOGIC. An event on the input port A would trigger the assignment to AB port (A... .Concurrent Statements A concurrent signal assignment is triggered by an event on a signal.

.. D: in STD_LOGIC.port (A. C.. A B AB 2 NS . AB <= A and B after 2 NS. B.

A B AB O F . F <= not O after 1 NS.AB <= A and B after 2 NS. CD <= C and D after 2 NS. O <= AB or CD after 2 NS.

Variables must be defined inside a process.Variables Previously we have looked at signals as electrical connections or “pieces of wires”. or be used to store intermediate values in abstract calculations. variable V: STD_LOGIC. Variables can be pieces of wire too. Variables can represent wires. but they can also be more abstract. . before begin (unlike signals which are defined in an architecture). registers.

Components A component is analogous to a chip socket. . It creates an extra interface which allows more flexibility when building hierarchical system out of its component parts.

library IEEE; use IEEE.STD_LOGIC_1164.all;

entity MUX2 is port (SEL, A, B: in STD_LOGIC; F: out STD_LOGIC); end MUX2;

SEL A

F
SELB B

architecture STRUCTURE of MUX2 is component INV port (A: in STD_LOGIC; F: out STD_LOGIC); end component; component AOI port (A, B, C, D: in STD_LOGIC; F: out STD_LOGIC); end component; signal SELB: STD_LOGIC; begin G1: INV port map(SEL, SELB); G2: AOI port map(SEL, A, SELB, B, F); end STRUCTURE;

Variables
Previously we have looked at signals as electrical connections or “pieces of wires”. Variables can be pieces of wire too, but they can also be more abstract. Variables can represent wires, registers, or be used to store intermediate values in abstract calculations. variable V: STD_LOGIC; Variables must be defined inside a process, before begin (unlike signals which are defined in an architecture).

B. C = '1' process (A. Signal assignments always have a delay (even if it is a delta delay ). just like a signal. F <= not V. [ V = ’U’ ] [ V = ’1’ ] [ V = ’0’ ] Variables behave quite differently to signals. B = '0'. V := V nor C. -. .Assume A = '0'. begin V := A nand B.A variable has a name and a type. C) variable V: Std_logic. variable assignments never have a delay. end process.

if we want a value passed between processes. F <= not V. end process. signal F: Std_logic. end process. process (F) begin ... When this process is synthesized. C) variable V: Std_logic. we MUST use a signal. V := V nor C.architecture . B.. A new wire is synthesized to hole the value of the variable each time it is assigned. A B C V V F A variable can be used ONLY inside the process. begin V := A nand B. each variable assignment creates a new logic level.. begin process (A. So. .

u1: xnor2 port map (a(1) . b(1) .GATESPKG. end STRUCT.STD_LOGIC_1164. begin u0: xnor2 port map (a(0) . x(1) . x(2)) . B : in STD_LOGIC_VECTOR ( 3 downto 0).all . F) . b(2) . entity COMP4 is port ( A. x(3) . F : out STD_LOGIC) . use WORK. b(0) . x(1)) . x(0)) . u3: xnor2 port map (a(3) .all. architecture STRUCT of COMP4 is signal x : STD_LOGIC_VEXTOR ( 0 to 3 ). u4: and4 port map (x(0) . u2: xnor2 port map (a(2) . use IEEE. x(2) .Structural Description library IEEE. b(3) . end COMP4. . x(3)) .

b . The process continues to execute until the last statement is reached or it encounters a wait statement. A process is either being executed or suspended. It then suspends itself. . It is executed when one of the signals in its sensitivity list had an event. end process.Process Statement Execution A process is an operation that involves a number of parameters identified in a sensitivity list: proc_x : process (a . c ) begin x <= a and b and c. a change of value.

so can be used to describe hardware at high level of abstraction. It can wait for a period of time (wait for). c . proc_x : process begin x <= a and b and c. end process. or forever (wait . b . The process is used to describe the behaviour of a part of a system without getting into the details of the implementation. a boolean condition to become true (wait until).A wait statement: is a sequential statement which causes a process to be suspended.). . an event on a signal in the sensitivity list (wait on). wait on a .

They are written between begin and end in an architecture.Concurrent statement : It is a statement which execute in parallel with other concurrent statements in the design hierarchy. The most common concurrent statements are a) the process b) the component instantiation c) concurrent signal assignment .

Y := E. An if statement can contain any number of other statements.Sequential Statements If Statements An if statement is a sequential statement which conditionally executes other sequential statements. end if. if C1 = '0' then V := A. W := C. based on the value of a Boolean condition. end if. end if. W := D. . if C2 = '0' then V := B. if C3 = '0' then X := D. else V := C. including other nested if statements.

The condition given at the top of the if statement forms the select input to the multiplexer. C if C1 = '0' then V := A. else V := B. end if A V B .An if statement is synthesised by generating a multiplexer for every signal or variable assigned within the statement.

C1 C2 V V If the condition is false. the previous value of V is fed through the multiplexer unaltered. end if. but the assignment V within the if still synthesizes to a multiplexer. . if C2 = '1' and C3 = '1' then V := not V.In the example below the if statement does not have an else part.

C2. end if. end if. B) variable V: Std_logic. A F <= V. B C2 C3 V V . A. begin if C1 = '0' then V := A. end process. else V := B.process (C1. C3. if C2 = '1' and C3 = '1' then C1 V := not V.

elseif C1 = '1' then F <= B. A. C2. B. C else F <= D. end process C2 F B A . C. process (C0. end if. D) begin if C0 = '1' then F <= A. end if. end if. D elseif C2 = '1' then F <= C. C1.Nested if Statements Each if must be balanced with an end if.

C1. such that only the branch following the first true condition is executed. end process. process (C0. elsif C2 = '1' then F <= C. elsif C1 = '1' then F <= B. A. Here there is no end if after each elseif. else F <= D. B. end if. C2. D) begin if C0 = '1' then F <= A. .The elseif allows multiple tests to be cascaded together. C.

Example: process begin if Clock = ‘0’ then F <= ‘0’. end process. What kind of hardware would by synthesized? . else F <= A. end if.

when "11" => F <= D.Case Statements The expression at the top of the case is evaluated and compared with the expressions following the whens. then control jumps to the statement following end case. . end case. case SEL is when "00" => F <= A. when others => F <= 'X'. when "10" => F <= C. The statments within the matching when branch are executed. SEL 2 A B C D F The others branch will catch any cases not already mentioned explicitly by the when. when "01" => F <= B.

It is possible to cover several cases in the same when branch by separating the values with vertical bars. 24 or 28. In this example the branch is executed if ADDRESS is: 16. when others => end case. 20. case ADDRESS is when 16 | 20 | 24 | 28 => A <= '1'. B <= '1'. .

when others => end case. . B <= '1'.Each branch can also include any number of sequential statements including other nested case statements as well!! case ADDRESS is when 16 | 20 | 24 | 28 => A <= '1'.

B <= '0'. when 8 to 15 => B <= '1'. end case. when 16 | 20 | 24 | 28 => A <= '1'.The null statement means do nothing A <= '0'. . when others => null. case ADDRESS is when 0 to 7 => A <= '1'. B <= '1'.

B <= '1'. case ADDRESS is when 0 to 7 => A <= '1'.It is possible also to cover a whole range using the case statement. when 16 | 20 | 24 | 28 => A <= '1'. when others => end case. when 8 to 15 => B <= '1'. .

case ADDRESS is when 0 to 7 => A <= '1'.If ADDRESS is: 1) =9 2) =19 What will be the values of A and B? A <= '0'. B <= '0'. when 16 | 20 | 24 | 28 => A <= '1'. end case. when 8 to 15 => B <= '1'. B <= '1'. when others => null. .

case is preferred.Case versus if: 1) if is used when priority is desired. . 2) in cases of more than three branches.

for I in 0 to 3 loop F(I) <= A(I) and B(3-I). .FOR Loops The FOR loop is a sequential statement which is used to execute a set of sequential statements repeatedly. end loop. V := V xor A(I).

V := V xor A(I). end loop.The range can be ascending or descending. for I in 0 to 3 loop F(I) <= A(I) and B(3-I). . but the loop parameter cannot change in increments greater than 1. V := V xor A(I). for I in 3 downto 0 loop F(I) <= A(I) and B(3-I). end loop.

. end loop. V := V xor A(I).The loop parameter is technically a constant. end if. which means that its value cannot be changed using an assignment. You cannot jump out of a loop by forcing the value of the loop parameter for I in 0 to 3 loop F(I) <= A(I) and B(3-I). if V = 'X' then I := 4.

.FOR Loop are synthesized by making multiple copies of the logic synthesized inside the loop. one copy for each possible value of the loop parameter.

for I in 0 to 3 loop F(I) <= A(I) and B(3-I). G <= V. V := V xor A(I). end loop. 0 A(0) A(1) A(2) A(0) F(0) B(3) A(1) F(1) B(2) A(2) F(2) B(1) A(3) F(3) B(0) G A(3) . B) variable V: Std_logic. end process. begin V := '0'.process (A.

end loop. and only leaves the loop when the condition is false. while CONDITION loop . . . tests a boolean condition at the top of the loop.LOOPS There are 3 different kinds of loop statements in VHDL: 1) The while loop. .

.2) The unbounded loop statement simply loops forever. exit when CONDITION. 3) for loop Only the for loop is synthesizable. .. exit. end loop. Loop ... . The other loops can be useful in test benches and behavioural models. and that only if the bounds are constant....

. exit L2 when A(J) = B(I). end loop L2.L1: for I in 0 to 7 loop L2: for J in 0 to 7 loop C := C + 1. end loop L1. exit L1 when B(C) = 'U'.

wait for 10 NS. end process ClockGenerator_1. . end loop. wait for 5 NS. wait.ClockGenerator_1: process begin for I in 1 to 1000 loop Clock <= '0'. Clock <= '1'.

Clock <= '1'. . wait.ClockGenerator_2: process begin while NOW < 15 US loop Clock <= '0'. end loop. end process ClockGenerator_2. wait for 10 NS. wait for 5 NS.

ClockGenerator_3: process begin loop Clock <= '0'. wait for 10 NS. wait for 5 NS. exit when NOW >= 15 US. end process ClockGenerator_3. . Clock <= '1'. end loop. wait.

end.Sequential Logic:Latches library IEEE. entity LATCH is port (ENB. architecture BEHAVIOUR of LATCH is begin process (ENB. end process.all. end. use IEEE.STD_LOGIC_1164. D: in STD_LOGIC. end if. D) begin if ENB = '1' then Q <= D. Q: out STD_LOGIC). .

end if. end process. The use of transparent latches is discouraged in some FPGA technologies because the implementation requires asynchronous feedback .process (ENB. D) begin if ENB = '1' then Q <= D.

Edge Triggered Flip-Flops This is achieved by using the signal attribute’EVENT as follows: process (Clock) begin if Clock'EVENT and Clock = '1' then Q0 <= D0. end if. which has a boolean value True or False. end process. Each signal has a signal attribute S’EVENT. . Q1 <= D1.

signal changes value). wait for 10 NS. wait for 10 NS. . . S <= '0'.... S <= '1'. process begin . S <= '1'..S’Evant changes during any delta in which there is an event on the signal (i. wait for 10 NS.e. S <= '0'.

Rising_edge and Falling_edge Functions Testing for a clock edge is such a common requirement that the package std_logic_1164 includes standard functions Rising_edge and Falling_edge . end process.all. end if. library IEEE.. The functions are given a signal of type STD_LOGIC and return a value which is either True or False. .STD_LOGIC_1164. use IEEE. process (Clock) begin if RISING_EDGE(Clock) then Q <= D. ..

Not all synthesis tools support the RISING_EDGE and FALLING_EDGE functions.process (Clock) begin if Clock'EVENT and Clock = '1' then Q <= D. end if. end if. process (Clock) begin if RISING_EDGE(Clock) then Q <= D. end process. . end process.

else Count <= Count + '1'. process (Clock. elsif RISING_EDGE(Clock) then if Load = '1' then Count <= Data. . Reset) begin if Reset = '0' then Count <= "00000000". end if.Asynchronous Reset Describing an asynchronous reset requires that the reset signal is added to the sensitivity list of the process. end if. end process.

elsif RISING_EDGE(Clock) then if Load = '1' then '1' Count <= Data. Reset) begin if Reset = '0' then Count <= "00000000". Data Load Reset Count + Clock > . end if.. signal Count : STD_LOGIC_VECTOR(7 downto 0).Synchronous operations and Asynchronous operations can be described within a single process. else Count <= Count + '1'. begin process (Clock.. end process. . end if.

> . elsif Enable = '1' then Q <= Data. end process. end if. end if.process (Clock) begin if RISING_EDGE(Clock) then Reset Q Data Enable Clock if Reset = '1' then Q <= '0'.

if Reset = '1' then Data Q <= '0'. else Q <= D. Another_Flipflop: process begin wait until Clock = '1'.Wait until Statement It suspends the process until a condition becomes True. The condition can be any Boolean expression. Clock end process. end if. Reset Q > .

Reset Q Data Clock > . end if. else Q <= D. if Reset = '1' then Q <= '0'. end process.Another_Flipflop: process begin wait until RISING_EDGE(Clock).

The most convenient is with a process statement. . dependent upon the values of the inputs and the previous state. There are many ways to describe a finite state machine in VHDL.Finite State Machines • A finite state machine is a sequential logic circuit which moves between a finite set of states. The state transitions are synchronized on a clock.

F <= '0'. variable State: StateType. Clear). G <= '0'. end. . G <= '1'. when Clear => State := Idle. when Stop => State := Clear. G <= '1'. if Reset = '1' then State := Idle. Start. architecture Explicit of FSM is begin process type StateType is (Idle. else case State is when Idle => State := Start. end process.The state of the machine can be stored in a variable or signal. when Start => State := Stop. end if. F <= '0'. end case. F <= '1'. Stop. and the possible states conveniently represented with an enumeration type. begin wait until RISING_EDGE(Clock).

and thus no way to verify their equivalence. which makes debugging easier. as this makes the VHDL code easy to understand. You should choose meaningful names. Otherwise. there is no reliable way to get the VHDL and gate level representations of the FSM into the same known state.State Names Using enumeration type allows you to give symbolic names to the states. but say nothing about the hardware implementation. it is important that finite state machines are initialized by means of an explicit reset signal. The names will also be visible during simulation. In practice. .

if Reset = '1' then State := Idle. else case State is when Idle => State := Start. . F <= '0'. Start. Stop. end case. end if. end process. when Stop => State := Clear.architecture Explicit of FSM is begin process type StateType is (Idle. G <= '1'. F <= '0'. G <= '0'. begin wait until RISING_EDGE(Clock). end. variable State: StateType. when Clear => State := Idle. Clear). G <= '1'. when Start => State := Stop. F <= '1'.

four flip flops will be synthesized. two for the state vector. and assigning the variable state (the state vector) and signal F and G (the outputs).The following description of an FSM consists of a process synchronized on a clock edge. and one each of the two outputs. Thus. .

Clear). F <= '0'. Stop. begin wait until RISING_EDGE(Clock).architecture Explicit of FSM is begin process type StateType is (Idle. . end case. if Reset = '1' then State := Idle. G <= '1'. when Clear => State := Idle. when Start => State := Stop. end process. F <= '1'. when Stop => State := Clear. F <= '0'. G <= '0'. G <= '1'. Start. end if. variable State: StateType. else case State is when Idle => State := Start. end.

Output: process (State) begin F <= '0'. if State = Clear then F <= '1'. if State = Clear or Reset = '1' then State <= Idle. signal State: StateType. end if. elsif State = Idle then G <= '1'. end process. . else State <= Clear. G <= '0'.architecture SeparateDecoding of FSM is type StateType is (Idle. begin Change_state: process begin wait until RISING_EDGE(Clock). end. elsif State = Start then State <= Stop. Start. Clear). end process. Stop. elsif State = Idle then State <= Start. end if.

. Stop.architecture RegistersPlusLogic of FSM is type StateType is (Idle. if Reset = '0' then State <= Idle. elsif State = Idle then NextState <= Start. end process. elsif State = Start then NextState <= Stop. begin Registers: process begin wait until RISING_EDGE(Clock). signal State: StateType. else NextState <= Clear. Clear). end if. else State <= NextState. end. Start. end if. F <= '1'. C_logic: process (State) begin if State = Clear then NextState <= Idle. G <= '1'. end process.

Concatenation • The concatenation operator “&” is used to join together two arrays end to end to make one longer array Signal A.B: STD_LOGIC_VECTOR(7 downto 0). F<= A & B. . Signal F: STD_LOGIC_VECTOR(15 downto 0).

C: STD_LOGIC. Signal F: STD_LOGIC_VECTOR(3 downto 0).B. or even bits with bits.• Concatenation can also be used to concatenate arrays with single bits. F(3) = A F(2) = B F(1) = C F(0) = unchanged . F(3 downto 1) <= (A & B) & C. Signal A.

Rotate left one digit . Signal Reg: STD_LOGIC_VECTOR(7 downto 0). Shift left one digit Reg <= Reg(6 downto 0) & Reg(7). Reg <= Reg(6 downto 0) & ‘0’.• Shift and rotate operations can be performed in one line by combining concatenation with slice names.

Shift and Rotate • In VHDL ’93 these operations can be performed also using the shift and rotate operators: • Shift left / right logical : sll srl • Shift left / right arithmatic : sla sra • Rotate left / right : rol ror .

Shift left one digit Reg <= Reg sll 1. Reg <= Reg(6 downto 0) & ‘0’. Reg <= Reg(6 downto 0) & Reg(7). .Signal Reg: STD_LOGIC_VECTOR(7 downto 0). Rotate left one digit Reg <= Reg rol 1.

...Example Variable A: STD_LOGIC_VECTOR (3 downto 0). A:= “0110”. • What is the value of this expression? A(0) & ‘1’ & A(2 downto 1) “0111” .

• This is illigal because the operator “+” is not defined to work on type Std_logic_vec tor. architecture A1 of ADDER is begin SUM <= A + B. use IEEE. . SUM: out STD_LOGIC_VECTOR(7 downto 0)). end.Operator Overloading library IEEE.all.STD_LOGIC_1164. B: in STD_LOGIC_VECTOR(7 downto 0). entity ADDER is port(A. end.

. • Defining operators to work on new types is called operator overloading. • The package also declares a set of operators which work on the type.all. use IEEE.• The Std_logic_vector type is declared in the package Std_logic_1164. library IEEE.STD_LOGIC_1164.

• There are also some operators that are implicitly defined for all array types. • These are the relational operators > >= < <= = /= .

• “+” is not defined in std_logic_1164. but it can be defined for std_logic_vector and put in a package. • All VHDL synthesis tools provide a package that overloads certain arithmatic operators on std_logic_vector or on related types. .

end. entity ADDER is port(A.all. B: in UNSIGNED(7 downto 0). • Package Numeric_Std includes new array types singed and unsigned to represent numbers and overloaded operators.library IEEE. end.all. SUM: out UNSIGNED(7 downto 0)).NUMERIC_STD. . use IEEE. use IEEE.STD_LOGIC_1164. architecture A1 of ADDER is begin SUM <= A + B.

signal A. C: STD_LOGIC. . B. F<= (A nand B ) xor (not C). F <= A + B . A B C F signal A. B: STD_LOGIC_VECTOR.

Others will make use of macro-cells optimized for the target technology. .Synthesis of Arithmetic • The synthesis of the arithmetic operators depend on the synthesis tool. depending on which one you choose. • A plus operator (+ ) can be implemented in hardware using a ripple carry or a carry lookahead scheme. The implementation will be smaller or faster. • Some tools will map the operators to discrete gates.

Discrete Gates ADDER8 Non-optimal connection of cells Optimized structure of cells .F <= A + B .

ADDER8 Technology independent VHDL code C1: ADDER8 port map (A.F <= A + B . ADDER8 Vendor Specific VHDL code .B.B).

• This would make your code vendor specific. sometimes you are forced to compromise technology independence in favour of efficiency. you will need to instantiate the macro-cell directly in your VHDL code.• If your synthesis tool can not map an arithmetic operator to an optimized macro-cell. . • However.

F <= A + B . + Constraints Ripple Carry Carry Look-ahead .

C1: SMALL-ADDER … (Ripple Carry Adder) C1: FAST_ADDER8 … (Carry Look-Ahead Adder) Ripple Carry Carry Look-ahead .

Resource Sharing • Resource sharing allows a single hardware to be shared by more than one VHDL operator • Some tools share resources automatically. -. C. K) begin if K then Z <= A + B. K Z A B C D + + .8 Bit else Z <= C + D. end process. D. end if. process (A. B.

C. end process. end if. A B C D K A C B D + K Z + + Z .8 Bit else Z <= C + D. D. -. B.process (A. K) begin if K then Z <= A + B.

process (A. begin if K then V1 := A. V2 := D. Z <= V1 + V2. B. • If your tool does not do resource sharing. V2 := B.. end process. V2 : . else V1 := C. end if. . D. you must rewrite your code to achieve same results.. K) variable V1. C.

State Machines (Again!) Inputs Input Logic Output Logic outputs .

• In order to eliminate the output registers and synthesize a pure state machine. we must re-write the VHDL description. • In order to synthesize the correct hardware. we must split the description into at least two processes. .• A State Machine should not have registers at the output stage.

Exercise
• What is the minimum number of processes necessary to describe this architecture for synthesis?
A
B

C

D

E
• • • • • • 2 processes (AC) (BDE) 4 processes (AC) (B) (D) (E) 3 processes (A) (CE) (BD) 4 processes (A) (BC) (D) (E) 2 processes (ABCE) (D) 3 processes (A) (BCE) (D)

entity FSM1 is port (Clock : in std_logic; SlowRAN: in std_logic; Read, Write: out std_logic); ST_Read end entity; architecture RTL of FSM1 is begin SEQ_abd_COMB: process type StateType is (ST_Read, ST_Write, ST_Delay); ST_Delay variable State:StateType := ST_Read; begin wait until rising_edge*Clock); case State is when ST_Read => Read <= ‘1’; Write <= ‘0’; State := ST_Write; when ST_Write => Read <= ‘0’; Write <= ‘1’; if (SlowRam = ‘1’) then State := ST_Delay; else State := ST_Read end if; when ST_Delay => Read <= ‘0’; Write <= ‘0’; State := ST_Read; end case; end process SEQ_AND_COMB; end architecture RTL;

ST_Write

entity FSM2 is port (Clock : in std_logic; SlowRAN: in std_logic; Read, Write: out std_logic); end entity; architecture RTL of FSM2 is type StateType is (ST_Read, ST_Write, ST_Delay); signal CurrentState, NextState: StateType; begin SEQ: process (Clock) begin if rising_edge(Clock) then if (Reset = ‘1’) then CurrentState <= ST_Read; else CurrentState <= NextState; end if; end process SEQ; COMB: process (CurrentState) begin case CurrentState is when ST_Read => Read <= ‘1’; Write <= ‘0’; NextState := ST_Write; when ST_Write => Read <= ‘0’; Write <= ‘1’; if (SlowRam = ‘1’) then State := ST_Delay; else NextState := ST_Read end if; when ST_Delay => Read <= ‘0’; Write <= ‘0’; NextState := ST_Read; end case; end process COMB; end architecture RTL;

ST_Read

ST_Write

ST_Delay

else CurrentState <= NextState.SEQ: process (Clock) begin if rising_edge(Clock) then if (Reset = ‘1’) then CurrentState <= ST_Read. end if. end process SEQ. .

Write <= ‘1’. NextState := ST_Read. if (SlowRam = ‘1’) then State := ST_Delay.COMB: process (CurrentState) begin case CurrentState is when ST_Read => Read <= ‘1’. . else NextState := ST_Read end if. when ST_Write => Read <= ‘0’. Write <= ‘0’. end case. NextState := ST_Write. end process COMB. Write <= ‘0’. when ST_Delay => Read <= ‘0’.

SlowRam D Q Q Read Reset D Q Write Q Clock .