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ferent gain levels, namely 0 dB (1 ×), 5 dB (1.778 ×), 6 dB (2 ×), necting two E96 values in parallel.
10 dB (3.162 ×), 14 dB (5 ×) and 20 dB (10 ×). The first table is At the higher gain levels, and particularly at high frequencies,
also necessary if you want to convert the filter from low-pass a very fast type of opamp must be used to avoid having it
to high-pass. affect the signal transfer. In order to keep deviations (in fre-
Table 2 shows more practical component values for the same quency and amplitude) as small as possible, the use of 1%
gains. Exact E12 values have been used for the capacitors, components is highly recommended (especially at higher
and we have calculated the theoretical values of the resistors gains).
for you so they can be implemented very accurately by con- (024115-1)

Long-Interval Timer 004

G. Ruschitzka

Occasionally there is a need for a timer circuit for tasks such as C2 C3

switching off a circuit element (such as an LC display) after a R4
47µ 100n IC1 16
given interval or generating a time delay for an application. 27k

Short intervals can be conveniently generated using a 555 CTR14 3
timer, but if the switch-off time lies in the range of minutes or R3
470k 5
longer, a 555 is no longer suitable due to the large value R1
10 14
required for the capacitor, which leads to inaccuracies or insta- 220k RX + 7
9 CT 13
R2 C1 CX 8
bility. In such cases, a digital counter circuit with an oscillator 2k2 9
is a better solution. TRIGGER 220n 11
The 74HCT4060 IC, with its built-in oscillator, can cover a wide 12
CT=0 3
range of frequencies in a simple and reliable manner and can
T1 D1 R5 8
also generate very low frequencies. The 14-bit divider chain

can divide the oscillator frequency by up to 16,384, which
BC237 BAT48
makes it easy to obtain long time intervals.
024065 - 11
The circuit presented here acts like a digital monostable. The
timeout time starts when the system is switched on, since a
Low level is initially present on the selected output of the ON TRIGGER TRIGGER

counter IC (Q13 or any other desired output Q2–Q12). This

represents the active (On) state for the connected circuit. After TRIGGER

the counter chain has counted up enough for the selected out-
put to switch to the High state, the oscillator is cut off by tran-
sistor T1 so that no further counting pulses can be generated.
The circuit thus remains in this state. The High signal level rep-
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resents a ‘rest state’ for the connected circuit.
In order to reactive the timeout, a positive pulse is applied to
the Reset input (pin 12). The circuit re-triggers, the Q output following circuit.
goes Low immediately (active) and a new timeout starts. The timeout interval is given by the formula
To make the selection of counter outputs flexible, a DIP switch
can be used as long as only one switch at a time is activated, timeout = 2n ÷ fosc
since otherwise short circuits will be created between the with
counter outputs. It is also useful to connect one of the n = selected output stage (n = 3–13)
switches to Vcc via a small resistance. If this switch is acti- fosc = 1 ÷ (2.5⋅(R1⋅C1))
vated, the connected circuit is permanently disabled, while if
neither this switch nor any of the other switches is activated, With the indicated component values (R1 = 220 kΩ, C1 =
the circuit is permanently enabled. This covers all possible 220 nF), the frequency is 8.3 Hz and the timeout interval at Q13
operating situations. It is important to keep the load small. If is 16.5 minutes.
necessary, a CMOS gate (inverter) can be used to buffer the (024065-1)

12/2002 Elektor Electronics 23