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2, FEBRUARY 2002

**Design of Highly Linear Tunable CMOS OTA for
**

Continuous-Time Filters

Slawomir Koziel and Stanislaw Szczepanski

**Abstract—An analytical method based on the standard cussed. Finally, as an example of applying the CMOS OTA, a
**

square-law metal–oxide–semiconductor (MOS) modeling for third-order elliptic lowpass filter with 4.6–29.6 MHz passband

the design of highly linear, fully differential complementary was simulated for 0.5- m HP AMOS14TB process.

metal–oxide–semiconductor (CMOS) operational transcon-

ductance amplifier (OTA) is presented. The proposed circuit

implementation combines a cross-coupled quad cell and a II. DESIGN OF THE LINEARIZED CMOS OTA

source-coupled differential pair, as well as the current mirror

technique in the output stage. As a result, improved linearity A substantial increase in linearity of CMOS OTA can be ob-

of the developed OTA over the large tuning range is obtained. tained by using two unsymmetrical and one symmetrical differ-

SPICE simulations show that for 0.5- m HP AMOS14TB process ential pair as shown in Fig. 1. In this circuit the input stage is

(MOSIS) with a 2.5 V power supply, total harmonic distortion the cross-coupled quad cell formed by two unsymmetrical dif-

(THD) at 2.5 pp is less than 0.5%. The dynamic range is equal ferential pairs ( - ) and a conventional, symmetrical differ-

to 76 dB at power consumption 5.7 mW. The alternative OTA

structures are also discussed and compared to the basic version; ential pair ( ). The second stage is just a classical current

for this circuit THD at 2.5 pp is less than 0.2%, however, the mirror circuit ( - ) with. By proper adding and subtracting

circuit is much more sensitive to the transistor mismatch. As an output currents in input stage, approximate cancellation of the

example, the OTA is used to design a third-order elliptic lowpass remaining nonlinearities can be obtained. Similar circuits have

filter in the high-frequency range. The cutoff frequency of the also been described in [12] and [13].

filter is tunable in the range of 4.6–29.6 MHz.

In this section we describe the complete analysis of the

Index Terms—Complementary metal–oxide–semiconductor proposed OTA circuit. Using the square-law characteristics of

(CMOS) integrated circuits, operational transconductance ampli-

fiers (OTAs), OTA-C filters. MOSFETs in saturation, we obtain the analytical expressions

fully determining the transfer characteristic of the OTA. Subse-

quently, the analytical procedure of nonlinearity cancellation

I. INTRODUCTION via current addition/subtraction is developed. This procedure

provides us with numerical values of the three design parame-

C MOS operational transconductance amplifiers (OTAs) are

widely used to design high-frequency continuous-time fil-

ters where the basic building blocks are OTA-C integrators [1]

ters for which we get the optimal linearity of the overall OTA

circuit.

and [2] that operate in the open-loop configuration near their

unity gain frequencies. Such applications usually require very A. General Remarks

linear OTAs with large-signal swing capability at their inputs. First, all MOSFETs are assumed to operate in their saturation

Several CMOS OTA structures with improved linearity have region and have their bulks connected to their sources. Thus,

been successfully employed in designing high-frequency filters, their drain currents can be characterized to first order by

using the differential pair approach [3]–[10], [14], [15].

In [3] a novel circuit technique (using unsymmetrical and (1)

symmetrical differential pair approach) for realizing linear

CMOS transconductance elements has been developed by Ne- where is the gate to source voltage, is the threshold

dungadi and Viswanathan. The idea was extended to alternative voltage, is the transconductance

transconductor structures with improved linearity [11] [13], parameter, and , , , are the mobility, oxide capacitance

one of which was applied for high-frequency OTA-C filter [12]. per unit area, and channel width and length, respectively. The

This paper describes an analytical design method of a CMOS effect of channel length modulation and other second-order ef-

OTA which employs a cross-coupled quad cell based input stage fects are neglected in this analysis [16] and [17]. The influence

[3] together with an additional linearizing symmetrical differen- of these effects on the OTAs transfer characteristics are shown

tial pair. An alternative version of the OTA with the linearizing via SPICE simulation.

differential pair in the output stage of the circuit is also dis- Let us introduce the following notation: is the

differential input voltage, , are the incremental drain cur-

rents due to in the transistors and , respec-

Manuscript received September 23, 2000; revised November 29, 2001. This

work was supported in part by the Polish State Scientific Research Committee tively, and is the incremental drain current in the transistors

under Grant 8T11B03716. This paper was recommended by Associate Editor . We also define and as the

M. Helfenstein. output current of the circuit in Fig. 1. The reference bias cur-

The authors are with the Faculty of Electronics, Telecommunications and In-

formatics, Technical University of Gdansk, 80-952 Gdansk, Poland. rent is denoted here as . We assume the reference transconduc-

Publisher Item Identifier S 1057-7130(02)05134-0. tance parameter for positive MOS (PMOS) transistors and

1057-7130/02$17.00 © 2002 IEEE

For the pair ( ) we can write an analogous expression B. Theoretical transfer characteristic of the OTAs first stage in Fig. Using (1) and the nota- tion introduced in the previous section. Using normalized variables we get tance parameters for and are and for and are . the transconduc.KOZIEL AND SZCZEPANSKI: DESIGN OF CMOS OTA FOR CONTINUOUS-TIME FILTERS 111 Fig. 1. . From (2) we obtain for (6b) (3) for (6c) . Thus. 1. We also introduce the following normalized variables for (4) and (similarly . we can write We can calculate the inverse functions for (4) and (5)[3] for (6a) (2) in which is potential of the drain of transistor . Fig. Analysis of the OTA for (5) Consider the pair ( ) in Fig. for negative MOS (NMOS) transistors. Simplified schematic diagram of the proposed CMOS OTA. and ). 2. 1.

Fig. NO. symmetrical differential pair. Transconductance characteristic of the OTAs first stage in Fig. Transconductance characteristic g (x). FEBRUARY 2002 Fig.112 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING. Now. 1. is described as . we consider the transistor pair ( ). which is the for (8a) following: for (10a) for (8b) for (10b) for (8c) . y (y (x )) = d. Fig.e. 3. Having (8a)–(8c) we can determine large-signal transconductance characteristic for (7b) for (9a) for (7c) where (7d) for (9b) The above inverse functions will make it possible to calculate for (9c) the transconductance characteristics of the circuit by straight- forward differentiation. This is a follows: conventional. 1. 3 shows the normalized transconductance characteristic cross-coupled quad cell . so one can easily calculate the normalized transfer function . 2 shows the transfer characteristic of the circuit for (7a) in Fig. 49. 2.. the value x is given according to the condition: y (x ) = y i. The output normalized current of the Fig. 4. VOL.

we require the equality (equivalently. and are given by (7d)]. According to (9a)–(9c) and (11a)–(11b). (20) ularity” of the characteristic by .KOZIEL AND SZCZEPANSKI: DESIGN OF CMOS OTA FOR CONTINUOUS-TIME FILTERS 113 We differentiate (9b) and get (13) Inserting (13) into (12) for [recall that . and (21) into the considered equality we arrive at the expression (12) (22) . 1 is . is fully determined by the three parameters: . which in- . left neighborhood of ). according to assumption (iii). Hence. we require to be constant in the right neighborhood of . From (12a) we have ii) The values of and have to be chosen in such a way that vanishes exactly for (19) (i. 5 shows the idea of linearization of the OTAs transfer char- acteristic. for . we obtain the following equation for : Having we can determine the normalized transconductance characteristic as below (14) for (11a) from which we get for (11b) (15) Fig. we have the following assumptions. which is equivalent to making as “flat” as possible. and . . 11(b)].e. (17) we can impose three conditions upon the characteristics and in order to determine uniquely the values of . we obtain Fig. Design Procedure According to assumption (ii) we want to be for The normalized transfer characteristic of the OTA in Fig. . 5. for ). (20). (18) i) The value of parameter has to be chosen in such a way that is constant in the right neighborhood of Now. Taking into account [(11a). we will obtain: . Our aim is to make lowing equality: as linear as possible. Respective transconductance charac. (21) According to (i). Thus. is constant in the to be satisfied. 4 shows the normalized transconductance characteristic whose positive root is . 5. According to Fig. and . In particular. Fig. (16) C. The idea of the OTAs design. iii) The values of and have to be chosen in such a way while from (9a) we have that . that is Inserting (19). Assumptions (ii) and (iii) enable us to compensate the “irreg. dicates that for we can write the fol- teristic is ..

. The transconductance is almost con. Alternative Version of the Linearized OTA equations uniquely determining the values of and . we introduce the . Expressions describing the normal- It means that the transfer characteristic of the circuit is highly ized transfer characteristic and are the same as in linear. the case of the basic version. This is a cause we cannot express as a function of the normalized input significant advantage of the proposed circuit topology since it variable as simply as in the case of the circuit in Fig. We simplifies the linearization of the real OTA. 6.. VOL. much more complex than previously be- rameter is independent of the parameters and . 7. 1. is in- the circuit (in normalized variables) obtained for . NO. istic is. given by (16) and (24). Fig. 49. the symmetrical differential pair ( ). One should notice that the pa. 6 shows the theoretical transconductance characteristic of the first one. . It will be shown in will use the same notation as before. The analysis of the alternative version of the circuit is very stant in the wide range of the normalized input signal variation. Theoretical transconductance characteristic of the circuit (in normalized variables). Simplified schematic diagram of the alternative version of CMOS OTA. those given by (16) and (24).114 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING. and for OTA considered with second order effects. similar to the previous one. and enable us to control the (9a)–(9c). differ slightly (23) from the theoretical ones. and cluded into the output stage of the circuit. Fig. For we get Section III that the optimal values of the parameters . i. The only difference between both versions is that Fig. They are given by (8a)–(8c) and The three parameters .e. 7 shows a and (24) simplified schematic diagram of an alternative version of the CMOS OTA. The derivation of the transfer character- transfer characteristic of OTA. respectively. 2. FEBRUARY 2002 Fig. . Moreover. Combining (18) and (23) together we arrive at the system of two D. that is The linearization technique described in this section can be also implemented in different circuit topology. however.

KOZIEL AND SZCZEPANSKI: DESIGN OF CMOS OTA FOR CONTINUOUS-TIME FILTERS 115 Fig. and as shown in Fig. Complete circuit diagram of the CMOS OTA1. consequently. 9. and. we can write have (25) (26) . . 7. auxiliary potentials . Fig. 8. . Complete circuit diagram of the CMOS OTA2. . for the source-coupled pair ( ) we Considering the transistor pair ( ).

and rewriting them using normalized variables. 2. ) and. for which . 10.116 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING. (28) it is invertible in that interval. that is (27) (31) and One can easily check that considered as a function of is monotonously increasing in the interval [0. thus. Common-mode feedback circuit. TABLE I SPECIFICATION OF OTA DESIGN PARAMETERS TABLE II COMPARISON OF OTA SIMULATED RESULTS (V =0 V = 2 5 V) : Fig. 8 and 9 with a 5-MHz sine wave. we get (29) From (29) one can determine as a function of in the fol- lowing form: (30) Calculating from (25) and (26) we obtain Note that . VOL. Simulated total harmonic distortion (THD) of the proposed OTAs in Figs. . This remark will be referred to in the sequel. 11. Again. Comparing the right-hand sides of (27) and (28). 49. FEBRUARY 2002 Fig. from (29) one can determine – the value of . NO.

the solution with “ ” has to be rejected since it would exceed the interval of invertibility of the function (see for (33a) for (33b) . we can write (32) (35) where is given by (9a)–(9c) and can be obtained through a straightforward differentiation which yields a some.e. Theoretical and simulated transconductance characteristics of OTA1 in Fig. 12. Now. 13. we want to equal zero for .KOZIEL AND SZCZEPANSKI: DESIGN OF CMOS OTA FOR CONTINUOUS-TIME FILTERS 117 Fig. or maining steps (ii) and (iii) give different values of the param- eters and . According to the step (i) of the procedure. Taking into consideration that is a composite func. For the circuit in Fig. Inserting from (7d) and solving (35) with as unknown we what complicated formula (see (33a) and (33b) at the bottom arrive at of the page). (36) From (8a) we have (34) Now. we can calculate transconductance characteristic Now. we take advantage of (31) where was the value of . 7. 9. now we can apply the same design procedure as described in Section II-C. Fig. The re. that is for ). for which . . we get the same optimal value of the parameter . We have tion of . i. Theoretical and simulated transconductance characteristics of OTA2 in Fig. 8. According to (ii)..

we will proceed as (44) follows: For we have (39) (45) Now we replace in (33a) by its Taylor expan- sion. we have (41). On the basis of (32) we can expression: write this in the form (43) (38) from which we get Unfortunately. 14. Thus. VOL.118 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING. 49. 2. NO. that is Combining (37) and (45) together we arrive at the system of two equations uniquely determining the values of and . (21). Monte Carlo simulation results for transconductance of OTA1 for I = 200 A and 1% deviations (with Gaussian distribution) in V and k . (31) and the comment below it). that is (40) and (46) (41) . shown at the bottom of the page. 15. which and calculating it for we get gives (37) (42) According to assumption (iii) we require that Inserting (20). Monte Carlo simulation results for transconductance of OTA2 for I = 200 A and 1% deviations (with Gaussian distribution) in V and k . Considering the latter solution Thus. we cannot determine an analytic expression for by straightforward calculation because the denominator of (33a) equals 0 for . FEBRUARY 2002 Fig. Fig. and (42) into (38) we arrive at the following .

All the design parameters . For the rest of the paper we will refer to the basic version of TABLE III THD VARIATIONS DUE TO LARGE SIMULTANEOUS NMOS TRANSISTOR the linearized OTA as to OTA1 and to the alternative version of WIDTHS CHANGES the circuit as to OTA2. 7. Monte Carlo simulation results for THD of OTA2 for I = 200 A. tion ratio (CMRR). Thus.5V . the new values of the design parameters are . SPICE simulation results of two complete ver- normalized transfer characteristic of the modified circuit is now sions of CMOS OTAs based on circuits in Figs. have normally better dynamic range. The same modification of the the two current sources of value in output stage with OTA in Fig. the drains of the transistors . input voltage 2. Monte Carlo simulation results for THD of OTA1 for I = 200 A. Namely. Comparison of CMOS OTA1 and OTA2 of remains unchanged. in Fig. 7 leads to the new parameter values: . 1 can be reduction of the total power consumption. Furthermore. and ( unchanged). 8 shows a complete diagram of the CMOS OTA1 based the transistors . However. the third-order el- linearity we must satisfy the following equality: liptic OTA-C filter has been designed and simulated. remain unchanged. 1. 8 and 9. nected to (note that such a modification can only work in a single-ended configuration). Moreover. The same can be done for the OTA in Fig. The theoretical transfer characteristic of OTA2 is as linear as the one of OTA1. it turns out that OTA2 is much more sensitive to the transistor mismatch than OTA1. 1 and 7 are pre- given by . while the value A. differential output. . E.5V . 17. input voltage 2. In this case.KOZIEL AND SZCZEPANSKI: DESIGN OF CMOS OTA FOR CONTINUOUS-TIME FILTERS 119 Fig. a current mirror circuit. OTA Modifications to Single-Ended Structures One can easily show that the OTA structure in Fig. 9. while the transcon- modified to a single-ended configuration by simply replacing ductance is not decreased. the inherent symmetry of fully sible. power supply rejection ratio (PSRR) and common-mode rejec- An additional modification of the OTA in Fig. that in the single-ended configuration However. Under assumption that the drains of Fig. using the OTA2 in Fig. III. 9 a complete . The In this section. Note. Similarly. we obtain a 40% on the simplified circuit in Fig. differential OTAs tends to reduce offsets and drift [16] and [17]. can be con. As it will be shown by the SPICE simulations including the second order effects. the design pro. 1 is also pos. to obtain the optimal sented. As a result. the full version of OTA2 performs as good as the full version of OTA1. and 1% deviations (with Gaussian distribution) in V and k . SIMULATION RESULTS cedure described in Section II-C is still valid for the assump- tions (i) and (ii) but the assumption (iii) takes a new form. note that the fully balanced architectures of OTA the transconductance is twice increased in comparison to the as shown in Figs. Fig. are connected to . and 1% deviations (with Gaussian distribution) in V and k . 16.

setting was simulated by varying all nMOS transistor channel widths in the transistors .5. the transconduc- tance is now twice decreased because of the reduction of . 14 and 15 show the Monte Carlo simulation results for AMOS14TB process and simulated using SPICE with the transconductance of the OTA1 and OTA2.5 input voltage. is presented in Fig. The same It follows from our results that OTA2 is much more sensi- rule has been applied to set the values of the biasing voltages.5 A/V for OTA1 and OTA2. and the linearizing differential pair OTAs in Figs. show the transconductance characteristics for both OTA circuits with A. Bias current has been set to 200 A. This widths of transistors . due and 1.10% and acting as current sources and current mirrors have been chosen 0. while the standard deviations of THD are 0. the design parameters .5 .6 A/V in designing both transconductance amplifiers. Carlo simulations have been also performed in order to check how the transistor mismatch affects transconductance and THD of OTA circuits. The mean value of THD is 0. dation of THD of OTA2. The ratios for the transistors for OTA2. and . 8 and 9. Nevertheless. Note that the common-mode feedback circuit (CMFB). 49. while the standard deviations of are 1. fairly complicated. [5]. respec. respectively. Moreover. The level seven models and MOSFETs with V. since the ratio of the transconductance param- with large-signal swing capability at their inputs are well suited eters for nMOS and pMOS transistors can vary within for applications in OTA-C integrators and filters. Monte Fig. respectively. Figs.6 A/V parameters . a range larger than 10% (due to the fact that transconductance Note that it is also possible to obtain a reduction of the power parameters for nMOS and pMOS transistors are determined in consumption of OTAs in Figs. respectively. 11 shows simulated THD of OTA1 ( ) in OTA1 are built with pMOS transistors. However.34% the complete OTA circuits. and A/V . while the and OTA2 with a 5-MHz sine wave. Theoretically obtained The mean value of is 106. . The results are shown in remaining transistors in order to maintain the proper values of Table III and indicate that OTA2 is affected by the variation . 7 is simulation rather than perform analytical considerations due to shown. simulations have been carried out assuming 1% deviation (with V. FEBRUARY 2002 Fig. Thus. so as to ensure operation in their saturation regions. Implementation of tunable zero for phase compensation [4]. 10. 19. and have been used as a starting point for OTA2. nected to and . up to the 2. tive to transistor mismatch than OTA1 and even relatively small Table I shows theoretical and actual values of the design deviations of transistor parameters can cause significant degra- parameters for both OTAs. Figs. for all circuit transistors. Active voltage-mode implementation of third-order elliptic filter. For example. 2. sistors. Fig. 8 and 9 by rescaling the channel different and independent steps of technological process). and 17 show the Monte Carlo simulation results for THD of OTA1 which give the optimal linearity differ slightly from the and OTA2. one obtains circuits with power consumption less than 3 mW and the large-signal swing capability as good as previously. and adjusting of some of the simultaneously by 10 and 10 . It is worth noticing that linearizing pair ( ) in OTA2 is built with nMOS tran- THD of OTA1 and OTA2 are less than 0. One can observe a good agreement between the theoretical and simulated curves.5 and 0. 18. VOL. NO..35% for OTA1 and 0. as shown in Fig. .120 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING. This means that the THD performance of OTA2 can be tively. respectively. 12 and 13. It means that the design procedure described bias current are the same as before. 16 and to the second-order effects the actual values of . one should stress the “flexibility” of the circuits in question: it is possible to find a good tradeoff within the same design methodology. It is much more useful to carry out that type of diagram of the CMOS OTA2 based on the circuit of Fig.m HP Figs. The input voltage equals in Section II can be successfully employed in implementing 2.2%. Gaussian distribution) in and transconductance parameters All p-channel and n-channel transistors have their bulks con. the Table II summarizes the simulated parameters of the designed cross-coupled quad . both OTA circuits even worse.7 A/V for OTA1 and 102. Both OTA circuits were designed for 0. A/V . Transistor parameter deviations and theoretical ones. respectively. . Of course. the fact that the design formulas for considered OTA circuits are the same for both OTAs.20% for OTA1 and OTA2. 17.

1994.6–29. a third-order elliptic filter has been designed giving the optimal linearity of the simulated circuit. The OTA literature (e. 18. 166–176. 20–32. 18 has been applied. 831–834. 29.” transistors and in series with the load capacitors IEEE J. the OTA has been used in designing sponding active implementation as shown in Fig. However.” IEEE Circuits Devices OTA-C integrators used in the filter of Fig. CONCLUSION tained mostly due to the fact that the introduced OTAs architec- tures need relatively small dimensions of the MOS transistors. L. vol.. P.. Mar. 1984. 1985. Changing the external current from 5 A–200 pp. in the proposed OTA structure exhibits potential to be used in the considered filter structure all input and output OTA capac- continuous-time filtering at higher frequencies. Viswanathan. Fig. Geiger and E. 1. Designing a third-order elliptic lowpass filter tunable in the frequency a filter in the megahertz range requires that both extra and para- range of 4. vol. As an prototype filter [14] and [15] was used to carry out the corre- example of application. The simulation results show that sitic capacitances should be taken into account. CAS-31. Theoretical values of the design parameters are close to those As an example. Sánchez-Sinencio. This property is ob. IV. R. etc. The compensation circuit here is accomplished by adding two [2] Y. 18. vol. Tsividis. [7]. Nedungadi and T. 18 is tuned in the very small. [15]). Mag. Filter Example one gets the optimal linearity of the overall OTA circuit. Circuits Syst. itances and some extra capacitances sum up.” IEEE Trans. It confirms and simulated using the OTA in Fig. Moreover. Filter amplitude response is presented in transconductance elements. the cutoff frequency of the filter in Fig. much more than OTA1. 19.. which gives the following values of elements: ACKNOWLEDGMENT pF pF The authors are very grateful to the anonymous reviewers for pF their helpful comments and suggestions during the preparation pF pF of this paper.6 MHz. “Design of linear CMOS as shown in Fig. Oct. so OTA2 with THD deteriorated by variation range of 4. pF pF REFERENCES An effective phase compensation method [4] and [5] for [1] R. Simulated amplitude responses of elliptic filter in Fig. The design procedure provides us with numerical values of the three design parameters for which B. 20. dynamic range. The normalized passive the practical usefulness of the proposed design method.KOZIEL AND SZCZEPANSKI: DESIGN OF CMOS OTA FOR CONTINUOUS-TIME FILTERS 121 Fig. P. [6]–[8] is not shown. 9. Fortunately. The SPICE simulations confirm that the proposed OTAs have a potential for high-frequency applications. [14]. 20. pp. PSRR. Mar. the nominal THD of OTA2 is A. “Active filter design using oper- ational transconductance amplifiers: A tutorial. Solid-State Circuits.g. pp. in the output stage.6 MHz. The simple and effective design method based on the so one can expect a small area occupation of the CMOS OTA square-law MOS modeling has been developed for realizing chip. power consuming. “Integrated continuous-time filter design – an overview. fully balanced tunable CMOS OTA. our OTAs exhibit much better circuit has been implemented using a cross-coupled quad in linearity and comparable (or better) other parameters such as conjunction with a linearizing symmetrical differential pair CMRR. in comparison to other circuits known from the a very linear.6–29. [3] A. Note that automatic tuning circuitry is still attractive. .

13–18.D. Technical University of Gdansk. “Design of a 15-MHz CMOS continuous-time filter with He is currently an Assistant Professor with the Fac- on-chip Tuning. pp. no. R. M. Szczepanski. Strader. 939–947. pp. 1990. Ramírez-Angulo. C. From August to [14] S. evolutionary compu- Circuits. Allen. Geiger. Feb. “A 20 MHz fully-balanced in 1975 and 1986. Symp. Elect. 40.D. . electronic engineering and the M. he was a Visiting Research Associate with Circuits and Systems. 25. circuit theory. in Proc. pp. “High-frequency Department of Electronic Circuits.” IEEE J. 1984. Design of Analog Integrated Circuits continuous time low-pass filter using linearised CMOS integrators. 26. I. 729–731. Nedungadi and R.” and Systems. Symp. 1. Schaumann. analog integrated circuit design in bipolar and CMOS technology. M. Conf. and current-mode analog signal processing. Sánchez-Sinencio. and W. 1997. (with honors) degrees in ters. 23. pp. and Y. Jakusz. R. I. vol. OR.S. Solid-State Circuits. respectively. Guggenbuhl. pp. J.122 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING. R. Howe.” IEEE Trans. Kosciuszko Foundation Fellowship. Schaumann. pp. Alini. Analog and Digital Circuits. Telecommunications two-input CMOS OTA for continuous-time filter applications. “Synthesis of CMOS (INPT). E. 22.” IEEE J. 44. and R. in 1970. Solid-State Circuits. Joehl. Lett. respectively. 1990. and Informatics. Dec. France. vol. 1991. FEBRUARY 2002 [4] A. “A BiCMOS low distortion tunable OTA for continuous-time filters. pp. pp. Portland State University. Circuit Theory and Electronic Networks. vol. 1993. Sun. transconductance-C filter in 2 m technology. 1990. “A voltage-controllable linear MOS search interests include circuit theory. New York: McGraw-Hill. “A linear fully balanced September 1998. 1993.” IEEE J. Electron. Wang and W.” IEEE Trans. 19.S. Faculty of Electronics. “A CMOS OTA with im. analog signal transconductor using bias offset technique. Sansen. Gdansk. he transconductance amplifiers with linearised transfer characteristics. R. fully integrated analog filters. Baschirotto. and S. Poland. [11] P. pp. [12] P. Solid- State Circuits. Krummenacher and N.Sc. Wu. June 1988. Mar. Jakusz. high-frequency transconductance [16] R. and 2002. 43–49. the Faculty of Engineering and Information Sciences at the University of Hert- II. P. Stanislaw Szczepanski received the M.. active filters design. proved linearity based on current addition. Solid-State Circuits. 1188–1191. 1990. and numerical analysis. Toulouse. “High frequency voltage controlled [17] K. M. Ali. 750–758. Szczepanski. IEEE Int. and Ph. A. ulty of Electronics. tation.K. vol. R. Daasch. Laker and W. he was a Visiting Professor with CMOS OTA for VHF filtering applications. Geiger. He [6] H. versity of Gdansk. Circuits Syst. 1992. He is currently an Assistant Professor and Head of the [15] J. vol. and P. Dec. vol. P. Poland. His teaching and research interests are in 2000. 60 papers and holds two patents. on a 223–228. Circuits Syst. He has published more than Inst. Solid-State processing.” in Proc. “High-frequency continuous-time fil. 315–317. 49. vol. Glinianowicz. and N. Eng.” in Proc. 2000. “8–32 MHz tunable BiCMOS continuous-time filter for high-frequency applications. pp. Jan. in 1995. Hatfield. 2296–2299. and R. New York: McGraw-Hill. Technical University of Gdansk. R. 147. Slawomir Koziel was born in Poland. 1905–1915. Portland. Gray. VLSI Design Techniques for amplifiers. Nat. L. Feb. Wu. the Institute National Polytechnique de Toulouse [13] S. 1988–1997. Szczepanski. J. Khorrambadi and P. NO.” was with the Department of Electrical Engineering. L. Gdansk. Szczepanski. From 1990 to 1991. 174–187.” Proc. degree in theoret- [7] F. Czarniak. Khoury. pp.. Castello. IEEE Int. 27. A. June 1986. pp. [10] R. 1994. and Ph. Schaumann.” IEEE J. “A 4-MHz CMOS continuous-time ical physics and mathematics from the Technical Uni- filter with on-chip automatic tuning. S. the Technical University of Gdansk. Gebacki. vol. In 1986. [8] J. and J. E. vol. Feb.-Circuits Devices Syst. [5] M. (with honors) degrees in electronic engineering from Circuits and Systems.” IEEE J. VOL. U. received the M. 2. He has published more than 30 papers and his re- [9] Z. fordshire.

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