S. Gopalan, Amrita Viswa Vidyapeetam, 24.01.

05
VLSI Fabrication
Semiconductor materials
Crystal structures
Defects in crystals
S. Gopalan, Amrita Viswa Vidyapeetam, 24.01.05
Classification of Materials
• Based on mechanical / physical properties:
– Metals
– Ceramics (compound of metal and non-metal)
– Polymers (chains of carbon-carbon and carbon-
hydrogen bond)
• Based on electrical properties:
– Conductors ( = 10
-4
– 10
-6
ohm.cm)
– Insulators ( = 10
10
ohm.cm)
– Semiconductors ( = 10
10
– 10
-4
ohm.cm)
– Superconductors
• Based on ordering of atoms:
– Crystalline
– Amorphous
– Partially crystalline
Based on
atomic nature
and bonding
S. Gopalan, Amrita Viswa Vidyapeetam, 24.01.05
Periodic Table
Semiconducting region
S. Gopalan, Amrita Viswa Vidyapeetam, 24.01.05
Ternary compounds: Al
x
Ga
1-x
As
Electronics: Si
Optoelectronics: binary (GaAs), and ternary compounds
S. Gopalan, Amrita Viswa Vidyapeetam, 24.01.05
(a) Metallic bonding (b) Ionic bonding
Chemical bonding in solids
In sodium chloride (NaCl), Na
being highly electropositive, gives
one electron to chlorine (which is
highly electronegative).
Positive ions in a sea of
electrons.
S. Gopalan, Amrita Viswa Vidyapeetam, 24.01.05
Chemical bonding in solids
In Covalent bonding, the atoms
involved share the electrons in
the outermost shell equally e.g.
Si, CH4, diamond, etc
In Van der waalls bonding,
coulumbic forces hold molecules
or layers of atoms together.
S. Gopalan, Amrita Viswa Vidyapeetam, 24.01.05
Crystalline: ordered arrangement of atoms throughout
the solid
Amorphous: random arrangement of atoms in lattice
(no order)
Partially crystalline: partial short range order (e.g.
some polymers)
Grain boundary
S. Gopalan, Amrita Viswa Vidyapeetam, 24.01.05
Crystalline structure can be of two types:
• single crystal - planes of atom oriented in the
same direction throughout the solid
• Polycrystalline - planes of atoms in adjacent
regions (grains) oriented along different directions
• Silicon substrates used for VLSI Circuits: single
crystal silicon
• Gate electrode for MOSFETs: Polysilicon
S. Gopalan, Amrita Viswa Vidyapeetam, 24.01.05
y
x
z
γ
β
α
c
b
a
Structure of crystalline solids
A UNIT CELL is the is the smallest cell in a lattice, which
when replicated by transalation, rotation etc., yields the
entire soild.
Lattice: 3-dimensional array of points in space
Unit cell is characterized by lattice
parameters
a, b, c: edge lengths along x, y, and
z directions
γ, α, β: inter-axial angles between x-
y, y-z, and z-x respectively.
S. Gopalan, Amrita Viswa Vidyapeetam, 24.01.05
Structure of crystalline solids
Seven crystal systems exist based on geometry (lattice
parameters) of unit cell:
• Cubic: a = b = c; α = β = γ = 90°
• Hexagonal: a = b = c; α = β = 90 °; γ = 120°
• Tetragonal: a = b c; α = β = γ = 90°
• Rhombohedral: a = b = c; α = β = γ 90°
• Orthorhombic: a b c; α = β = γ = 90°
• Monoclinic: a b c; α = γ = 90° β
• Triclinic: a b c; α β γ 90°
S. Gopalan, Amrita Viswa Vidyapeetam, 24.01.05
1. Fix coordinate system and choose vector along direction in the
lattice.
2. Determine components of vector along axes.
3. Reduce to lowest set of integers.
4. Equivalent [100] directions indicated as <100>.
‘ Miller Indices’ for Directions
S. Gopalan, Amrita Viswa Vidyapeetam, 24.01.05
‘ Miller Indices’ for Planes
• Take reciprocals of intercepts and reduce to lowest
set of integers, unless intercept is fraction of unit
cell edge.
• Choose coordinate system
with origin at any lattice
point and orient axes along
edges of cube.
• Determine intercepts of
planes with axes in multiples
of unit cell edges.
S. Gopalan, Amrita Viswa Vidyapeetam, 24.01.05
• “ { } “ : used to denote family of planes.
• {100} : (100), (010), (001), (100), (010), (001)
• Equivalent sets of (100) planes by
rotation of the unit cell within the cubic
lattice: e.g. {100} planes.
S. Gopalan, Amrita Viswa Vidyapeetam, 24.01.05
Basic Crystal Structures
Cubic structures
Hexagonal Close Packed (HCP)
S. Gopalan, Amrita Viswa Vidyapeetam, 24.01.05
Crystal structures of Si and GaAs
Si
GaAs
Diamond structure
For Si, one silicon atom occupies all FCC positions + one silicon
atom occupies tetrahedral sites formed by 1 corner atom and 3
adjacent face centered atoms
Can be thought of as two interpenetrating FCC structures
Zinc Blende (ZnS) structure
S. Gopalan, Amrita Viswa Vidyapeetam, 24.01.05
Simple Cubic (SC)
Cell parameters
Lattice
constant ‘ a ’
Atomic radius ‘ r ’
• Number of atoms per unit cell: 8 corner atoms each shared by 8 adjacent
unit cells 8 x (1/8) = 1 atom/unit cell
• lattice parameter in terms of atomic radius: a = 2r, where ‘ r ’ is the radius
of atom.
• atomic density = number of atoms per unit cell / unit cell volume = 1/(a
3
)
• Number of nearest neighbors: Each corner atom is in contact with 6
adjacent corner atoms
• Atomic packing fraction (APF) = Volume of atoms in unit cell/ unit cell vol
S. Gopalan, Amrita Viswa Vidyapeetam, 24.01.05
Crystal structures of Si and GaAs
a
4
3
• crystal lattice is face centered cubic (FCC), with two atom
basis [at (0,0,0) and (1/4, 1/4, 1/4) ]
- two “interpenetrating” FCC lattices
- lattice constant “a”: cube side length
silicon (rmtemp): 5.43 Å ; GaAs: 5.65 Å
nearest neighbor distance dn =
Atoms/unit cell:
4 atoms inside cube
6 atoms “half” inside at face centers
8 atoms 1/8 inside at corners
total of 8 atoms unit cell
atomic density : 8 / a3
S. Gopalan, Amrita Viswa Vidyapeetam, 24.01.05
Defects in Crystals
• Point defects : missing atoms, extra atoms,
impurity atoms
• Line defects : Edge dislocation, screw dislocation
(1-Dimensional)
• Area defects: stacking faults, etc (2-D)
• Volume defects: precipitates of impurities (3-D)
S. Gopalan, Amrita Viswa Vidyapeetam, 24.01.05
Point defects
vacancy vacancy
substitutional
impurity
substitutional
impurity
interstitial
impurity
interstitial
impurity
self
interstitial
self
interstitial
Frenkel defect Frenkel defect
• Schottky: cation-anion vacancy (e.g. Na+ and Cl-)
• Impurities can either
occupy substitutional or
interstitial sites
• Interstitials can have
atoms of same type (self
interstitials) or impurity
atoms
S. Gopalan, Amrita Viswa Vidyapeetam, 24.01.05
Defect concentrations
n ≅ N
atomic
e
− E 2 kT
– vacancy-interstitial pair:
Frenkel defect
• E
formation
~ 1 eV
– T = 300K: n ~ 10
14
– T = 1300K: n ~ 10
21
n ≅ N
atomic
e
− E k T
• E
formation
~ 2 eV
– T = 300K: n ~ 0
– T = 1300K: n ~ 10
15
– isolated vacancy:
S. Gopalan, Amrita Viswa Vidyapeetam, 24.01.05
Rate constants and
Arrhenius plots
• thermally activated process
– i.e., process must
thermally overcome an
energy barrier
• plot log(y) vs 1/T
if process has the simple
thermally-activated behavior
you will get a straight line!
kT
E
o
A
e y y

⋅ =
0. 000 2
0. 000 4
0. 000 6
0. 000 8
400 600 800
1x10
+003
1. 2x10
+003
1. 4x10
+003
temperature
y
E
A
= 1eV
E
A
= 0.5eV
0.001 0.001 5 0.002 0.002 5 0.003
1x10
+005
1x10
+010
1x10
+015
1/[temperature]
log[y]
E
A
= 1eV
E
A
= 0.5eV
27°C 250°C 500°C 1000°C
S. Gopalan, Amrita Viswa Vidyapeetam, 24.01.05
Line Defects:
Edge dislocation
• Edge dislocation: extra half plane of atoms in lattice
• Formation energy is high, concentration usually low
• Dislocation line is ⊥ to plane of paper
• Above dislocation line bonds are stretched
• Below dislocation line, bonds are compressed
• Dislocation can move (in this case, left or right) – the plane
on which the dislocation moves is called slip-plane
“extra” plane of atoms
dislocation
S. Gopalan, Amrita Viswa Vidyapeetam, 24.01.05
Line Defects:
Screw dislocation
• screw dislocations are most commonly formed during
crystal growth
• Burgers vector indicates the magnitude and direction of
dislocation: in this case it is parallel to dislocation line.
• Screw dislocation: a
portion of crystal is shifted
by a lattice distance by
shear stress
S. Gopalan, Amrita Viswa Vidyapeetam, 28.01.05
VLSI Fabrication
Defects in crystals
Si wafer fabrication
Zone refining
28.01.05
2
S. Gopalan, Amrita Viswa Vidyapeetam, 28.01.05
Topics of last class
• Crystalline and amorphous materials
• Single crystal and poly crystal structures
• Semiconductor materials
• Basic crystal structures
• Crystal parameters and Miller indices
• Structure of Si and GaAs
• Defects in crystals
– Point, line, area and volume defects
• Point defects and line defects
– Vacancy, interstitial, substitutional impurity, frenkel, schottky
– Edge and screw dislocations
3
S. Gopalan, Amrita Viswa Vidyapeetam, 28.01.05
Line Defects:
Edge dislocation
• Edge dislocation: extra half plane of atoms in lattice
• Formation energy is high, concentration usually low
• Dislocation line is ⊥ to plane of paper
• Above dislocation line bonds are stretched
• Below dislocation line, bonds are compressed
• Dislocation can move (in this case, left or right) – the plane
on which the dislocation moves is called slip-plane
“extra” plane of atoms
dislocation
4
S. Gopalan, Amrita Viswa Vidyapeetam, 28.01.05
Line Defects:
Screw dislocation
• screw dislocations are most commonly formed during
crystal growth
• Burgers vector indicates the magnitude and direction of
dislocation: in this case it is parallel to dislocation line.
• Screw dislocation: a
portion of crystal is shifted
by a lattice distance by
shear stress
5
S. Gopalan, Amrita Viswa Vidyapeetam, 28.01.05
B
B B
B
B B
B B
C
C C
C
C C C
C
A A A A A
A A A A A
A
A
A A A
B
B B
B
B B
B B
C
C C
C
C C C
C
A A A A A
A A A A A
A
A
A A A
B
B B B
B B B B B
B
B B B B
B
B
If atoms in a particular layer are
arranged in positions ‘A’, then
the following layer of atoms can
go to position B or position C.
After B, the next layer can be
either C or A
Stacking sequences in crystals
6
S. Gopalan, Amrita Viswa Vidyapeetam, 28.01.05
Area defects: stacking faults
• Stacking sequence example:
– A B C A B C A B C ……..
– A B A B A B A B ……
• Missing or extra plane causes a 2-D defect or
“stacking fault”
– A B C A B C A B A B C (missing plane C)
– A B A B A B C A B (extra plane C)
7
S. Gopalan, Amrita Viswa Vidyapeetam, 28.01.05
Volume defects: precipitates or 2
nd
phase
• The crystal structure of precipitate could be very different
from the original lattice
• undesirable in active region of wafer
• O
2
precipitates in inactive regions are sometimes beneficial
for gettering (removal of defects)
• If impurity atoms in a
particular region get
clustered together, then a
2nd phase is formed.
8
S. Gopalan, Amrita Viswa Vidyapeetam, 28.01.05
Gettering
• Precipitates tend to act as trap sites for dislocations, and other
defects.
• By having a highly strained regions (such as scratching the
back side of wafer), extrinsic gettering can be achieved.
• By having O2 precipitates away from the active region (in the
substrate), you can reduce defects in channel region by pull
them away – called intrinsic gettering.
• Denuded zone – depth in wafer below which precipitates are
present (20-30µm)
• Denuded zone depth needs to be optimum.
p-type silicon p-type silicon
poly (gate) poly (gate)
oxide (channel insulator) oxide (channel insulator)
channel channel channel
n-type silicon n-type silicon
source drain
n-type silicon n-type silicon
source drain
Denuded zone
9
S. Gopalan, Amrita Viswa Vidyapeetam, 28.01.05
Fabrication Starting Point:
• Step1: Metallurgical grade Si from SiO2 (quartzite)
Quartzite is heated with coke, charcoal, etc in an electric
arc furnace to give 98% pure Si
– SiO2 (s) + 2C (s) ÆSi (l) + 2CO
• Step 2: Pulverized Si is treated with anhydrous HCl at
300ºC to form tri-chloro Silane (SiHCl3)
Si + 3HCl = SiHCl3 + H2
Electrode
Liquid Si
10
S. Gopalan, Amrita Viswa Vidyapeetam, 28.01.05
Fabrication Starting Point:
• Step 3: Fractional distillation of SiHCl3 to remove
unwanted impurities
– SiHCl3 is a liquid at room temperature with a boiling
point of 32C
• Step 4: Reduction of SiHCl3 in Hydrogen to form
Electronic Grade Si (EGS)
SiHCl3 + H2 = Si + 3HCl
– Reaction takes place in a reactor containing a
resistance heated Si rod which serves as a
nucleation point for deposition of Si
– Impurity in ppb range
– Polycrystalline Si obtained
11
S. Gopalan, Amrita Viswa Vidyapeetam, 28.01.05
Step 5: Czochralski Bulk Crystal Growth
• Insert a single crystal Si ‘seed’ into melt
• Pull crystal SLOWLY (~ 4 mm/minute) while rotating (for
uniformity).
• “Container-less” process. Results in very few defects.
seed
Grown crystal
silica crucible
Graphite susceptor
melt
RF coil
Anticlockwise rotation
• Molten Si at 1412 C.
• For obtaining single cryustal Si from EGS
12
S. Gopalan, Amrita Viswa Vidyapeetam, 28.01.05
• Add dopants to melt, but
incorporation governed by
distribution coefficient
or segregation
coefficient, k
d
= C
S
/C
L
.
• Common impurities are
C and O from crucible.
Cs and C
L
are equilibrium concentrations of dopant in
solid and liquid near interface
13
S. Gopalan, Amrita Viswa Vidyapeetam, 28.01.05
• Diameter increases as pull rate reduced. Industry grows
large 300 mm diameter boules or ingots.
• As molten Si solidifies, it imitates the structure of the
seed crystal and hence the process results in a huge
single crystal
Czochralski Bulk Crystal Growth
images from Mitsubishi Materials Silicon
http://www.egg.or.jp/MSIL/english/msilhist0-e.html
pull direction
seed
rotation
14
S. Gopalan, Amrita Viswa Vidyapeetam, 28.01.05
• dm/dt = amount freezing per unit time
• ρ = density
• Vpull = pull rate
• A = cross sectional area
Modeling CZ growth
• latent heat of fusion (L): heat flux (power) released is
( )
pull
v A L
t d
x d A
L
t d
m d
L ρ =
ρ
⋅ = ⋅
15
S. Gopalan, Amrita Viswa Vidyapeetam, 28.01.05
• critical factor is heat flow from liquid to solid
– heat flux (power) balance
( )
2
solid
1
liquid pull
x d
T d
A
x d
T d
A v A L ⋅ ⋅ κ = ⋅ ⋅ κ + ⋅ ρ
Heat released
on solidification
thermal diffusion in liquid
from hot liquid towards
solidification interface
+
thermal diffusion in solid from solidification interface
towards cooler sides/end of boule
=
Thermal conductivity of liquid Thermal conductivity of solid
16
S. Gopalan, Amrita Viswa Vidyapeetam, 28.01.05
– interface between liquid and solid should be an isotherm
• temperature fluctuations cause problems!
0
x d
T d
1
=
( )
2
pull solid
d T
L A v A
d x
thermal current
ρ κ ⋅ = ⋅ ⋅
1442443
2
pull
solid
d T L
v
d x
ρ
κ
= ⋅
2
pull
solid
d T L
v
d x
ρ
κ
= ⋅
or
17
S. Gopalan, Amrita Viswa Vidyapeetam, 28.01.05
• most of the heat is lost via radiation from the sides
of the boule
– thermal current still proportional to cross sectional
area A ∝ (diameter)
2
and v
pull
– if the heat sink is from sides of boule:
• thermal resistance inversely proportional to
perimeter ∝ diameter,
• temperature change (“voltage”) = I
thermal
R
thermal
( ) [ ]
pull pull
v diam
diam
constant
v diam constant T ⋅ ∝






⋅ ⋅ ⋅ = ∆
2
( ) T v diam
pull
∆ ⋅ ∝
−1
¨
18
S. Gopalan, Amrita Viswa Vidyapeetam, 28.01.05
•Segregation coefficient for most
dopants are < 1. This implies that
in most cases, impurities are
continuously rejected into melt.
Czochralski Bulk Crystal Growth
Dopant Kd
B 0.8
Al 0.002
Ga 0.008
In 0.0004
O 1.25
C 0.07
P 0.35
As 0.3
Sb 0.023
Cs and C
L
are equilibrium concentrations of dopant in solid
and liquid near interface
K
d
= C
S
/C
L
19
S. Gopalan, Amrita Viswa Vidyapeetam, 28.01.05
Further purification: Float Zone Process
• Also called Zone Refining process
• Used to grow Si with lower
contaminations than obtained from
Czochralski technique
• Start with a solid Si bar with a seed
attached to the bottom. An RF coil is
used to keep a small region molten.
The RF coil is progressively moved
up.
• segregation effects used intentionally
to purify semiconductor material
• As float zone moves up, the liquid
become more richer, while impurities
are removed from the solid
• The process is done in an
controlled ambient using Ar
20
S. Gopalan, Amrita Viswa Vidyapeetam, 28.01.05
Further Steps in (100) Si wafer fabrication:
1. Grind boule into cylinder and put notch on {110}orientation.
2. Saw into wafers, and grinding/ polishing of damage.
3. “Chamfer” edges and chemical-mechanical polish front.
21
S. Gopalan, Amrita Viswa Vidyapeetam, 28.01.05
• desire is to keep number of chips (die) per
wafer high, even as die size increases
• Several challenges with non-uniformities with
larger wafer diameter
1970 1975 1980 1985 1990 1995
0
50
100
150
200
250
300
W
a
f
e
r

d
i
a
m
e
t
e
r

(
m
m
)
Year
Wafer diameter trends
S. Gopalan, Amrita Viswa Vidyapeetam, 31.01.05
VLSI Fabrication
Czochralski process
Liquid Encapsulated Czochralski
Bridgman process
Wafer specification
31.01.05
2
S. Gopalan, Amrita Viswa Vidyapeetam, 31.01.05
Topics of last class
• Area and volume defects
– Stacking faults and precipitates
• Gettering
• Extraction of Electronic Grade Silicon from
quartzite
• Czochralski crystal growth
• Relationship between pull velocity and temp
gradient in solid
• Relationship between pull velocity and crystal
diameter
• Float Zone process
3
S. Gopalan, Amrita Viswa Vidyapeetam, 31.01.05
Gettering
• Process by which defects (e.g. metal atoms) diffuse through
the crystal and get trapped in a gettering site
• O2 precipitates intentionally used in inactive region to
remove defects away from active region.
• Excess oxygen is trapped by rapid cooling. O2 precipitates
are formed when the supersaturated solution is annealed at
high temperatures
“bulk” wafer
“device” region
back side damage
bulk faults
mobile impurities
“bulk” wafer
“device” region
back side damage
bulk faults
mobile impurities
4
S. Gopalan, Amrita Viswa Vidyapeetam, 31.01.05
Gettering
• Precipitate shape and direction depends on
temperature of annealing
– 650C: Rod shaped along [110] direction in (100)
plane
– 800C: square precipitates on (100) planes with
[111] rounded edges
– 1000C: ‘octahedra’ shaped precipitates
• actual starting material oxygen concentration
and process determined by trial device fab
and performance evaluation.
5
S. Gopalan, Amrita Viswa Vidyapeetam, 31.01.05
Fabrication of Si wafer:
• Step1: Metallurgical grade Si from SiO2 (quartzite) by
reduction with coke etc. (98% pure)
• Step 2: Pulverized Si is treated with anhydrous HCl at
300ºC to form tri-chloro Silane (SiHCl3)
• Step 3: Fractional distillation of SiHCl3 to remove
unwanted impurities
• Step 4: Reduction of SiHCl3 in Hydrogen to form
Electronic Grade polycrystalline silicon (impurity in ppb
range)
• Step 5: Czochralski single crystal growth
• Step 6: Further purification: Float Zone process
• Step 7: Boule grinding, wafer slicing and polishing
6
S. Gopalan, Amrita Viswa Vidyapeetam, 31.01.05
Step 5: Czochralski Bulk Crystal Growth
• For obtaining single crystal Si
from EGS
• Molten Si at 1412 C.
• Insert a single crystal Si ‘seed’
into melt and pull while rotating
in anticlockwise direction
• “Container-less” process.
Results in very few defects.
pull direction
seed
rotation
pull direction
seed
rotation
( ) T v diam
pull
∆ ⋅ ∝
−1
As molten Si solidifies, it imitates the structure of the
seed crystal and hence the process results in a huge
single crystal
Diameter increases as pull
rate reduced
7
S. Gopalan, Amrita Viswa Vidyapeetam, 31.01.05
• Initially, when seed comes in contact with liquid, there are a
lot of defects created at the interface due to thermal stress.
In order to prevent these from agglomerating in the crystal,
the initial pull rate is high (small dia neck minimizes
dislocation).
• Later, the pull rate is decreased to get desired diameter.
This technique results in highly perfect crystal.
• Boule and liquid container are rotated in opposite directions
to minimize temperature gradient in liquid.
Czochralski growth principles
8
S. Gopalan, Amrita Viswa Vidyapeetam, 31.01.05
• Furnace evacuated initially and then back filled with inert
gas to maintain strict control of ambient.
• Impurity redistribution at solid-liquid interface governed
by distribution coefficient or segregation coefficient,
kd = C
S
/C
L
.
• Common impurities are C and O from crucible.
• Most of oxygen escapes as SiO (g).
• Magnetic field commonly used to reduce concentration of
defects: the Lorentz force (qVxB) will keep the ionized
impurities away from S-L interface (magnetically
confined CZ).
• Mag. field can be axial or transverse to boule.
Impurities during Czochralski growth
9
S. Gopalan, Amrita Viswa Vidyapeetam, 31.01.05
Oxygen in CZ Silicon
• concentrations typically in 10
16
- 10
18
cm
-3
range
– segregation coefficient k ~ 1.25
• more in solid than liquid
– contact area between crucible and melt decreases as
growth procedes
– oxygen content decreases from seed to tang end
• effects of oxygen in silicon
– ~ 95% interstitial; increases yield strength of silicon via
"solution hardening" effect
– as-grown crystal is usually supersaturated (occurs
above about 6 x 10
17
)
10
S. Gopalan, Amrita Viswa Vidyapeetam, 31.01.05
• Impurity concentration in the solid (C
s
) at any point can be
obtained as a function of initial liquid concentration C
o
,
distribution coefficient k as:
where X is the fraction of liquid solidified
C
S
= k⋅ C
o
⋅ 1 − X ( )
k−1
• This assumes well-mixed liquid
• In reality, the liquid is not well mixed due
to existence of re-circulation cells.
• There is a region near the S/L interface,
where very little mixing occurs – called
boundary layer (b)
Recirculation cells
b
11
S. Gopalan, Amrita Viswa Vidyapeetam, 31.01.05
• The impurities entering solid must diffuse through
this region.
• Taking the effect of boundary layer into account, k
can be replaced by an effective segregation
coefficient k
e
( )
D Vb
e
e k k
k
k

⋅ − +
=
1
Where V is the pull velocity, b is the boundary layer
thickness, and D is impurity diffusivity
12
S. Gopalan, Amrita Viswa Vidyapeetam, 31.01.05
Impurity profile in boule
• The ends of the boule are richer in impurities because of
seggregation effects. When the final amount of liquid
solidifies, all the remaining impurities are trapped.
k = 0.5, Cliquid = 1e17
1.0E+16
1.0E+17
1.0E+18
Percent Solidified
C
o
n
c
e
n
t
r
a
t
i
o
n

(
#
/
c
m
3
)
0
1
13
S. Gopalan, Amrita Viswa Vidyapeetam, 31.01.05
Float Zone process
• segregation effects used
intentionally to purify
semiconductor material
• zone refining consists of
repeated passes through the
solid by a liquid zone
Where L is the length of fusion
zone
• float zone silicon used for high
resistivity
Zone Refining k = 0.5
1E+16
1E+17
1E+18
position x (L=0.1)
C
o
n
c
e
n
t
r
a
t
i
o
n

(
#
/
c
m
3
)
Pass 1
Pass 3
14
S. Gopalan, Amrita Viswa Vidyapeetam, 31.01.05
Modifications in FZ process
Disadvantage of FZ process: doping concentration is
not uniform
• Core doping
– Start with doped polysilicon rod and deposit undoped
poly rod on top to get desired concentration (process
can be repeated)
• Pill doping
– Dopant inserted through small holes drilled on top
• Gas doping
– Gases such as PH3 or AsCl3 injected in the molten
zone
• Transmutation doping (only for n-type doping)
– Isotope changed through exposure to neutrons
15
S. Gopalan, Amrita Viswa Vidyapeetam, 31.01.05
Challenges associated with growth of GaAs:
• Vapor pressure of Ga is 0.001atm while that of
As is ~ 10atm at melting point of Si (1238C).
– Arsenic evaporates and maintaining stoichiometry will
be difficult.
• The thermal conductivity of GaAs (0.07W/cm-K)
is 1/3
rd
of that of silicon (0.21W/cm-K)
– Heat dissipation is more difficult
• Critical resolved shear stress for creating
dislocation is very small (1/4
th
of silicon) at mp
– Very easy to create dislocations in GaAs
ÆGaAs is typically grown by LEC or Bridgman methods
16
S. Gopalan, Amrita Viswa Vidyapeetam, 31.01.05
Liquid Encapsulated Czochralski (LEC)
• A sealant material such as B2O3 is
used on top of GaAs to prevent out
diffusion of Arsenic.
• B2O3 melts at ~400C and seals GaAs.
• Seed crystal is inserted through
sealant on to GaAs.
• Crystal growth occurs usually at
~20atm (high pressre LEC).
• Pull rates around 1cm/hr.
GaAs
B2O3
A slight excess of As is
used to compensate
for some out diffusion
17
S. Gopalan, Amrita Viswa Vidyapeetam, 31.01.05
Bridgman Growth
• Solid Ga and As are fused into a fused silica ampoule, which
is later sealed.
– Smaller temperature gradients result in lower dislocation densities
• Separate As chamber sometimes included in ampoule with
small orifice to maintain stoichiometry
• Tube furnace is made to pass through trough containing
ampoule (ampoule kept stationary to minimize disturbance).
• Molten GaAs crystallizes at bottom. Seed can be used if
necessary.
• Crystal diameter typically 1 – 2”. Growth of larger crystal
requires greater process control.
Ampoule
Seed
18
S. Gopalan, Amrita Viswa Vidyapeetam, 31.01.05
Comparing LEC and Bridgman methods for GaAs
• Higher defect densities of
>10
4
/cm
2
due to vertical
temperature gradient
• Alloying with Indium (0.1%)
can reduce defects, but
makes wafers more brittle
• Used only for small dia
wafers.
• Resistivity higher than
Bridgman (100Mohm-cm)
• Lowest dislocation density
(< 10
3
/cm
2
)
• Large diameter possible
• Problem - low resistivity
wafers
– Vertical bridgman or vertical
giant freeze methods
LEC Bridgman
19
S. Gopalan, Amrita Viswa Vidyapeetam, 31.01.05
Wafer preparation
• Boule characterized for resistivity and crystal perfection
• Mechanically trimmed into proper diameter
• Wafer slicing
– <100> within ±0.5°
– <111>, within 2 – 5 ° off axis
• lapping
– grind both sides, flatness ~2-3 mm
– ~20 mm per side removed
• edge profiling
• etching
– chemical etch to remove surface damaged layer
– ~20 mm per side removed
• polishing
– chemical-mechanical polish, SiO2 / NaOH slurry
– ~25 mm per polished side removed
– gives wafers a “mirror” finish
• cleaning and inspection
20
S. Gopalan, Amrita Viswa Vidyapeetam, 31.01.05
Wafer specifications
– warp: distance between highest and lowest points
relative to reference plane
– bow: concave or convex deformation
wafer
diam.
thickness thickness
variation
bow warp
150 mm
±
0.5mm
675µm
±
25µm

50µm

60µm

200 mm
±


30µm

10µm

30µm

300 mm
±
0.2mm
775µm
±
25µm

≤ 10µm

<30µm

≤ 100µm


21
S. Gopalan, Amrita Viswa Vidyapeetam, 31.01.05
Wafer specifications
• ‘Flats’ used to identify and orient wafers
• Large ‘flat’ perpendicular to [110] direction
– Used to align the wafers during lithography
• Secondary ‘flat’ used to identify doping type
P-type
Primary
Secondary
(111)
(100)
n-type
Primary
Secondary
45deg
Secondary
180deg
S. Gopalan, Amrita Viswa Vidyapeetam, 09.02.05
VLSI Fabrication
Oxidation of Silicon
Properties of SiO2
Mechanism of oxidation
09.02.05
2
S. Gopalan, Amrita Viswa Vidyapeetam, 09.02.05
•SiO
2
is stable down to 10
-9
Torr , T > 1000°C
•SiO
2
can be etched with HF which leaves Si unaffected
•SiO
2
is a diffusion barrier for B, P, As
•SiO
2
is good insulator, ρ > 10
16
Ωcm, Eg = 9 eV!
•SiO
2
has high dielectric breakdown field, 10
7
V/cm
•SiO
2
growth on Si Æhigh-quality Si / SiO
2
interface
The beneficial properties of SiO
2
and the superior
Si/SiO
2
interface are believed to be the principle
reasons for the success of semiconductor
industry.
3
S. Gopalan, Amrita Viswa Vidyapeetam, 09.02.05
Types of SiO
2
used in devices
Poly Si
Substrate
Gate oxide
FOX
LTO
Metal
MOSFET
Field Oxide
Gate Oxide
Low
Temperature
Oxide
• Device Isolation (Field oxide)
• Insulator for MOS device (Gate oxide)
• Inter-metal dielectric (Low-temperature oxide)
• Mask and Pad oxide
D
4
S. Gopalan, Amrita Viswa Vidyapeetam, 09.02.05
• The growth rate, quality, and properties of SiO2
depend on the intended application:
– Gate oxide:
• Very high quality ultra thin oxides (currently 1-2nm)
• High dielectric constant preferred
• High density
• Amorphous structure required
– Inter-metal dielectric:
• Low density desired
• Low dielectric constant desired (to have reduced RC-delay)
• Quality not as critical as gate oxide
5
S. Gopalan, Amrita Viswa Vidyapeetam, 09.02.05
• The growth rate, quality, and properties of SiO2
also depend on the oxidation/deposition
technique:
– Gate oxide:
• Processed at high temperature
• Growth rate depends on ambient, temp., etc. (e.g. wet vs. dry)
• N-incorporation preferred to get higher K
– Inter-metal dielectric:
• Processed at lower temperatures
• Fluorine incorporation preferred
• Deposition rates not critical
6
S. Gopalan, Amrita Viswa Vidyapeetam, 09.02.05
Structure of Silicon Dioxide
• When the tetrahedral elements are linked in a structured
way, we get a crystalline material
• When the tetrahedral units are linked to each other
randomly, we get “amorphous” material
– Usually a more open structure with lower density
• The basic unit of SiO2 is a
Tetrahedral structure
• Each bond makes 109.5°
with others
7
S. Gopalan, Amrita Viswa Vidyapeetam, 09.02.05
Structure of Silicon Dioxide
8
S. Gopalan, Amrita Viswa Vidyapeetam, 09.02.05
Structure of Silicon Dioxide
• Thermally grown SiO2 is usually amorphous.
• The larger the fraction of bridging to non-bridging, the stronger the oxide
(e.g. dry vs. wet).
• Common impurities include water related complexes, B, P, Na, K, etc.
• B and P are network formers: reduce the bridging to non-bridging ratio
(by substituting for Si).
• Na, K are common network modifiers (interstitials).
network former
hydroxyl group
network modifier
silicon
bridging oxygen
non-bridging oxygen
9
S. Gopalan, Amrita Viswa Vidyapeetam, 09.02.05
10
S. Gopalan, Amrita Viswa Vidyapeetam, 09.02.05
SiO
2
formation
• Oxidation of Si
– Thermal oxidation (wet and dry)
– Anodization
• Deposition
– Chemical vapor deposition (CVD or MOCVD)
– Physical vapor deposition (PVD)
– Evaporation
11
S. Gopalan, Amrita Viswa Vidyapeetam, 09.02.05
Methods of Oxidation
Essentially involves heating Si wafers at high temperatures (usually 900C –
1050C) in an oxidizing ambient.
Dry oxidation - Si (s) + O
2
(g) SiO
2
(s)
Wet oxidation - Si (s) + 2H
2
O(g) SiO
2
+ 2H
2
(g)
proposed process:
1) H2O + Si-O-Si Æ Si-OH + Si-OH
2) diffusion of hydroxyl complex to SiO2 -Si interface
Wet oxidation usually results in a more open structure and hence the oxide
has lower density (ρ
SiO2
= 2.15 gm/cm
3
) than dry oxide (ρ
SiO2
= 2.25 gm/cm
3
)
900 – 1200°C
900 – 1200°C
• Thermal Oxidation
Si - OH Si - O - Si
+ Si - Si → + H
2
Si - O H Si - O - Si
12
S. Gopalan, Amrita Viswa Vidyapeetam, 09.02.05
Thermal Oxidation Furnace
Wafer loading end
The temperature ramp rates, ambient flow
rate etc, are microprocessor controlled.
CVD systems are very similar:
i.e. Gases react on wafer surface to
deposit thin films
Horizontal furnace
13
S. Gopalan, Amrita Viswa Vidyapeetam, 09.02.05
Methods of Oxidation
• Rapid Thermal Oxidation (RTO)
– Heat wafer rapidly to high temperatures and keep at high
temperatures for a very short period of time (< 2minutes) in oxidizing
ambient (O2, NO, N2O, etc)
– Ramp rates are very high ÆRoom Temp to 900-1000C in < 1minute
– Typically these furnaces can process only one wafer at a time
– Used for high-quality thin oxides
– Reaction similar to the one for dry oxidation (for O
2
ambient)
N2
Wafer
RTO Schematic
O2
Heating lamp
14
S. Gopalan, Amrita Viswa Vidyapeetam, 09.02.05
Deposition techniques for SiO2
• Chemical Vapor Deposition
In CVD, two gases are introduced onto a furnace. The
gases react close to the heated wafer surface and the
product is deposited on the wafers.
For different temperature regimes, different chemical
reactions are used
– e.g. Silane reacting with Oxygen in atmospheric pressure or low pressure
(LPCVD) at temperatures between 300C and 500C
SiH4 (g) + O2 (g) SiO2 + 2H2 (g)
used for inter-metal dielectric due to low dielectric constant and low
deposition temperature
– For 500-800C, decomposition of TEOS is used
Si (OC2H5)4 SiO2 + by products
450°C
700°C
15
S. Gopalan, Amrita Viswa Vidyapeetam, 09.02.05
Deposition techniques
• Decomposition of TEOS
– has more conformal films due to higher deposition temperatures
– Deposition rate is given by: exp (- E
a
/ kT)
– Activation energy for decomposition of TEOS is ~1.9eV while for reaction of
Silane is 0.6eV
• For higher temperatures (900C), SiO
2
is formed by reacting
dichloro silane with nitrous oxide (N2O).
SiCl
2
H
2
+ 2N
2
O SiO
2
+ 2N
2
+2HCl
900°C
16
S. Gopalan, Amrita Viswa Vidyapeetam, 09.02.05
Methods of Oxidation
• Physical Vapor Deposition
- sputter atoms from a Si target using O
2
as oxidation species.
(Electric field ionizes Ar gas into ions and electrons. These
ions impinge on target to knock off atoms which react with
oxidizing species. The product is accelerated by an electric
field to reach wafer)
Plasma
Ar
+
and e
-
Ar
Wafer
Cathode
PVD Schematic
O2
17
S. Gopalan, Amrita Viswa Vidyapeetam, 09.02.05
• Currently gate oxide thickness required is ~1nm
SiO2 Thickness
18
S. Gopalan, Amrita Viswa Vidyapeetam, 09.02.05
19
S. Gopalan, Amrita Viswa Vidyapeetam, 09.02.05
Growth of SiO2
X 0.44X
• When Si oxidizes, there is volume expansion (~2.2X)
• Diffusivity of Si in SiO2 is several orders of magnitude
smaller than diffusivity of O2
• O2 is believed to diffuse through the oxide to react with Si
at interface (tracer studies).
20
S. Gopalan, Amrita Viswa Vidyapeetam, 09.02.05
Growth of SiO2
• Overall reaction for dry oxidation.
• Pathway increases with Si vacancies.
• High doping increases charged vacancies and hence linear
oxidation rate
• At room temperature, O2 and Si are not mobile enough in SiO2
Æ hence reaction stops after a while.
21
S. Gopalan, Amrita Viswa Vidyapeetam, 09.02.05
Next class
• Deal-Grove Model for Thermal oxidation
• Rate constants
• Effect of impurities on oxidation
S. Gopalan, Amrita Viswa Vidyapeetam, 12.02.05
VLSI Fabrication
Oxidation
12.02.05
2
S. Gopalan, Amrita Viswa Vidyapeetam, 12.02.05
Topics covered in last class
• Types of SiO2 in devices
– Gate oxide, field oxide, LTO
• Oxidation / deposition techniques
– Thermal oxidation (wet and dry)
– Chemical Vapor Deposition
– Physical Vapor Deosition
• Properties and structure of SiO2
– Bridging and non-bridging oxygen
– Network formers and network modifiers
3
S. Gopalan, Amrita Viswa Vidyapeetam, 12.02.05
• Mechanism of oxidation
• Deal Grove model for thermal oxidation
• Linear and Parabolic rate constants
• Growth models for thin oxides
Topics for today
4
S. Gopalan, Amrita Viswa Vidyapeetam, 12.02.05
Growth of SiO2
X 0.44X
• When Si oxidizes, there is volume expansion (~2.2X)
• Diffusivity of Si in SiO
2
is several orders of magnitude
smaller than diffusivity of O
2
• O
2
is believed to diffuse through the oxide to react with Si
at interface (tracer studies).
Original Si
surface
5
S. Gopalan, Amrita Viswa Vidyapeetam, 12.02.05
Deal Grove model for thermal oxidation
• C represents the concentration of oxygen (atoms per unit
volume) at each position
• J represents the oxygen flux moving through the cross-
section: atoms per unit area per unit time
C
g
J
1
J
2
J
3
C
s
C
o
C
i
Si SiO2
Stagnant
Gas layer
6
S. Gopalan, Amrita Viswa Vidyapeetam, 12.02.05
Deal Grove model for thermal oxidation
• Oxygen transport across stagnant
gas layer is given by
Where h
g
is mass transport coefficient.
…. ( 1 )
• Oxygen transport across oxide layer is governed by diffusion as
given by Fick’s law:
Where D
O
is diffusivity of O
2
in the oxide and X
o
is thickness of oxide.
….. ( 2 )
J
1
= h
g
(C
g
– C
s
)
J
2
= D
o
(C
o
– C
i
) / X
o
7
S. Gopalan, Amrita Viswa Vidyapeetam, 12.02.05
Deal Grove model for thermal oxidation
• In equilibrium,
combining equations 1, 2, and 3, we have three unknowns, Cs, Co,
and Ci.
but the concentration of oxygen in oxide is given by Henry’s law:
• Where H is Henry’s gas constant and Ps is obtained from PV = nRT
• Flux due to oxygen reacting with Si at
interface is given by:
Where Ks is the reaction rate constant
J
3
= k
s
C
i
….. ( 3 )
J
1
= J
2
= J
3
….. ( 4 )
C
o
= HP
s
= HkTC
s
….. ( 5 )
8
S. Gopalan, Amrita Viswa Vidyapeetam, 12.02.05
• Where P
s
is the partial pressure of oxidizing species at the surface.
• Using equations 1 - 5, we can solve for the respective concentrations
of oxygen at surface, in the oxide and at interface:
D
X K
h
k
HP
C
o s s
g
i
+ +
=
1
HkT
hg
h =
D
X K
h
k
D
X k
HP
Co
o s s
o s
g
+ +
+
=
1
) 1 (
Where
Thickness of oxide
9
S. Gopalan, Amrita Viswa Vidyapeetam, 12.02.05
Oxidation Rate
= = =
n
j
t d
x d
R
• The growth rate is given by J/N
1
, where N
1
is the number
molecules of oxygen per unit volume of SiO
2
,
(For oxidation with O
2
, N
1
has a typical value of 2.2 x 10
22
cm
-3
)
• Integrating the above equation assuming that X
i
is the
thickness at time t = 0, we get:
….. ( 7 )
Xo
Where C
*
= HP
g
Concentration in bulk of
oxide
10
S. Gopalan, Amrita Viswa Vidyapeetam, 12.02.05
• Where
and
• Equation 7 can be rewritten as:
• Where
….. ( 8 )
Initial thickness of oxide
11
S. Gopalan, Amrita Viswa Vidyapeetam, 12.02.05
Rate constants
• For very thick oxides (or long times),
Xo
2
= B (t + τ)
• dependence is “parabolic”: (thickness)2 µ time
• characteristic of a diffusion limited process
• hence B is called parabolic rate constant
- growth rate is diffusion controlled
B = 2DC
*
/N
1
t + τ >> A
2
4 B
( ) ( ) τ
τ
+ ⋅ =

+
⋅ ≈ t B
B A
t A
t X
o
4 2
2
12
S. Gopalan, Amrita Viswa Vidyapeetam, 12.02.05
Rate constants
• For thin oxides (or short times),
Xo ~ (B/A) (t + τ);
• thickness is linearly increasing with time
hence B/A is called linear rate constant
- growth rate is controlled by reaction at interface
B/A = ksC
*
/N
1
( ) ( ) τ
τ
+ ⋅ =


|
|
.
|

\
|
+
⋅ + ⋅ ≈ t
A
B
B A
t A
t X
o
1
4
1
2
2
2
1
t + τ << A
2
4 B
13
S. Gopalan, Amrita Viswa Vidyapeetam, 12.02.05
Linear rate constant
Dependent on
reaction rate between
oxidizer and silicon (k)
– Temperature
– Si orientation
– Pressure
– Oxidizing ambient
solid solubility of oxidizer in
oxide (N
0
)
– H
2
O: 3 x 10
19
cm
-3
– O
2
: 5 x 10
16
cm
-3
B/A = ksC
s
/N
1
14
S. Gopalan, Amrita Viswa Vidyapeetam, 12.02.05
Parabolic rate constant
B = 2DC
s
/N
1
Dependent on
• diffusivity of oxidizer in oxide (D)
AND
• solid solubility of oxidizer in oxide
(N
0
)
• temperature dependence mainly
from diffusivity
• is NOT orientation dependent
• IS oxidizer dependent
15
S. Gopalan, Amrita Viswa Vidyapeetam, 12.02.05
Calculated Oxide thickness using O2
16
S. Gopalan, Amrita Viswa Vidyapeetam, 12.02.05
Pressure dependence
• Higher pressures result in increased growth rates
(increased rate constants)
17
S. Gopalan, Amrita Viswa Vidyapeetam, 12.02.05
Halogenic Oxidation
• Addition of 1 – 3% Chlorine to oxygen
– increases the growth rate than pure O2
– helps remove metallic contaminants in the form of
volatile chlorides
– Results in better interface with Si
– Better electrical characteristics (Vth, mobility)
– Better dielectric strength
• HCl used as halogen source (corrosive)
– Trichloro ethylene (TCE) – carcinogenic
– Trichloro ethane (TCA) – forms toxic COCl
2
18
S. Gopalan, Amrita Viswa Vidyapeetam, 12.02.05
Effect of HCl on parabolic rate constant
19
S. Gopalan, Amrita Viswa Vidyapeetam, 12.02.05
Effect of HCl on linear rate constant
20
S. Gopalan, Amrita Viswa Vidyapeetam, 12.02.05
Thin Oxides
• D-G model fits data for broad range of thicknesses
• But for very thin oxides (<500A), the model suggests that
we should have a constant oxidation rate
• In reality, the oxidation for very thin films is quite high
• τ can be used to compensate for this discrepancy.
• Even then, below 300A, this model fails
• Various models have been proposed.
S. Gopalan, Amrita Viswa Vidyapeetam, 12.02.05
VLSI Fabrication
Oxidation
14.02.05
2
S. Gopalan, Amrita Viswa Vidyapeetam, 12.02.05
Topics covered in last class
• Deal Grove model for oxidation
– Oxide growth rate from flux of oxygen atoms
• Linear and Parabolic Rate constants
– Oxide growth as a function of time for long and
short times (thick or thin films)
– Factors affecting rate constant (temperature,
pressure, etc..)
• Halogenic oxidation
– Effect of Cl in O2 on the growth rate and rate
constants
3
S. Gopalan, Amrita Viswa Vidyapeetam, 12.02.05
• Growth models for thin oxides
• Effect of dopants on oxidation rates
• Oxide characterization
Topics for today
4
S. Gopalan, Amrita Viswa Vidyapeetam, 12.02.05
Predicted and measured data for wet oxidation
10
0

10
1

10
-1

10
-2

10
0
10
1
10
-1

1100°C
1050°C
1150°C
Time (hours)
O
x
i
d
e

t
h
i
c
k
n
e
s
s

(
m
i
c
r
o
n
s
)
(100) silicon
steam
1
0
0
0
°
C
9
5
0
°
C
9
0
0
°
C
8
0
0
°
C
Calculated from D-G model Measured thickness
D-G model predicts the thickness well for a broad range of
parameters and oxide thickness
0.01
0.1
1
10
0.01 0.1 1 10 100
o
x
i
d
e

t
h
i
c
k
n
e
s
s

(
m
i
c
r
o
n
s
)
wet oxidation time (hours)
(100) Si
1100ºC
900ºC
1000ºC
0.01
0.1
1
10
0.01 0.1 1 10 100
o
x
i
d
e

t
h
i
c
k
n
e
s
s

(
m
i
c
r
o
n
s
)
wet oxidation time (hours)
(100) Si
1100ºC
900ºC
1000ºC
5
S. Gopalan, Amrita Viswa Vidyapeetam, 12.02.05
Problems with Deal Grove model
` Although D-G model predicts the thickness well thick
oxides, it does not correctly model thin oxide growth
` For the first 200A, the actual oxide growth rate is much
higher than predicted.
` Dry oxidation growth curves do not extrapolate back to
zero oxide thickness at zero time.
` To compensate for this discrepancy τ value can be
adjusted.
` Even then, below 300A, this model fails
` Various models have been proposed.
0.01
0.1
1
0.1 1 10
D
r
y

O
x
i
d
a
t
i
o
n

T
h
i
c
k
n
e
s
s

(
µ
m
)
time (hours)
1100ºC
1000ºC
900ºC
(100) Si
0.01
0.1
1
0.1 1 10
D
r
y

O
x
i
d
a
t
i
o
n

T
h
i
c
k
n
e
s
s

(
µ
m
)
time (hours)
1100ºC
1000ºC
0.01
0.1
1
0.1 1 10
D
r
y

O
x
i
d
a
t
i
o
n

T
h
i
c
k
n
e
s
s

(
µ
m
)
time (hours)
1100ºC
1000ºC
900ºC
(100) Si
6
S. Gopalan, Amrita Viswa Vidyapeetam, 12.02.05
Models for thin oxide growth
( I ) Enhanced arrival of oxidation species at interface:
1. Deal-Grove suggested presence of Electric field enhances
motion of diffusing species to interface
– Issue: this model requires that the diffusing species must be ionic
2. Existence of holes or “micro-channels” in oxide enhances
oxygen diffusion to interface
– Issue: this model cannot explain uniform oxide thickness across
wafer
3. Difference between thermal expansion coefficient
between Si and SiO2 causes stress which enhances
oxygen diffusion
Problem with these model: For the thin oxide regime, the
oxidation is reaction rate limited, not diffusion limited. The linear
rate constant (B/A) is independent of diffusivity.
7
S. Gopalan, Amrita Viswa Vidyapeetam, 12.02.05
Models for thin oxide growth
( II ) Increased solid solubility of O
2
in oxide:
• Causes greater reaction with interface
• Not well accepted
– Henry’s law not true for thin oxides (as it assumes that the
adsorbed oxygen does not dissociate not recombine)
( III ) Oxygen reaction at interface occurs over some
finite distance (Massoud et. al. – ref. 13, Ch 4)
• Oxygen diffuses some distance into silicon (through defects) and
reacts
• Shown to be true for very low temperatures
L is the characteristic distance over which the reaction occurs, and C is const
8
S. Gopalan, Amrita Viswa Vidyapeetam, 12.02.05
( V ) Reisman et. al. : simple power-law fit
– Volume expansion and viscous flow of SiO
2
increase
interface reaction rate
• Simple power-law fits the data well
• a and b are experimentally determined parameters
( IV ) Han and Helms model (ref. 15, Ch. 4)
– Another parallel reaction (out-diffusion of oxygen
vacancy and reaction at top of oxide surface)
• B
2
and B
2
/A
2
represent the reaction rate constants for this
second reaction
Models for thin oxide growth
9
S. Gopalan, Amrita Viswa Vidyapeetam, 12.02.05
Models for thin oxide growth
• Experimental data agrees well with Reisman, Massoud, and Han &
Helms models.
• None of the models are widely accepted.
• Since Massoud et. al. model is an extension of Deal-Grove, this
model is used in process simulators.
10
S. Gopalan, Amrita Viswa Vidyapeetam, 12.02.05
Effects of Dopants during oxidation
• Substrate usually doped prior to oxidation
• During oxidation, impurity redistributes between oxide
and silicon according to segregation coefficient, k
• If k > 1, oxide rejects impurity
– Dopant accumulates in silicon under oxide reaching maximum at
iinterface
– If impurity diffuses rapidly in SiO2, dopant rapidly removed from
interface
• If k < 1, oxide takes up dopants
– Impurity concentration at substrate decreases near interface
2 SiO
Si
C
C
k =
11
S. Gopalan, Amrita Viswa Vidyapeetam, 12.02.05
12
S. Gopalan, Amrita Viswa Vidyapeetam, 12.02.05
Effect of dopants during oxidation
Boron
• Weakens structure, and reduces viscosity
• For heavily doped substrate (C
B
> 10
20
cm
-3
), diffusivity
of oxygen enhanced
– Increase in parabolic rate constant
Phosphorous
• k = 10
• Phosphorous pile up at interface causes increased
reactivity with oxygen
– Rapid increase in linear rate constant
– Parabolic rate constant shows only small increase
13
S. Gopalan, Amrita Viswa Vidyapeetam, 12.02.05
Problems with thermal oxidation: OSF
• Oxidation induced stacking faults (OSF) caused by
creation of large number of silicon self-interstitials
• OSF usually lies on {111} and found close to Si-SiO2
interface
• Act as gettering sites for heavy metal impurities
– Cause excess leakage of device
• Length of stacking fault is linearly proportional to
oxidation time
• density can vary from ~0 to 10
7
/ cm
2
• Any process that injects Si vacancies inhibit
formation of OSF: e.g. nitridation
14
S. Gopalan, Amrita Viswa Vidyapeetam, 12.02.05
15
S. Gopalan, Amrita Viswa Vidyapeetam, 12.02.05
Next class
• Characterization of Oxides
– Thickness
– Dielectric strength
• Si-SiO2 interface
• Diffusion
16
S. Gopalan, Amrita Viswa Vidyapeetam, 12.02.05
S. Gopalan, Amrita Viswa Vidyapeetam, 31.01.05
VLSI Fabrication
Oxide characterization
Photo Lithography
21.02.05
2
S. Gopalan, Amrita Viswa Vidyapeetam, 31.01.05
Topics of last class
• Problems with DG oxidation model
• Thin oxide growth models
• Effect of dopants during oxidation
• Oxidation induced stacking faults
3
S. Gopalan, Amrita Viswa Vidyapeetam, 31.01.05
Oxide characterization methods
• Thickness characterization
– Optical method
– Electrical method
• Interface characterization
– Interface state density
– Charge traps
• Photo Lithography
– Steps in lithography
– Mask making
– Pattern transfer
4
S. Gopalan, Amrita Viswa Vidyapeetam, 31.01.05
Microscopic techniques
• Create a step in the oxide
– Use lithography to create a step by etching away
portions of the oxide
– For thickness > 1000A, use SEM
– For thickness < 1000A, use TEM
• Surface profilometer
– Mechanically scan wafer with a needle stylus
– Deflection of needle is measured and amplified as a
function of position
– Very good resolution ( ~ few angstroms)
5
S. Gopalan, Amrita Viswa Vidyapeetam, 31.01.05
Microscopic techniques
• Optical method 1
– Dip part of wafer in dilute HF to remove oxide
completely
– A gradation of thickness exists between etched and
unetched oxides
– Thickness obtained from color sequence
• Optical method 2 - ellipsometry
– Polarized coherent light is reflected off the oxide
surface at some angle
– Reflected light and intensity measured as a function
of polarization angle
– Comparing intensities of incident & reflected light and
change in polarization angle, film thickness and index
of refraction can be determined
6
S. Gopalan, Amrita Viswa Vidyapeetam, 31.01.05
Microscopic techniques
• Optical method 3 – interference method
– Incident light almost normal to wafer
– Intensity of reflected light measured as a function of λ
– Optical maximum when incoming and outgoing waves
interfere constructively for some wavelength
– Destructive interference Æminima
– ∆λ Between maximum and minimum measured
– n is the index of refraction of oxide
– Thickness down to a few hundred angstroms
t
SiO2
= ∆λ / 2n
ox
7
S. Gopalan, Amrita Viswa Vidyapeetam, 31.01.05
Thickness by Electrical method
• Breakdown voltage
– Use metal electrode on top of oxide
– Apply continuous voltage to electrode and measure
current
– Initially current increases slowly and
– Suddenly current starts increasing rapidly Æ
breakdown
– From breakdown voltage and breakdown field
(12MV/cm for SiO2), thickness can be determined.
Si
Vg
E
SiO2
= V
BD
/ t
ox
Ig
Vg
V
bd
8
S. Gopalan, Amrita Viswa Vidyapeetam, 31.01.05
Thickness by Electrical method
• C-V measurement
– Use metal electrode on top of oxide
– Measure capacitance in accumulation region
– For p-type substrate, you have to apply –ve voltage
for accumulation
– Knowing K for SiO2 to be 3.9, we can determine t
ox
Si
Vg
C
SiO2
= ( A. ε
o
.K
SiO2
)/ t
ox
C
Vg
-2V
+2V
Where ε
o
is the permittivity of free space, A is
area of electrode, and K is dielectric constant
9
S. Gopalan, Amrita Viswa Vidyapeetam, 31.01.05
Q
ot
– due to defects in SiO2
Q
m
– due to processing
Q
it
– due to sudden
termination of silicon lattice at
Si-SiO2 interface
Q
f
– due to presence of ionic
Si and dangling Si bonds
All these charges affect the
electrical characteristics of
the oxide
Charges in oxide and Si-SiO2 interface
10
S. Gopalan, Amrita Viswa Vidyapeetam, 31.01.05
Electrical characterization of oxides
• TDDB (time dependent dielectric breakdown)
– Constant voltage (other techniques - constant current, or ramped
voltage techniques)
– Apply constant voltage for extended period of time, and monitor
current through oxide
– Current decreases due to electron trapping in oxide bulk
– Breakdown due to accumulated trapped positive charge near
interface
– Area under I – t curve gives total charge to breakdown
I (A)
t (sec)
I (A)
t (sec)
Less
trapped
charge
more
trapped
charge
11
S. Gopalan, Amrita Viswa Vidyapeetam, 31.01.05
• Qm
– Cause a shift in the CV curve laterally
– Can be determined from the ∆Vg
– Qm determined from bias temperature stressing
C
T
C
T
C
ox
C
ox
C
ox
before BTS before BTS after BTS after BTS
∆Q
m
/ C
ox
∆Q
m
/ C
ox
p-type
substrate
voltage (metal wrt substrate)
c
a
p
a
c
i
t
a
n
c
e
p-type
substrate
voltage (metal wrt substrate)
c
a
p
a
c
i
t
a
n
c
e
• measure C-V curves
before and after BTS
• stress- heat sample to
100C and apply electric
field for 10-20min
•Q
m
≈ C
ox
x ∆V
t
• ρ ≈ Q
m
/ t
ox
A
cap
q
12
S. Gopalan, Amrita Viswa Vidyapeetam, 31.01.05
• Interface trapped charge
– Due to unsatisfied bonds at interface
– Measurement difficult
– Decreases the slope of C-V profile
– Determined by comparing actual CV with theoretical
CV (obtained from oxide thickness and
semiconductor work function, and doping levels)
– High temperature annealing can reduce interface
trapped charge
C
Vg
-2V
+2V
Due to interface
states
13
S. Gopalan, Amrita Viswa Vidyapeetam, 31.01.05
PHOTO LITHOGRAPHY
14
S. Gopalan, Amrita Viswa Vidyapeetam, 31.01.05
Lithography
• Process of transferring patterns of geometric shapes
on a mask to a thin layer of radiation sensitive
material (called photo resist) covering the surface of
wafer
• Two step process
– Transfer pattern from mask on to photo resist (PR)
– Transfer of pattern from PR to wafer by etching
• Device layout is broken into several layers of
information
• Each layer is a map for the location of one film on IC
15
S. Gopalan, Amrita Viswa Vidyapeetam, 31.01.05
Steps in Mask fabrication
Define chip function
Breakdown into sub-functions
Layout of sub-functions on floor plan using
design rules
Construct high-level model to test
functionality and performance
Make adjustments to design
Transfer design to pattern generator
16
S. Gopalan, Amrita Viswa Vidyapeetam, 31.01.05
• Same size as finished chip or an integral factor (5x or
10x) of final chip
• During exposure, the image size is reduced.
• Typically 150mm square
• Made of fused silica
• Essential properties
– High degree of optical transparency
– Small thermal expansion coefficient
– Flat and polished surface
– Resistant to scratches
• Chromium is used as opaque layer
• Typically 15-20 masks are used in a process sequence
Mask
17
S. Gopalan, Amrita Viswa Vidyapeetam, 31.01.05
• Electron beam used to create the pattern on the mask due
to its high precision
• The quartz is first covered with chrome followed by PR
• E-beam is raster scanned on to PR
• Un-wanted PR is removed and chromium is etched
S. Gopalan, Amrita Viswa Vidyapeetam, 23.02.05
VLSI Fabrication
Photo Lithography
23.02.05
2
S. Gopalan, Amrita Viswa Vidyapeetam, 23.02.05
Topics of last class
• Characterization of oxides
– Thickness
– Breakdown
– Interface states
• Charges in SiO2 and Si-SiO2 interface
• Photolithography
– Steps in mask fabrication
3
S. Gopalan, Amrita Viswa Vidyapeetam, 23.02.05
Steps in Mask fabrication
Define chip function
Breakdown into sub-functions
Layout of sub-functions on floor plan using
design rules
Construct high-level model to test
functionality and performance
Make adjustments to design
Transfer design to pattern generator
4
S. Gopalan, Amrita Viswa Vidyapeetam, 23.02.05
• The quartz is first covered with chrome followed by PR
• Electron beam used to create the pattern on the mask due
to its high precision
• Computer driven e-beam is raster scanned on to PR
• Un-wanted PR is removed and chromium is etched
5
S. Gopalan, Amrita Viswa Vidyapeetam, 23.02.05
Overlay errors between two patterns
• goal: align two “identical” patterns one on top of the
other
σ
λ
level 1
level 2
• λ : pure registration error
• σ : distortion error
– overlay error: sum of all errors
• really a statistical quantity
• rule of thumb: total overlay error not more than 1/3 to 1/5
of minimum feature size
• what can go wrong??
6
S. Gopalan, Amrita Viswa Vidyapeetam, 23.02.05
Steps in standard lithography process
Dehydration bake
Adhesion promoter application
Resist application
Soft bake or pre-bake
Aligning and Light Exposure
Develop
Hard bake or Post-bake Etching
Wafer with film
7
S. Gopalan, Amrita Viswa Vidyapeetam, 23.02.05
Photo Resist (PR)
• Is a radiation sensitive material which changes chemically
on exposure to light
• Usually a carbon based organic molecule
• Two types of resist:
– Positive
• Regions of resist exposed to light dissolve quickly in ‘developer’
• Unexposed regions remain unchanged and are not removed by
developer
– Negative
• Regions exposed to light are hard to remove by developer
• Unexposed regions are easily removed by developer
• Positive resists result in better resolution than negative
resist
film to be patterned
substrate (with topography!)
film to be patterned
substrate (with topography!)
Photo resist
Exposed regions
8
S. Gopalan, Amrita Viswa Vidyapeetam, 23.02.05
Positive and Negative resist
mask mask
exposing
radiation
exposing
radiation
made insoluble made insoluble made soluble made soluble
film to be patterned
mask blank: transparent,
mechanically rigid
masking layer:
opaque,
patternable
masking layer:
opaque,
patternable
develop
etch
NEGATIVE POSITIVE
photoresist photoresist
9
S. Gopalan, Amrita Viswa Vidyapeetam, 23.02.05
Components of PR
• Matrix material or resin binder
– provides mechanical properties such as adhesion and
etch resistance
– Inert to incident radiation
• Sensitizer or inhibiter or PAC
– Inhibits dissolution in developer
– Photo active compound absorbs light (visible or UV)
and causes photo-chemical change
• Solvent
– Keeps the photo resist as a liquid
10
S. Gopalan, Amrita Viswa Vidyapeetam, 23.02.05
Characteristics of PR
• Photoresist is an organic molecule
– Aromatic rings (closed chain hydrocarbons)
– long chain polymers
• Sensitivity
– Amount of light energy required to create a chemical
change
– Higher sensitivity results in quicker developing
• Resolution
– Smallest feature size that can be reproduced on PR
without distortion
11
S. Gopalan, Amrita Viswa Vidyapeetam, 23.02.05
Basic pattern transfer techniques
• contact
gap
mask
photoresist
optical imaging system
• proximity
• Imaging/
Projection
12
S. Gopalan, Amrita Viswa Vidyapeetam, 23.02.05
• Contact printing is capable of high resolution but has unacceptable defect
densities.
• Proximity printing cannot easily print features below a few mm (except for
x-ray systems).
• Projection printing provides high resolution and low defect densities and
dominates today.
• Typical projection systems use reduction optics (2X - 5X), step and repeat
or step and scan mechanical systems, print » 50 wafers/hour and cost $5 -
10M.
Usually 4X
or 5X
Reduction
1:1 Exposure Systems
13
S. Gopalan, Amrita Viswa Vidyapeetam, 23.02.05
Resolution of Imaging Systems
• contact
– “shadow” formation, “no”
diffraction
λ ⋅ ≈ gap l
2
3
min
• proximity
– some diffraction, “sharp” filter
cut-off, flat response in
passband
• projection:
- low pass filter, “smooth”
decrease in passband
contact
projection
illumination, intensity I
o
, wavelength λ
position
i
n
t
e
n
s
i
t
y
I
o
position
i
n
t
e
n
s
i
t
y
I
o
I
o
proximity
l
min
≈ √(g • λ)
14
S. Gopalan, Amrita Viswa Vidyapeetam, 23.02.05
Optics – Basics of Diffraction
• Ray tracing (assuming light travels in straight lines as particle) works
well as long as the dimensions are large compared to λ.
• At smaller dimensions, diffraction effects dominate (light treated as a
wave).
• Diffraction is bending of light waves around corners.
• If the aperture is on the order of l, the light spreads out after passing
through the aperture. (The smaller the aperture, the more it spreads
out.)
15
S. Gopalan, Amrita Viswa Vidyapeetam, 23.02.05
• If we want to image the aperture on an image plane (resist), we can
collect the light using a lens and focus it on the image plane.
• But the finite diameter of the lens means some information is lost
(higher frequency components).
16
S. Gopalan, Amrita Viswa Vidyapeetam, 23.02.05
• A simple example is the image formed by a small circular aperture
(Airy disk).
• Note that a point image is formed only if λ→0, f →0 or d→∞.
• Diffraction is usually described in terms of two limiting cases:
– Fresnel diffraction - near field.
– Fraunhofer diffraction - far field.
S. Gopalan, Amrita Viswa Vidyapeetam, 23.02.05
VLSI Fabrication
Photo Lithography
23.02.05
2
S. Gopalan, Amrita Viswa Vidyapeetam, 23.02.05
Topics of last class
• Characterization of oxides
– Thickness
– Breakdown
– Interface states
• Charges in SiO2 and Si-SiO2 interface
• Photolithography
– Steps in mask fabrication
3
S. Gopalan, Amrita Viswa Vidyapeetam, 23.02.05
Steps in Mask fabrication
Define chip function
Breakdown into sub-functions
Layout of sub-functions on floor plan using
design rules
Construct high-level model to test
functionality and performance
Make adjustments to design
Transfer design to pattern generator
4
S. Gopalan, Amrita Viswa Vidyapeetam, 23.02.05
• The quartz is first covered with chrome followed by PR
• Electron beam used to create the pattern on the mask due
to its high precision
• Computer driven e-beam is raster scanned on to PR
• Un-wanted PR is removed and chromium is etched
5
S. Gopalan, Amrita Viswa Vidyapeetam, 23.02.05
• Each successive layer has to be aligned with the previous
layer (for e.g. the gate electrode has to come on top of
gate oxide accurately)
• Each mask contains alignment marks which help in
aligning the layers on top of each other.
• Important alignment features:
– Resolution:
• ability of PR to accurately transfer patterns on to film
underneath
• Is the minimum feature size that can be transferred with
minimal tolerance
• Measured in terms of 3-sigma (standard deviation of minimum
feature size)
Aligning using Masks
6
S. Gopalan, Amrita Viswa Vidyapeetam, 23.02.05
• Important alignment features:
– Registration:
• Measure of overlay accuracy from layer to layer
• Measured in terms of 3-sigma
– Throughput:
• Number of wafers processed per hour
• For industry, this number has to be sufficiently high while
maintaining good resolution and registration
• Usually alignments are automated
Aligning using Masks
7
S. Gopalan, Amrita Viswa Vidyapeetam, 23.02.05
Overlay errors between two patterns
• goal: align two “identical” patterns one on top of the
other
σ
λ
level 1
level 2
• λ : pure registration error
• σ : distortion error
– overlay error: sum of all errors
• really a statistical quantity
• rule of thumb: total overlay error not more than 1/3 to 1/5
of minimum feature size
• what can go wrong??
8
S. Gopalan, Amrita Viswa Vidyapeetam, 23.02.05
Basic pattern transfer techniques
• contact
gap
mask
photoresist
optical imaging system
• proximity
• Imaging/
Projection
9
S. Gopalan, Amrita Viswa Vidyapeetam, 23.02.05
• Contact printing is capable of high resolution but has unacceptable defect
densities.
• Proximity printing cannot easily print features below a few mm (except for
x-ray systems).
• Projection printing provides high resolution and low defect densities and
dominates today.
• Typical projection systems use reduction optics (2X - 5X), step and repeat
or step and scan mechanical systems, print » 50 wafers/hour and cost $5 -
10M.
Usually 4X
or 5X
Reduction
1:1 Exposure Systems
10
S. Gopalan, Amrita Viswa Vidyapeetam, 23.02.05
Resolution of Imaging Systems
• contact
– “shadow” formation, “no”
diffraction
λ ⋅ ≈ gap l
2
3
min
• proximity
– some diffraction, “sharp” filter
cut-off, flat response in
passband
• projection:
- low pass filter, “smooth”
decrease in passband
contact
projection
illumination, intensity I
o
, wavelength λ
position
i
n
t
e
n
s
i
t
y
I
o
position
i
n
t
e
n
s
i
t
y
I
o
I
o
proximity
l
min
≈ √(g • λ)
11
S. Gopalan, Amrita Viswa Vidyapeetam, 23.02.05
Optics – Basics of Diffraction
• Ray tracing (assuming light travels in straight lines as particle) works
well as long as the dimensions are large compared to λ.
• At smaller dimensions, diffraction effects dominate (light treated as a
wave).
• Diffraction is bending of light waves around corners.
• If the aperture is on the order of l, the light spreads out after passing
through the aperture. (The smaller the aperture, the more it spreads
out.)
12
S. Gopalan, Amrita Viswa Vidyapeetam, 23.02.05
• If we want to image the aperture on an image plane (resist), we can
collect the light using a lens and focus it on the image plane.
• But the finite diameter of the lens means some information is lost
(higher frequency components).
13
S. Gopalan, Amrita Viswa Vidyapeetam, 23.02.05
• A simple example is the image formed by a small circular aperture
(Airy disk).
• Note that a point image is formed only if λ→0, f →0 or d→∞.
• Diffraction is usually described in terms of two limiting cases:
– Fresnel diffraction - near field.
– Fraunhofer diffraction - far field.
14
S. Gopalan, Amrita Viswa Vidyapeetam, 23.02.05
Contact and Proximity Systems
( Fresnel Diffraction)
• Contact printing systems operate in the near field or Fresnel diffraction
regime.
• There is always some gap g between the mask and resist.
• The aerial image can be constructed by imagining point sources within
the aperture, each radiating spherical waves (Huygens wavelets).
15
S. Gopalan, Amrita Viswa Vidyapeetam, 23.02.05
Fresnel diffraction
• Interference effects and diffraction result in “ringing” and
spreading outside the aperture.
• Fresnel diffraction applies when
• Within this range, the minimum resolvable feature size is
For e.g.
W
min
16
S. Gopalan, Amrita Viswa Vidyapeetam, 23.02.05
Projection Systems
( Fraunhofer Diffraction)
• These are the dominant systems in use today.
• Performance is usually described in terms of
– resolution
– depth of focus
– modulation transfer function
– alignment accuracy
– Throughput
• The numerical aperture of the lens is by definition
Where α is one half angle of acceptance of objective
lens and n is refractive index of medium
αα
α sin ⋅ = n NA
17
S. Gopalan, Amrita Viswa Vidyapeetam, 23.02.05
Projection Systems (Fraunhofer Diffraction)
• Resolution is given by Raleigh’s criterion:
• k1 is an experimental parameter which depends on the lithography
system and resist properties and is » 0.6 - 0.8.
W
min
=
Obviously resolution can
be increased by:
• decreasing λ
• increasing NA (bigger
lenses)
18
S. Gopalan, Amrita Viswa Vidyapeetam, 23.02.05
Projection Systems
( Fraunhofer Diffraction)
• However, higher NA lenses also decrease the depth of
focus:
• k
2
is usually experimentally determined.
• Usually, it is better to decrease wavelength of light.
• Another useful concept is the modulation transfer
function or MTF, defined as shown below:
– Can be thought of as a measure of the optical contrast of areal
image
19
S. Gopalan, Amrita Viswa Vidyapeetam, 23.02.05
Projection Systems (Fraunhofer Diffraction)
•Higher the MTF, better
the contrast
•MTF dependent on
diffraction grating
20
S. Gopalan, Amrita Viswa Vidyapeetam, 23.02.05
Spatial Coherence
• Finally, another basic concept is the spatial coherence of
the light source.
• The spatial coherence of the system is defined as:
– Typically, S ~ 0.5 to 0.7 in modern systems.
Or also by