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PROBLEMA 2.

47

F1

library ieee;
use ieee.std_legic_1164.all;
ENTITV problena IS
PORT(
x1 : in std_logic;
x2 : in std_logic;
x3 : in std_logic;
x4 : in std_logic;
f : out std_logic);
END problena;

architecture problemaA of problema is


signal aux1 : std_logic;
signal aux2 : std_logic;
signal aux3 : std_logic;
signal aux4 : std_logic;
signal aux5 : std_logic;
begin
aux1 <= x1 and not x3;
aux2 <= x2 and not x3;
aux3 <= not x3 and not x4;
aux4 <= x1 and x2;
aux5 <= x1 and not x4;
F <= aux1 or aux2 or aux3 or aux4 or aux5;
end problemaA;

F2

library ieee;
use ieee.std_logic_1164.all;
EHTITY problemA IS
PORT(
x1 : in std_logic;
x2 : in std_logic;
x3 : in std_logic;
x4 : in std_logic;
f : out std_logic);
END problemaA;

architecture solucion of problemaA is


signal aux1 : std_logic;
signal aux2 : std_logic;
signal aux3 : std_logic;
begin
aux1 <= x1 or not x3;
aux2 x1 or x2 or not x4;
aux3 x2 or not x3 or not x4;
F <= aux1 and aux2 and aux3;
end solucion;

PROBLEMA 4.38

library ieee;
use ieee.std_logic_1164.all;
entity problema1 is
port (
x1 : in std_logic;
x2 : in std_logic;
x3 : in std_logic;
x4 : in std_logic;
f : out std_logic);
end problema1;

architecture solucion of problema1 is


begin
F <= ((not x3 and not x4) or (not x1 and not x3) or (not x2 and not x3) or (not x1 and not x2 and not
x4) or (x2 and not x4) or (x1 and x3 and x4) or (x1 and x2 and x3));
end solucion;

PROBLEMA 4.39

library ieee;
use ieee.std_logic_1164.all;
entity problema2 is
port (
x1 : in std_logic;
x2 : in std_logic;
x3 : in std_logic;
x4 : in std_logic;
f : out std_logic);
end problema2;

architecture solucionario of problema2 is


begin
f <= ((not x1 and not x3) or (not x1 and x2 and x4) or (x1 and x2 and x3));
end solucionario;
PROBLEMA 4.40

library ieee;
use ieee.std_logic_1164.all;
entity problema3 is
port (
x1 : in std_logic;
x2 : in std_logic;
x3 : in std_logic;
x4 : in std_logic;
f : out std_logic);
end problema3;

architecture solucion of problema3 is


begin
f <= (not x1 or x3) and (x1 or not x2 or not x3 or x4);
end solucion;

PROBLEMA 4.41
library ieee;
use ieee.std_logic_1164.all;
entity problema4 is
port (
x1 : in std_logic;
x2 : in std_logic;
x3 : in std_logic;
x4 : in std_logic;
f : out std_logic);
end problema4;

architecture solucion of problema4 is


begin
f <= (x2 or not x3) and (not x1 or not x3 or x4);
end solucion;
PROBLEMA 5.51

library ieee;
use ieee.std_logic_1164.all;
use work.fulladd.package.all;

entity CircuitComp is
port (
x,y : in std_logic.vector (3 downto 0);
v,n,z : out std_logic);
end CircuitComp;

architecture Estructura of CircuitComp is


signal s : std_logic.vector (3 downto 0);
signal c : std_logic.vector (1 to 4);
begin
stage 0 : fulladd part map(‘1’ ,x(0) ,not y(0) ,s(0) ,c(1);
stage 1 : fulladd part map(c(1) ,x(1) ,not y(1) ,s(1) ,c(2);
stage 2 : fulladd part map(c(2) ,x(2) ,not y(2) ,s(2) ,c(3);
stage 3 : fulladd part map(c(3) ,x(3) ,not y(3) ,s(3) ,c(4);

v <= c(4) xor c(3);


n <= s(3);
z <= ‘1’ when s(3 downto 0) else ‘0’;
end Estructura;
PROBLEMA 5.17
LIBRARY ieee;
USE ieee.std_logic.1164.all ;
ENTITY problem IS
PORT( Input : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Output : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) :
END problem ;

ARCHITECTURE LogicFunc OF problem IS


BEGIN
WITH Input SELECT
Output<= "0001" WHEN "0101".
"0010" WHEN "0110".
"0011" WHEN "0110",
"0010" WHEN "1001”,
"0100" WHEN "1010".
"0110“ WHEN "1011“.
“0011" WHEN "1101“.
"0110" WHEN "1110".
"1001” WHEN "1111".
"0000” WHEN OTHERS ;
END LogicFunc ;
PROBLEMA 2.48

F1
library ieee;
use ieee.std_legic_1164.all;
entity problema5 is
port (x1,x2,x3,x4 : in std_logic;
f : out std_logic};
end problema5;

architecture solucion of problema5 is


begin
F <= ((x1 and x3) or (not x1 and not x3)) or ((x2 and x4) or (not x2 and not x4);
end solucion;

F2
library ieee;
use ieee.std_logic_1164.all;
entity problem6 is
port (x1,x2,x3,x4 : in std_logic;
f2 : out std_logic);
end problem6;

architecture solucion of problem6 is


begin
f2 <= (x1 and x2 and hot x3 and not x4) or (not x1 and x2 and x3 and x4) or (x1 and not x2 and not
x3 and x4) or (not x1 and x2 and x3 and not x4);
end solucion;